TD2 Corrige [PDF]

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Cours/TD  VHDL   OPERATEURS  ARITHMETIQUES   1)  Recopier,  compiler,  écrire  le  testbench    et  simuler  le  code  du  composant  décrit   ci-­dessous  :   ----------------------------------library ieee; use ieee.std_logic_1164.all; entity add4 is port (r0:in std_logic; a,b: in std_logic_vector ( 3 downto 0); s: out std_logic_vector (4 downto 0)); end add4; architecture archi of add4 is signal r: std_logic_vector(4 downto 0); component c2 port(a,b,rin: in std_logic; s, rout: out std_logic); end component; begin r(0) a(i), b=> b(i), rout=>r(i+1), s=>s(i)); end generate; end archi; ----------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity add4_tb is end add4_tb; architecture archi of add4_tb is signal rin: std_logic; signal entree1, entree2: std_logic_vector(3 downto 0); signal sortie: std_logic_vector(4 downto 0); component add4 port (r0:in std_logic; a,b: in std_logic_vector ( 3 downto 0); s: out std_logic_vector (4 downto 0)); end component; begin uut: add4 port map (a=> entree1, b => entree2, r0 => rin, s => sortie); rin