S-R - To - D Flip-Flop Conversion VHDL Code [PDF]

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S-R_TO_D FLIP FLOP CONVERSION VHDL CODE 

library IEEE;  use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------------------entity SR_to_D is Port ( D,clock,reset : in STD_LOGIC; Q,Q1 : inout STD_LOGIC); end SR_to_D;

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Library ieee declaration. In “ieee” library std_logic_1164 package is declared for std_logic data types (predefined data types).

Entity describes circuit external ports. D, clock, reset: - input port to D flip flop. Q, Q1: - output port to D flips flop.

--------------------------------------------------------architecture structural_con of SR_to_D is --------------------------------------------------------component s_rff  Component (s_rff) declaration.  Declarative part of D flip-flop’s architecture. port (s,r,clk,rst:in std_logic;  Components represent the structure of x,y:inout std_logic); converted flip-flop. end component; ---------------------------------------------------------Architecture begins. begin ------------------------------------------------------------------------ 

ff: s_rff port map (D,not D,clock,reset,Q,Q1); -------------------------------------------------------------------------end structural_con;

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Statements part of the architecture. Components are port mapped to perform D flip flop operation.

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