D - To - S-R Flip-Flop Conversion VHDL Code [PDF]

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D_TO_S-R FLIP FLOP CONVERSION VHDL CODE 

library IEEE;  use IEEE.STD_LOGIC_1164.ALL; --------------------------------------------------------entity D_to_SR is Port ( S,R,clock,reset : in STD_LOGIC; Q,Q1 : inout STD_LOGIC); end D_to_SR;

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Library ieee declaration. In “ieee” library std_logic_1164 package is declared for std_logic data types (predefined data types).

Entity describes circuit external ports. S, R, clock, reset: - input port to S-Rflipflop. Q, Q1: - output port to S-R flip-flop. q:- present state, qbar: - next state.

--------------------------------------------------------architecture structural_con of D_to_SR is --------------------------------------------------------signal s1:std_logic;  Signal s1is declared to hold a particular value. These are acting as inout ports. ----------------------------------- Component (d_ff) declaration. component d_ff is  Declarative part of S-R flip-flop’s port (d,clk,rst:in std_logic; architecture. x,y:out std_logic);  Components represent the structure of end component; converted flip-flop. -------------------------------------------------------Architecture begins. begin ------------------------------------------------------------------------s1