Lenovo Idepad Miix 520-12IKB 1702B 3nod Miix510 Rev V01 Schematic - BoardView PDF [PDF]

Zitiervorschau

NGEF(KEY E) WIFI/BT MODULE

PCle X4 USB2.0

GSPI

Fingerprint connector

12C

FPC to touch panel

Power LED Hall sensor

Changer

8

7

6

5

4

3

2

1

TABLE OF CONTENTS D

C

B

A

01 -- COVER PAGE 02 -- TABLE OF CONTENTS 03--SKL-U(1/12)DDI,MISC,XDP,EDP 04--SKL-U(2/12)DDR4 05--SKL-U(3/12)SPI,ESPI,SMB,LPC 06--SKL-U(4/12)HDA,EMMC,SD 07--SKL-U(5/12)CLK,GPIO 08--SKL-U(6/12)GPIO 09--SKL-U(7/12)PCIE,USB,SATA 10--SKL-U(8/12)Power 11--SKL-U(9/12)Power 12--SKL-U(10/12)Power,SVID 13--SKL-U(11/12)GND 14--SKL-U(12/12)RSVD 15--SOC (DECOUPLING) 16--NA 17--NA 18--NA 19--DDR4_CHA 20--DDR4_CHB 21--DDR4 Decoupling 22--NA 23--RF / EMC Solution 24 -- SYSTEM FLASH 25 -- NC_EMMC 26 -- PCIE SSD MODULE 27 -- NC_MICRO-SD CARD 28 -- NC_SD CARD POWER 29 -- CPU THERMAL SENSOR 30 -- FAN conn

31 -- Finger print 32 -- NA 33 -- NA 34 -- NC_HDMI LEVEL SHIFTERS 35 -- NC_HDMI CONNECTOR 36 -- DISPLAY 37 -- TOUCH PANEL AND DOCK 38 -- SENSORS & LID 39 -- FRONT AND REAR CAMERA CON 40 -- CAMERA DISCRETE CONTROLL 41 -- TPM 42 -- USB3.0 CONN 43 -- WLAN WIFI BT MODULE 44 -- WWAN MODULE 45 -- MICRO SIM 46 -- AUDIO CODEC 47 -- AUDIO-MIC AND SPKRS 48 -- IO board CONN 49 -- DC JACK 50 -- EMBEDDED CONTROLLER 51 -- BUTTON & LED 52 -- TYPE-C MULTIPLEXER 53 -- TYPE-C PD CONTROLLER 54 -- NC_TYPE-C BOOST VR 55 -- TYPE-C CONNECTOR 56 -- UART CONN & HOLE & CLIP 57 -- HW Change list 58--PWR_DCIN/BATT CONN 59--PWR_CHARGER(OZ8690) 60--PWR-+V5P0A / +V3P3A

61--PWR-DDR 62--PWR-+V2P5U_VPP 63--PWR-+1.0V_PRIM 64--PWR-NA 65--PWR-+1.8V_PRIM 66--PWR-CPU VR IC 67--PWR-VCC_CORE/GT/SA 68--PWR-Block Diagram 69--PWR_Change list

C

B

A

Miix510

Project: Size

sky_y_mrd._

7

6

5

4

Title:

Custom Date:

Wed Jun 03 11:22:42 2015

8

Jacky

Engineer:

BPAGE DRAWING

INTERNAL ONLY

D

3

2

Rev

TABLE OF CONTENTS

Tuesday, June 27, 2017

Sheet

2

of 1

V01 69

A

B

C

D

UC1A

E

SKL-U Rev_0.53

E55 F55 E58 F58 F53 G53 F56 G56

52 52 52 52 52 52 52 52

1

+V3P3A

C50 D50 C52 D52 A50 B50 D51 C51

DDI2_TX0_DN DDI2_TX0_DP DDI2_TX1_DN DDI2_TX1_DP DDI2_TX2_DN DDI2_TX2_DP DDI2_TX3_DN DDI2_TX3_DP

DDI1_TXN[0] DDI1_TXP[0] DDI1_TXN[1] DDI1_TXP[1] DDI1_TXN[2] DDI1_TXP[2] DDI1_TXN[3] DDI1_TXP[3]

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

DDI2_TXN[0] DDI2_TXP[0] DDI2_TXN[1] DDI2_TXP[1] DDI2_TXN[2] DDI2_TXP[2] DDI2_TXN[3] DDI2_TXP[3]

DDI

EDP_AUXN EDP_AUXP

EDP

EDP_DISP_UTIL DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

DISPLAY SIDEBANDS

No need HDMI TP1064

R1092 2.2K 5% R0402_N I

DDI1_DDC_SDA

TP1063

TP_DDI2_DDC_SCL DDI2_DDC_SDA

+1.0VS_VCCIO 37 R1009 R0402

N7 N8 N11 N12

TOUCH_PANEL_RESET_N 24.9R 1%

L13 L12

EDP_COMP I

E52

GPP_E18/DDPB_CTRLCLK GPP_E19/DDPB_CTRLDATA

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3 GPP_E17/EDP_HPD

GPP_E20/DDPC_CTRLCLK GPP_E21/DDPC_CTRLDATA GPP_E22/DDPD_CTRLCLK GPP_E23/DDPD_CTRLDATA

EDP_BKLTEN EDP_BKLTCTL EDP_VDDEN

1 OF 20

EDP_RCOMP

C47 C46 D46 C45 A45 B45 A47 B47 E45 F45

EDP_TX0_SOC_DN EDP_TX0_SOC_DP EDP_TX1_SOC_DN EDP_TX1_SOC_DP EDP_TX2_SOC_DN EDP_TX2_SOC_DP EDP_TX3_SOC_DN EDP_TX3_SOC_DP

36 36 36 36 36 36 36 36

EDP_AUX_SOC_DN EDP_AUX_SOC_DP

36 36

B52 1 G50 F50 E48 F48 G46 F46 L9 L7 L6 N9 L10

DDI2_AUX_DN DDI2_AUX_DP

DDI1_HPD DDI2_HPD TP_SMC_EXTSMI_N SMC_RUNTIME_SCI_N EDP_HPD

52 52

No need HDMI

TP9991 DDI2_HPD TP1049

50,53

SMC_RUNTIME_SCI_N EDP_HPD 36

R12 R11 U13

EDP_BKLT_EN 36 EDP_BKLT_PWM 36 EDP_VDD_EN 36

50

From eDP

SKL-U_BGA1356 @ +1.0VS_VCCSTG

R1024 1K R0402 5% I

+1.0V_VCCST 50,66 R1021

1K

THERMTRIP_SOC_N

R0402_N

1%

I

PROCHOT_N

UC1D

SKL-U Rev_0.53

TP1019 50

PECI_EC

R1022 R1023

43R 499R

R0402_N1% R0402 1%

I I

CRB install 499R,ARMOUR install 0R

CATERR_SOC_N PECI_SOC H_PROCHOT#_R THERMTRIP_SOC_N

D63 A54 C65 C63 A65 C55 D55 B54 C56

2

5/17 update

37 7,31 R1025 R1026 RC7 RC8

47 WOV_KILL_N TOUCH_PANEL_INT_N HW_ID3 43 BT_RF_KILL_N 49.9R 49.9R 49.9R 49.9R

R0402 R0402 R0402 R0402

1% 1% 1% 1%

A6 A7 BA5 AY5

CPU_POPIRCOMP AT16 PCH_OPIRCOMP AU16 EDRAM_OPIO_RCOMP H66 EOPIO_RCOMP H65

I I I I

CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#

JTAG

PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST#

CPU MISC

BPM#[0] BPM#[1] BPM#[2] BPM#[3]

PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_TRST# JTAGX

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

B61 D60 A61 C60 B59

XDP_TCK0 XDP_TDI XDP_TDO XDP_TMS XDP_TRST_N

B56 D59 A56 C59 C61 A59

XDP_TCK1_PCH XDP_TDI XDP_TDO XDP_TMS XDP_TRST_N XDP_TCK0

2

PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP 4 OF 20

SKL-U_BGA1356 @

+V3P3A +1.0VS_VCCIO +1.0VS_VCCSTG +1.0V_VCCST

+V3P3A 4,5,6,7,9,10,11,23,24,29,31,37,38,42,47,49,50,51,52,53,56,60,62,65,66,67 +1.0VS_VCCIO 10,14 +1.0VS_VCCSTG 10,12 +1.0V_VCCST 7,10,12,14,66

+1.0VS_VCCSTG 3

R1028

51R

R0402

5%

I

XDP_TDO

R1029

51R

R0402

5%

NI

XDP_TMS

R1027

51R

R0402

5%

NI

XDP_TDI

R1031

51R

R0402

5%

NI

XDP_TCK0

R1034

51R

R0402

5%

NI

XDP_TCK1_PCH

R1032

51R

R0402

5%

I

XDP_TCK0

R1033

51R

R0402

5%

NI

XDP_TRST_N

3

4

4

Project: Miix510 Size Custom Date: A

B

C

D

Jacky Engineer: Title: SKL-U(1/12)DDI,MISC,XDP,EDP Tuesday, June 27, 2017 E

Sheet

3

of

Rev V01 69

5

4

3

2

Non‐Interleaved

1

Non‐Interleaved SKL-U

UC1B

D

C

19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20

AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25

M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ

UC1C

SKL-U Rev_0.53

DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47]

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1] DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[3] DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5] DDR0_ALERT# DDR0_PAR

DDR CH - A

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ DDR_VTT_CNTL

AU53 AT53 AU55 AT55

M_A_DIM0_CK_DDR0_DN M_A_DIM0_CK_DDR0_DP

BA56 BB56 AW56 AY56

M_A_DIM0_CKE0

AU45 AU43 AT45 AT43 BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54 AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

M_A_DIM0_ODT0

5%

0R NI

19 19

M_A_A5 19 M_A_A9 19 M_A_A6 19 M_A_A8 19 M_A_A7 19 M_A_BG0 19 M_A_A12 19 M_A_A11 19 M_A_ACT_N 19 M_A_BG1 19

2/2 add 0R

M_A_A13 19 M_A_A15_CAS_N 19 M_A_A14_WE_N 19 M_A_A16_RAS_N 19 M_A_BA0 19 M_A_A2 19 M_A_BA1 19 M_A_A10_AP 19 M_A_A1 19 M_A_A0 19 M_A_A3 19 M_A_A4 19

AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26

M_A_DQS_DN M_A_DQS_DP M_A_DQS_DN M_A_DQS_DP M_A_DQS_DN M_A_DQS_DP M_A_DQS_DN M_A_DQS_DP M_B_DQS_DN M_B_DQS_DP M_B_DQS_DN M_B_DQS_DP M_B_DQS_DN M_B_DQS_DP M_B_DQS_DN M_B_DQS_DP

AW50 AT52

DDR0_A_ALERT_N 19 DDR0_A_PARITY 19

AY67 AY68 BA67

+V_DDR_CA_VREF

AW67

19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20

19

M_A_DIM0_CS0_N

M_A_BG1_SOC RM97 R0402_N

19 19

19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20

19

+V_DDR_VREFDQ02_CHB

20

DDR_VTT_CTRL

2 OF 20

AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21

M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_A_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ M_B_DQ

Rev_0.53

DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]

SKL-U_BGA1356

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1] DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[3] DDR1_MA[4] DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR CH - B

DDR1_ALERT# DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

AN45 AN46 AP45 AP46 AN56 AP55 AN55 AP53

20

M_B_DIM0_ODT0

M_B_BG1_SOC RM98 R0402_N 5%

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

2/2 add 0R

M_B_A13 20 M_B_A15_CAS_N 20 M_B_A14_WE_N 20 M_B_A16_RAS_N 20 M_B_BA0 20 M_B_A2 20 M_B_BA1 20 M_B_A10_AP 20 M_B_A1 20 M_B_A0 20 M_B_A3 20 M_B_A4 20

AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21 AN43 AP43 AT13 AR18 AT18 AU18

20 20

M_B_A5 20 M_B_A9 20 M_B_A6 20 M_B_A8 20 M_B_A7 20 M_B_BG0 20 M_B_A12 20 M_B_A11 20 M_B_ACT_N 20 M_B_BG1 20

0R NI

D

20

M_B_DIM0_CS0_N

M_A_DQS_DN M_A_DQS_DP M_A_DQS_DN M_A_DQS_DP M_A_DQS_DN M_A_DQS_DP M_A_DQS_DN M_A_DQS_DP M_B_DQS_DN M_B_DQS_DP M_B_DQS_DN M_B_DQS_DP M_B_DQS_DN M_B_DQS_DP M_B_DQS_DN M_B_DQS_DP

C

19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20

DDR1_B_ALERT_N 20 DDR1_B_PARITY 20 DDR4_DRAMRST_N 19

DDR4_DRAMRST_N SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

3 OF 20

RM1 100R

SKL-U_BGA1356

@

20

M_B_DIM0_CK_DDR0_DP M_B_DIM0_CKE0

BB42 AY42 BA42 AW42 AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

M_B_DIM0_CK_DDR0_DN

1% R0402_N I

@

RM2 80.6R 1% R0402_N

RM3 200R 1% R0402_N I

I

B

B

+V1P2U_VDDQ

SDP 4Gb or 8Gb

8G or 16Gb

DRAM M9 pin

RM95,RM96,RM97,RM98 need uninstall

RM95,RM96,RM97,RM98 need install

CM1 0.1uF 10V 10%

page4,19,20

RM99,RM100 need install

RM99,RM100 need uninstall

RM79,RM81,RM83,RM85, RM87,RM89,RM91,RM93 need install 0 ohm

RM79,RM81,RM83,RM85, RM87,RM89,RM91,RM93 need install 240 ohm

C0402 X5R I

UM10 1

DRAM E9 pin

+V3P3A

DDP

Memory size

DDR_VTT_CTRL

2 3

page19,20

NC

RM4 100K 5% R0402 I

5

VCC

A

4

Y

SM_PG_CTRL

61

GND

74AUP1G07GW sot_353

I

DDR_RCOMP0

RM3 200R

RM3 121R

need install

need install

page04

Default 2/2 Add (4Gb 8Gb) & (16Gb) BOM option table A

A

Project: Miix510 +V3P3A +V1P2U_VDDQ

Size Custom Date:

5

4

Jacky

Engineer:

+V3P3A 3,5,6,7,9,10,11,23,24,29,31,37,38,42,47,49,50,51,52,53,56,60,62,65,66,67 +V1P2U_VDDQ 10,19,20,21,61

3

2

Title:

Rev

SKL-U(2/12)DDR4

Tuesday, July 25, 2017 1

Sheet

4

of

V01 69

5

4

3

SPI Flash

D

SMBUS, SMLINK

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT# GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_C5/SML0ALERT# GPP_C6/SML1CLK GPP_C7/SML1DATA GPP_B23/SML1ALERT#/PCHHOT#

SPI - TOUCH M2 M3 J4 V1 V2 M1

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

5/9 EC_KBRST# Add PU R1066 10Kohm +V3P3SX

5% R0402_N I

To EC

50

EC_KBRST#

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_A5/LFRAME#/ESPI_CS# GPP_A14/SUS_STAT#/ESPI_RESET#

50

LPC_SERIRQ

CL_CLK CL_DATA CL_RST#

AW13

GPP_A0/RCIN#

AY11

R7 R8 R10

TP_SMB_CLK TP_SMB_DATA STRAP_GPP_C2

TP1053 TP1054

R9 W2 W1

SML0_CLK SML0_DATA STRAP_GPP_C5

TP9998 TP9999

W3 V3 AM7

SML1_CLK_R SML1_DATA_R THERMAL_ALERT#_R

R9861 R9862 R9863

R1055 1K

R1053 100K

R0402 5% NI

R0402 5% NI

R9872 10K

R9873 10K

5% R0402_N I

5% R0402_N I

Difference with armour connect to thermal sensor 0R 0R 0R

R0402_N R0402_N R0402_N

5% 5% 5%

I I NI

D

SML1_CLK 29 SML1_DATA 29 THERMAL_ALERT#

29

LPC

C LINK G3 G2 G1

+V3P3A +V3P3A

3/2 R9863 change to NI,THERMAL HW shutdown

+V3P3SX R1066 10K

+V3P3A

Rev_0.53

SPI - FLASH AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1

1

+V3P3A

SKL-U

UC1E

24,50 FLASH_SPI_CLK 24,50 FLASH_SPI_MISO 24,50 FLASH_SPI_MOSI 24 FLASH_SPI_IO2 24 FLASH_SPI_IO3 24,50 FLASH_SPI_CS0_N

2

GPP_A6/SERIRQ

5 OF 20

GPP_A9/CLKOUT_LPC0/ESPI_CLK GPP_A10/CLKOUT_LPC1 GPP_A8/CLKRUN#

AY13 BA13 BB13 AY12 BA12 BA11

LPC_AD0 41,43,50 LPC_AD1 41,43,50 LPC_AD2 41,43,50 LPC_AD3 41,43,50 LPC_FRAME_N 41,43,50

TP_PM_SUS_STAT_N

TPM/WLAN/EC

TP1052 AW9 AY9 AW11

LPC_CLK_EC_R LPC_CLK_PRT80_R

R1064 R1065

I I

22R 22R

R0402 R0402

PM_CLKRUN_N

5% 5%

LPC_CLK_EC 50 LPC_CLK_PRT80 41,43

50

LPC Mode SKL-U_BGA1356

+V3P3A

@ +V3P3A

C

R1059

10K

R0402

5%

I

R1061 8.2K

LPC_SERIRQ PM_CLKRUN_N

5/9 Page50 EC pin24 BAT_CHGOK_LED_N change to EC_KBRST#,connect to SOC pin AW13(RCIN)

R0402 5% I

C

R1073 1K R0402 5% NI

+V3P3A

+V3P3A

3,4,6,7,9,10,11,23,24,29,31,37,38,42,47,49,50,51,52,53,56,60,62,65,66,67

B

B

A

A

Project: Miix510 Jacky

Engineer: Size Custom Date: 5

4

3

2

Title:

SKL-U(3/12)SPI,ESPI,SMB,LPC

Tuesday, June 27, 2017

Sheet 1

5

of

Rev V01 69

5

4

3

2

1

To Enable ME Override 37,50

ME_Flash_EN

R9848

0R

R0402_N

5%

Difference with armour Add EC to enable ME override

D

33R

R0402

5%

I

HDA_SYNC_SOC HDA_BCLK

46

HDA_SYNC

RC393

46

HDA_BCLK_R

R1086

33R

R0402

5%

I

46

STRAP_HDA_SDO

RC395

33R

R0402

5%

I

STRAP_HDA_SDO_SOC

46

HDA_RST_N

RC394

33R

R0402

5%

NI

HDA_RST_N_SOC

STRAP_HDA_SDO_SOC I

5/23 R9848 install,BIOS request

D

+V3P3A R1054 1K R0402 5% NI

SKL-U

UC1G

Rev_0.53 AUDIO

HDA for AUDIO

46

HDA_SYNC_SOC HDA_BCLK STRAP_HDA_SDO_SOC HDA_SDI0

HDA_SDI0

HDA_RST_N_SOC

39

R10086

FCAM_RST_N

0R

R0402_N

5%

NI

FCAM_RST_N_CPU RCAM_RST_N

C

TP10034 40 40

FCAM_CLK_EN RCAM_CLK_EN

44 43

WWAN_DISABLE_N WIFI_DISABLE_N

46

PCH_AUDIO_PWREN 7 HW_ID4

+V3P3SX

BA22 AY22 BB22 BA21 AY21 AW22 J5 AY20 AW20

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

AK7 AK6 AK9 AK10

D8 C8

R1052

100K

R0402

5%

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3 GPP_G5/SD_CD# GPP_G6/SD_CLK GPP_G7/SD_WP

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

H5 D7

6/27 update

SDIO/SDXC

AW5

GPP_A17/SD_PWR_EN#/ISH_GP7 GPP_A16/SD_1P8_SEL

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

SD_RCOMP

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

Non-Micro SD

TP_SD_WP

R9864

0R

SDMMC_RCOMP

R1015

200R

R0402_N

5%

Difference with armour Add 0ohm NI

NI

C

BA9 BB9 AB7

AF13

FCAM_PD_N

R0402

1%

I

39

GPP_B14/SPKR

NI

7 OF 20

46

HDA_SPKR SKL-U_BGA1356 @

1/4 Connect codec

+V3P3A +V3P3SX

+V3P3A 3,4,5,7,9,10,11,23,24,29,31,37,38,42,47,49,50,51,52,53,56,60,62,65,66,67 +V3P3SX 5,7,9,10,23,26,30,31,36,37,38,39,40,41,43,44,45,46,47

B

B

UC1I

SKL_ULT

Rev_0.53 CSI-2

Rear Camera1 8M

Front Camera 5M

39 39 39 39 39 39 39 39

CSI2_RCAM_DATA0_DN CSI2_RCAM_DATA0_DP CSI2_RCAM_DATA1_DN CSI2_RCAM_DATA1_DP CSI2_RCAM_DATA2_DN CSI2_RCAM_DATA2_DP CSI2_RCAM_DATA3_DN CSI2_RCAM_DATA3_DP

A36 B36 C38 D38 C36 D36 A38 B38

39 39 39 39

CSI2_FCAM_DATA0_DN CSI2_FCAM_DATA0_DP CSI2_FCAM_DATA1_DN CSI2_FCAM_DATA1_DP

C31 D31 C33 D33 A31 B31 A33 B33 A29 B29 C28 D28 A27 B27 C27 D27

A

CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_COMP GPP_D4/FLASHTRIG

C37 D37 C32 D32 C29 D29 B26 A26 E13 B7

CSI2_RCAM_CLK_DN CSI2_RCAM_CLK_DP CSI2_FCAM_CLK_DN CSI2_FCAM_CLK_DP

CSI2_COMP R1013 CSI2_FLASH_STROBE

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7 GPP_F21/EMMC_RCLK GPP_F22/EMMC_CLK GPP_F12/EMMC_CMD 9 OF 20

1%

I

3/18 Add TP1061

EMMC

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

100R R0402 TP1061

39 39 39 39

EMMC_RCOMP

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

RCAM_PD_N 39 FCAM_ALLPWR_EN RCAM_ALLPWR_EN

4/24 update

1/4 check PDG

AM2 AM3 AP4 AT1

39 40

EMMC_RCOMP

R1014

200R

R0402

1%

Non-EMMC

A

I

SKL-U_BGA1356

Project: Miix510

@

Jacky

Engineer: Size

Title:

SKL-U(4/12)HDA,EMMC,SD

Custom Date: Wednesday, July 05, 2017 5

4

3

2

Sheet 1

6

of

Rev V01 69

5

4

3

2

1

XTAL_24M_SOC_IN

SDV

SIV

SIT

SVT XTAL_24M_SOC_OUT R1057

1

0

1

HW_ID1

0

0

1

1

SKL_ULT

UC1J

R9865 10K

R9866 10K

R9867 10K

R9868 10K

R10126 10K

5% R0402_N I

5% R0402_N I

5% R0402_N NI

5% R0402_N NI

5% R0402_N DSP

R1088 10K

R1089 10K

R1090 10K

5% R0402_N NI

R1091 10K

5% R0402_N I

5% R0402_N NI

R10127 10K

HW_ID3 HW_ID4

3 6

0R 0R

PCIE_REFCLK_SSD_DN_R PCIE_REFCLK_SSD_DP_R

R0402_N5%I R0402_N5%I

2016/10/07

6/27 update

2

43 43

HW_ID0

B42 A42 AT7

HW_ID1

D41 C41 AT8

HW_ID2

D40 C40 AT10

Difference with armour Modify HW_ID

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#

GPD8/SUSCLK XTAL24_IN XTAL24_OUT

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#

XCLK_BIASREF RTCX1 RTCX2

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#

PCIE_REFCLK_WLAN_DN_R E40 PCIE_REFCLK_WLAN_DP_R E38

SRTCRST# RTCRST#

AU7

HW_ID2

non-TPM U9505

0

non FP sensor

BA17

SUS_CLK

E37 E35

XTAL_24M_SOC_IN XTAL_24M_SOC_OUT

E42

XCLK_BIASREF

AM18 AM20

XTAL_32K_SOC_IN XTAL_32K_SOC_OUT

AN18 AM16

SRTC_RST_N RTC_RST_N

2.7K R0402

D

43 3/10 Change C1249,C1250 from 22pF to 8.2pF

+V1P0A_VCCPRIM

R1019

NPO C0402_N U22,U22F

1%

I

XTAL_32K_SOC_OUT XTAL_32K_SOC_IN R1056

10M

R0402

5%

I

Y1000 1

2

10 OF 20

32.768KHz +/-20ppm

Have DSP

1/13 Add RTC reset circuit.

R9885

0R

R0402_N

5%

R9884

0R

R0402_N

1

5%

CRY2_3215 I

C1251 15pF 50V 5% NPO C0402_N I

@

non DSP

C1249 8.2pF 50V 0.1pF

NPO C0402_N U22,U22F

F43 E43

SKL-U_BGA1356

TPM U9505

4 Y4

X4S32X25 U22,U22F

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#

WLAN

have FP sensor

Y1

24MHZ 10PPM

C1250 8.2pF 50V 0.1pF

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#

B40 A40 AU8

PCIE_REFCLK_SD_DN_R PCIE_REFCLK_SD_DP_R 45 SD_CLK_REQ_N PCIE_REFCLK_WLAN_DN_R PCIE_REFCLK_WLAN_DP_R 43 WLAN_CLK_REQ_N

1

Y2

Y3

D42 C42 AR10

SD 45 45

5% R0402_N NONDSP

U22,U22F

3

Close to SOC

SSD

HW_ID0 HW_ID1 HW_ID2 HW_ID3 HW_ID4

5% R0402_N NI

R9887 R9888

26 PCIE_REFCLK_SSD_DN 26 PCIE_REFCLK_SSD_DP 26 SSD_CLK_REQ_N

5%

Y1001

Rev_0.53 CLOCK SIGNALS

+3V_PRIM

D

1M

R0402

GND

0

GND

HW_ID0

SRTC_RST_N NI

C1252 15pF 50V 5% NPO C0402_N I

RTC_RST_N I

D

HW_ID3

1

0 50

C

HW_ID4

0

SRTCRST_EC

1

S

G

R9883 10K

Q8209 2N7002 250mA 60V

3/10 Change Y1000 from seiko to HOSONIC

sot_323_dgs I

3/10 Change C1251,C1252 from 18pF to 12pF

+V1P0A_VCCPRIM +V3P3A +V3P3SX +1.8V_PRIM +V3.3AL +RTCVCC +3V_PRIM +1.0V_VCCST

C

3/21 Change C1251,C1252 from 12pF to 15pF, hosonic & seiko share

5% R0402_N I

+V1P0A_VCCPRIM 14 +V3P3A 3,4,5,6,9,10,11,23,24,29,31,37,38,42,47,49,50,51,52,53,56,60,62,65,66,67 +V3P3SX 5,6,9,10,23,26,30,31,36,37,38,39,40,41,43,44,45,46,47 +1.8V_PRIM 10,11,31,39,40,44,47,56,65 +V3.3AL 11,50,51,58,60,66 +RTCVCC 11 +3V_PRIM 8,11 +1.0V_VCCST 3,10,12,14,66

+RTCVCC +V3P3A R1072 10K

PM_BATLOW_N UC1K +V3P3A

R1093 2.2K

RTC_RST_N

R1071 2.2K

26,41,43,45,50

5% R0402_N NI

50

PLT_RST_N

PM_SYSRST_N

RSMRST_N

TP_CPUPWRGD A68 H_VCCST_PWRGD B65

TP1021

B

PM_SYSRST_N 50

RSMRST_N

50 SYS_PWROK IMVP_PCH_PWRGD

R1079 100K

TP1081 TP1048

5% R0402_N I

26,43

RSMRST_N

TP_SUS_PWR_DN_ACK AR13 TP_SUSACK_N AP11 BB15 AM15 AW17 AT15

PCIE_WAKE_PCH_N +V3P3A R1041

R0402_N

B6 BA20 BB20

10K 5%

GPP_B12/SLP_S0# GPD4/SLP_S3# GPD5/SLP_S4# GPD10/SLP_S5# SLP_SUS# SLP_LAN# GPD9/SLP_WLAN# GPD6/SLP_A#

PROCPWRGD VCCST_PWRGD SYS_PWROK PCH_PWROK DSW_PWROK

GPD3/PWRBTN# GPD1/ACPRESENT GPD0/BATLOW#

GPP_A13/SUSWARN#/SUSPWRDNACK GPP_A15/SUSACK# WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD

GPP_A11/PME# INTRUDER# GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT#

11 OF 20

AT11 AP15 BA16 AY16 AN15 AW15 BB17 AN16 BA15 AY15 AU13

SLP_S0_N SLP_S5_N

TP9996 TP9988

SLP_SUS_N

SLP_S3_N SLP_S4_N SLP_SUS_N

10,50,60 10,42,47,50,60 Difference with armour SLP_SUS_N open +3V_PRIM

C1254 1uF 6.3V 10%

C1253 1uF 6.3V 10%

X5R C0402_N I

X5R C0402_N I

11 +3V_PRIM

SLP_A_N

PM_PWRBTN_R_N

AC_PRESENT_R

PM_BATLOW_N

AU11 AP16

PME_N SM_INTRUDER_N

AM10 AM11

EXT_PWR_GATEB R200_PWR_EN

B

TP9997 50

+1.0V_VCCST

R1020 10K

50

5% R0402_N I

R1044

H_VCCST_PWRGD IMVP_PCH_PWRGD

TP1025 TP1022

C

CR1003 RB521C30 100mA 30v

R9886 100K

SOD-923 I

5% R0402_N NI

SKL-U_BGA1356

+V3P3A

+1.8V_PRIM 29,66

R9850 2.2K

5% R0402_N I

R0402_N

0R 5%

R1048 100K

IMVP_PCH_PWRGD I

5% R0402_N I

50

44 50,59

D2QX1B

G2

S22N7002KDW

CHG_ACOK change to ACPRES from Charger IC

115mA 60V

SOT363V D1QX1A

I

R1046

AC_PRESENT

ACPRES

to WWAN reset pin

PLT_RST_N_Q

A

VR_PWRGD

R1042

2/24 Add R1042,VR_PWRGD connect to SOC and EC BUF_PLT_RST_N_V1P8S

5% R0402_N I

5%

A

Difference with armour Del U1201 Low-power buffer(74AUP1G07GW) and add Dual MOS to change level

R9849 100K

1K

R0402_N I

@

+V3.3AL

5% R0402_N I

SM_INTRUDER_N

SKL-U

GPP_B13/PLTRST# SYS_RESET# RSMRST#

I

R1062 1M

5% R0402_N I

SRTC_RST_N

SYSTEM POWER MANAGEMENT

AN10 B5 AY17

R1060 20K

5% R0402_N I

Rev_0.53

+V3P3SX

5% R0402_N I

R1058 20K

5% R0402_N I

R0402_N NI

C

0R 5%

AC_PRESENT_R

A

CR9052 RB521C30 100mA 30v

A

SOD-923 I

PLT_RST_N G1

S1

2N7002KDW 115mA 60V SOT363V I

Project: Miix510 Jacky

Engineer: Size

Title:

5

4

3

2

Rev

SKL-U(5/12)CLK,GPIO

Custom Date: Monday, September 04, 2017

1

Sheet

7

of

V01 69

5

4

3

2

1

GPP_D10

+3V_PRIM

SKL-U

UC1F LPSS

D

TP1009

TP_STRAP_GPP_B18

AM5 AN7 AP5 AN5

31 FP_SPI_CS0_N 31 FP_SPI_CLK 31 FP_SPI_MISO 31 FP_SPI_MOSI Add the GPIO for Hall sensor

G-sensor Touch panel Camera 8M Camera 5M 4/20 update

AB1 AB2 W4 AB3

38,47,50 LID_INT_N 37,50 DOCK_DET 43 WLAN_RST 49,50 LID_INT_N1 56 56

UART for debug

38 38 37 37 39 39 39 39 44 44

AN8 AP7 AP8 AR7

AD1 AD2 AD3 AD4

UART2_RXD UART2_TXD

U7 U6

TP_I2C0_SDA_EDP2DSI TP_I2C0_SCL_EDP2DSI

U8 U9

TOUCH_I2C_SDA TOUCH_I2C_CLK

AH9 AH10

I2C_2_RCAM_SDA I2C_2_RCAM_SCL

AH11 AH12

I2C_3_FCAM_SDA I2C_3_FCAM_SCL

AF11 AF12

WWAN_HOST_WAKE_N GPS_DISABLE_N

Rev_0.53

ISH

GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI

GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL

GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#

GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5 GPP_A12/BM_BUSY#/ISH_GP6

GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL

Add the GPIO for control CAM 5M/8M

1% R0402_N I

03/22 Modify

P2 P3 P4 P1 M4 N3 N1 N2

WWAN_GNSS_3P3_SDA WWAN_GNSS_3P3_SCL IMU_I2C_SDA IMU_I2C_SCL

AD11 AD12

SH9515 SH9516

AC1 AC2 AC3 AB4

0R 0R

R0402_N R0402_N

5% 5%

I I

44 44

38 38

IMU Sensor

CRD_PWR_OFF_N_SOC

44

44

2/17 Modify

Memory detection 3/1 Modify

AY8 BA8 BB7 BA7 AY7 AW7 AP13

IMU_INT1

Difference with armour WWAN_SAR_DET AD11 move to BA7 follow Intel MRD

38 ACCEL_INT 38 38 38 FP_SLEEP_N 31 FP_DRDY 31 38

IMU_INT2 IMU_INT3 IMU_INT4

6 OF 20

WWAN 3/1 Modify

IMU_I2C_SDA_HUB IMU_I2C_SCL_HUB

WWAN_GNSS_INT

MEM_DEC0 MEM_DEC1 MEM_DEC2 MEM_DEC3

1

D

CRD_PWR_OFF_N_SOC

TP10014 TP10015

0

5M CAM

Add the GPIO for control docking power

DOCK_DET_SOC 37 CAM_8M 39 VOLUME_UP 49,50 VOLUME_DOWN 49,50

U1 GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 GPP_D15/ISH_UART0_RTS# U4 GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL

R10089 10K

8M CAM

6/24 SAR_PROX_RST,reserved R1096 connect to GPP_A12,add R1095 connect to GPP_A22,BIOS request

SKL-U_BGA1356

C

C

@ +3V_PRIM

+3V_PRIM

+3V_PRIM

+3V_PRIM

Memory Dectection 3/2 Change memory ID PU from +1.8V_PRIM to +3V_PRIM +V3P3A +1.8V_PRIM

R9803 10K

+V3P3A 3,4,5,6,7,9,10,11,23,24,29,31,37,38,42,47,49,50,51,52,53,56,60,62,65,66,67 +1.8V_PRIM 7,10,11,31,39,40,44,47,56,65

R9801 10K

1% R0402_N NI

1% R0402_N NI

MEM_DEC0 R9804 10K

1% R0402_N I

Hynix_4GB SDP

MEM_DEC1

R9802 10K

R9807 10K

1% R0402_N I

1% R0402_N I

Mem_DEC3 MEM_DEC2

R10090 10K

Voltage

One Channel

0V

Two Channel

3.3V

1% R0402_N NI

MEM_DEC3

R10091 10K 1% R0402_N I

3/29 add memory ID

Samsung_4GB SDP

Hynix_8GB DDP

Samsung_8GB DDP

Hynix_8GB SDP

Micron_8GB SDP

Samsung_8GB SDP

0

1

0

1

0

1

0

1

0

1

0

1

MEM_DEC1

0

0

1

1

0

0

0

0

1

1

0

0

MEM_DEC2

0

0

0

0

1

1

0

0

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

Default

Micron_8GB DDP

1% R0402_N NI

MEM_DEC0

MEM_DEC3

Micron_4GB SDP

R9806 10K

Hynix_16GB DDP

Micron_16GB DDP Samsung_16GB DDP

B

B

A

A

Project: Miix510 Jacky

Engineer: Size

Title:

5

4

3

2

Rev

SKL-U(6/12)GPIO

Custom Date: Monday, September 04, 2017

1

Sheet

8

of

V01 69

5

4

3

UC1H

2

1

SKL-U Rev_0.53 SSIC / USB3

PCIE/USB3/SATA

H13 G13 B17 A17 G11 F11 D16 C16

D

H16 G16 D17 C17

NGFF WIFI Module

43 43 43 43

G15 F15 B19 A19

PCIE_WLAN_LN0_RX_SOC_DN PCIE_WLAN_LN0_RX_SOC_DP PCIE_WLAN_LN0_TX_SOC_DN PCIE_WLAN_LN0_TX_SOC_DP

F16 E16 C19 D19

5/4 WIFI PCIE port 8 change to port 4,because PCH HSIO 8 can use PCIe interface (for Base-U)

45 45 45 45

PCIE_SD_LN0_RX_SOC_DN PCIE_SD_LN0_RX_SOC_DP PCIE_SD_LN0_TX_SOC_DN PCIE_SD_LN0_TX_SOC_DP

C9586 C9587

0.22uF 10V 10% 0.22uF 10V 10%

G18 F18 D20 C20

CPU_SD_TX_DN CPU_SD_TX_DP

C0402_NX5R I C0402_NX5R I

F20 E20 B21 A21

2016/10/07 C

G21 F21 D21 C21

PCIE9_SSD_RX_DN PCIE9_SSD_RX_DP PCIE9_SSD_TX_DN_C PCIE9_SSD_TX_DP_C

C0600 C0601

0.22uF 10V 10% 0.22uF 10V 10%

C0402_NX5R I C0402_NX5R I

PCIE9_SSD_TX_DN PCIE9_SSD_TX_DP

26 26 26 26

PCIE10_SSD_RX_DN PCIE10_SSD_RX_DP PCIE10_SSD_TX_DN_C PCIE10_SSD_TX_DP_C

C0602 C0603

0.22uF 10V 10% 0.22uF 10V 10%

C0402_NX5R I C0402_NX5R I

PCIE10_SSD_TX_DND23 PCIE10_SSD_TX_DPC23

F25 E25

R1063 NGFF SSD

R0402

PCIE_RCOMP_N PCIE_RCOMP_P

100R 1%

I

XDP_PRDY_N XDP_PREQ_N TP_EC_CS_WAKE

TP1051 TP1062 TP1050

B

E22 E23 B23 A23

26 26 26 26

26 26 26 26 26 26 26 26

PCIE11_SSD_RX_DN PCIE11_SSD_RX_DP PCIE11_SSD_TX_DN_C PCIE11_SSD_TX_DP_C PCIE12_SSD_RX_DN PCIE12_SSD_RX_DP PCIE12_SSD_TX_DN_C PCIE12_SSD_TX_DP_C

Difference with armour SSD interface SATA change to PCIE SATA1A change to PCIE port 9,10,11,12

F5 E5 D56 D61 BB11 E28 E27

C0604 C0605 C0606 C0607

0.22uF 10V 10% 0.22uF 10V 10% 0.22uF 10V 10% 0.22uF 10V 10%

C0402_NX5R I C0402_NX5R I

PCIE11_SSD_TX_DND24 PCIE11_SSD_TX_DPC24

C0402_NX5R I C0402_NX5R I

E30 F30 PCIE12_SSD_TX_DNA25 PCIE12_SSD_TX_DP B25

USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP

PCIE1_RXN/USB3_5_RXN PCIE1_RXP/USB3_5_RXP PCIE1_TXN/USB3_5_TXN PCIE1_TXP/USB3_5_TXP

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

PCIE2_RXN/USB3_6_RXN PCIE2_RXP/USB3_6_RXP PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

PCIE3_RXN PCIE3_RXP PCIE3_TXN PCIE3_TXP

USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP

PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP

USB2N_1 USB2P_1

PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP

USB2N_2 USB2P_2 USB2N_3 USB2P_3

PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP

USB2N_4 USB2P_4

PCIE7_RXN/SATA0_RXN PCIE7_RXP/SATA0_RXP PCIE7_TXN/SATA0_TXN PCIE7_TXP/SATA0_TXP

USB2

USB2N_5 USB2P_5 USB2N_6 USB2P_6

PCIE8_RXN/SATA1A_RXN PCIE8_RXP/SATA1A_RXP PCIE8_TXN/SATA1A_TXN PCIE8_TXP/SATA1A_TXP

USB2N_7 USB2P_7 USB2N_8 USB2P_8

PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP

USB2N_9 USB2P_9

PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP

USB2N_10 USB2P_10 USB2_COMP USB2_ID USB2_VBUSSENSE

PCIE_RCOMPN PCIE_RCOMPP

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

PROC_PRDY# PROC_PREQ# GPP_A7/PIRQA# PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP PCIE11_TXN/SATA1B_TXN PCIE11_TXP/SATA1B_TXP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_TXN PCIE12_TXP/SATA2_TXP

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2 GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_E8/SATALED#

H8 G8 C13 D13

USB3_P1_RX_DN USB3_P1_RX_DP USB3_P1_TX_DN USB3_P1_TX_DP

J6 H6 B13 A13

USB3_P2_WP2_RX_DN USB3_P2_WP2_RX_DP USB3_P2_WP2_TX_DN USB3_P2_WP2_TX_DP

J10 H10 B15 A15

USB3_P3_WWAN_SSIC_RX_DN USB3_P3_WWAN_SSIC_RX_DP USB3_P3_WWAN_SSIC_TX_DN USB3_P3_WWAN_SSIC_TX_DP

42 42 42 42

USB3.0 CONN 52 52 52 52

Type-c 44 44 44 44

WWAN

E10 F10 C15 D15 AB9 AB10

USB2_P1_WP1_DN USB2_P1_WP1_DP

42 42

AD6 AD7

USB2_P2_WP2_DN USB2_P2_WP2_DP

55 55

AH3 AJ3

USB2_P3_WWAN_DN USB2_P3_WWAN_DP

AD9 AD10

USB2_P4_BT_DN USB2_P4_BT_DP

AJ1 AJ2

USB2_P5_DOCK_DN USB2_P5_DOCK_DP

USB3.0 connector Type-c 44 44

NGFF WWAN Module

43 43

BT 37 37

USB 2.0 docking

AF6 AF7 C AH1 AH2 AF8 AF9 AG1 AG2 AH7 AH8 AB6 AG3 AG4

USB2_COMP USB2_P1_WP1_OTG_ID USB2_VBUSSENSE

A9 C9 D9 B9

USB2_P2_WP3_OC_N

R1012 R1084 R1085

113R R0402 1K R0402_N 1K R0402_N

1% 5% 5%

I I I

USB2_P1_WP1_OC_N 42 USB2_P2_WP2_OC_N 53 WWAN_PWR_ON 44

J1 J2 J3

TP_SATA0_DEVSLP SATA1_DEVSLP

TP1079 TP8201

H2 H3 G4

TP_SSD_SATA0_PCIE_DET_N

TP1080 TP1082

H1

TP_EDP2DSI_CORE_PWR_EN

SATA2_DEVSLP

SSD_SATA_PCIE_DET_N

Difference with armour B9 modify to WWAN_PWR_ON

Difference with armour modify SATA2_DEVSLP

26

Difference with armour SSD_SATA_PCIE_DET_N connect to G4 pin

B

TP8213

8 OF 20

Checklist： Gen1 and Gen2=100nF Gen3=220nF

SKL-U_BGA1356 @

GPIO USB_OC0#

A

+V3P3A +V3P3SX

DEVICE CONTROL Type C

USB_OC1#

USB2 Port 2

USB_OC2#

NA

USB_OC3# DEVSLP0

WWAN_PWR_ON NA

DEVSLP1

NA

+V3P3A Difference with armour R1050 install,R1087 uninstall R9882 10K

R1087 100K 5% R0402_N NI

USB2_P2_WP3_OC_N SSD_SATA_PCIE_DET_N 1/7 Add PU +V3P3A

DEVSLP2

NGFF SSD KEY M

SATA_GP0

NA

SATA_GP1

NA

SATA_GP2

SSD_SATA_PCIE_DET_N

R1050 10K

NOTE: USE FITC TO ALLOW SELECTION OF

5% R0402_N I

PCIE VS SATA BASED ON STRAPPING: GPP_E_2 FOR SATA2/PCIE:

A

1 - SATA2, 0 - PCIE P9,P10,P11,P12

Project: Miix510

+V3P3A 3,4,5,6,7,10,11,23,24,29,31,37,38,42,47,49,50,51,52,53,56,60,62,65,66,67 +V3P3SX 5,6,7,10,23,26,30,31,36,37,38,39,40,41,43,44,45,46,47

3

Jacky

Engineer: Title:

SKL-U(7/12)PCIE,USB,SATA

Custom Date: Tuesday, June 27, 2017 4

+V3P3SX

5% R0402_N I

Size

5

D

2

Sheet 1

9

of

Rev V01 69

5

4

3

2

+V1P2U_VDDQ +V5P0A

+V5P0A

CC98 1uF 6.3V 10%

CC97 1uF 6.3V 10%

X5R C0402 I

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

CC96 0.1uF 10V 10%

X5R C0402 I

X5R C0402 I

11/17_Follow 543977_SKL_PDDG_Rev0_91 CC95 10PF ->22us(Spec: