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Experiment (b) To Model a PISO( parallel input serial output ) shift register Entities:
entity PISO is Port ( clk,load : in STD_LOGIC; pi : in std_logic_vector(3 downto 0); so : out STD_LOGIC); end PISO; architecture Behavioral of PISO is signal t : std_logic; signal temp: std_logic_vector(3 downto 0); begin process (clk,pi,load) begin if (load='1') then temp(3 downto 0)