Surface Pro 5 M1007506 015 REV.U23 [PDF]
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Table of Contents Sheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
D
C
B
Title Table of Contents Build Options BLOCK DIAGRAM CLOCK DISTRIBUTION SIGNAL & RESET MAP POWER FLOW (1 OF 3) POWER FLOW (2 OF 3) POWER FLOW (3 OF 3) I2C MAP CPU(1)_MISC,JTAG,DDI.EDP CPU(2)_LPDDR3 CPU(3)_KBL_POWER1 CPU(4)_KBL_POWER2 CPU(5)_GND CPU(6)_CFG_RESERVED LPDDR3(1)_MEMORY DOWN LPDDR3(2)_MEMORY DOWN XDP LPDDR3(3)_CA/DQ Voltage PCH(1)_SD,HDA,RTC, CLK PCH(2)_CLK,SMB,LPC, SPI PCH(3)_SYS PWR CONTR PCH(4)_CCI, HWID PCH(5)_PCIE,USB PCH(6)_CPU,GPIO,MISC PCH(7)_POWER PCH(8)_empty Power Monitor SI Coupon Touch Con & Key
Sheet 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Title Button & Diagnostic Conn On Board-Sensors Debug Conn PECI Silego Controller SAM Power, ADC, & Debug SAM Buses & Gpio TPM Temp Sensor/System Fan REALTEK ALC3269C_81BGA Audio Jack/Spkr Microphone_rear SSD_1 SSD_2 USB3.0 DP Dongle Control mDP SDXC Camera IR Wi-Fi_BT Empty Camera Power Camera Rear Camera Front 3P3VA & Reset +VCCIO eDP connector +VCCEDRAM & +VCCEOPIO +5VSB & +3P3VSB +1P2V_DUAL&+VTT
Sheet 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
Title +1VSB +1.8VSB & Load SW CHARGER +5V Load SW +3P3V Load SW Controller 1 IA and SA Empty GT SL1 Power, Battery Conn SL1 Signals +3P3V_HPD/LCD backlight/TB Debug Expansion Connector Blade Interface Power Protect Shields, TPs, & Mechanical
D
C
https://vinafix.com B
A
A
CAD Note: Default component
footprint is SMD 0201, X5R, 1% resistors. Property: BUILD-OPT DNP = Do Not Place 5
4
S or DB = Replace after Debug 3
2
5
4
BUILD-OPT ALL DNP TBL1001 TBL3602 U23E TBL6601 TBL2301 TBL3601 TBL1601 TBL3801 TBL4301 SSD1 SSD2 S DBG DBG_D DBG_N DBG_R DBG_S DBG_T DBG_D_TBL4301 XDP XDP_D FAN
D
C
3
BOMAssy Common Common CPU CPU CPU CPU BdID BdID Mem TPM SSD SSD SSD Debug Debug Debug Debug Debug Debug Debug Debug XDP XDP FAN
2
Remarks DEFAULT- PopulatedasshowninCoreschematicforallvariants O-STUFFforallvariants CPUselection ResJumpers OnlypopulatedtosupportU23evariants(generallyusedforadditional CPUpowerparts) U23e/U22PartChanges ResJumpers ResJumpers LPDDR3MemoryAssemblyOptions SecurityDeviceOptions SSDMemorypartoptions OnlypopulatedforsingleSSDconfigurations. OnlypopulatedfordualSSDconfigurations. Legacy- OriginallyintendedsameasDBG_S. pleasereplacewithDBG_S, DBG_R, orDBG_Dasappropriate. Legacy- SameasDBG_Dshownbelow.PartdepopulatedforMP. DebugPart- RemovefromBOM(Depopulate) forMP Non-DebugPart- Installedonlyinnon-debugbuilds DebugPart- ReplacewithlowercostcomponentforMP(Ex; replaceprecisionshuntwith0-ohmjumper) DebugPart- ReplacewithboardshortforMP(notcommonlyusedanymore) DebugPart- UsedforPowerTelemetryinMPasneeded. DebugRemoveforMP, InstallforDebugperTBL4301 Legacy- SameasXDP_D OnlyusedasneededforCPUDebug. DepopulatedforMPandmostEV/DV/PVassemblies. PartsusedtosupportFanoption.
1
D
C
https://vinafix.com B
B
A
A
CAD Note: Defaults: Footprint 5
SMD 0201, Cap tmp Coeff X5R, 1% resistors 4
3
2
5
4
3
2
1
D
D
C
C
https://vinafix.com B
B
A
A
5
4
3
2
5
4
3
2
1
LPDDR3-1 CH A
D
LPDDR3 - CH B
D
M_CHA_CLK[0..1]/# M_CHB_CLK[0..1]/#
Intel SKL U/Y
C
C
CK_24M_TPM 24 MHz
https://vinafix.com CLKOUT_LPC_1
B
CLKOUT_ITXDP_N CLKOUT_ITXDP_P
CLK_XDP_N CLK_XDP_P 100 MHz
XDP
CLKOUT_PCIE_N2 CLKOUT_PCIE_P2
PCIE_WIFI_RCLK_N PCIE_WIFI_RCLK_P 100 MHz
WIFI
CLKOUT_PCIE_N4 CLKOUT_PCIE_P4
PCIECLK_SSD_DN PCIECLK_SSD_DP 100 MHz
SSD
HDA_BCLK
SPI_CLK A
XTAL24_IN
24MHz 5
4
TPM
AZ_BITCLK 24 MHz
AUDIO CODEC
SPI_CLK 50 MHz
SPI ROM A
RTCX
32.768KHz 3
B
2
5
4
3
2
1
SIGNAL & RESET MAP D
D
VDD_BATA_PACK
SL1_PWR_GOOD PWR_SL1_F
1-1
Switch (Diode)
SW
PWR_SL1
SL1
+V_ALWAYS_ON +1P2V_DUAL_PWRGD ALL_SUS_PWRGD VRM_PWRGD ALL_SYS_PWRGD +VCCIO_PWRGD
VOLT REG.
FORCE_OFF#
USER_RESET MAX6443
CHG_BATDRV_A
FET
3P3VA_EN
Charging circuit
2
+3P3V_SAM
14 SLP_S4# 3
16 SLP_S3#
RESET#
+5V_SHA
& Switch
C
+VCC_RTC
Step-Down
SAM Reset circuit SAM_RESET#
Battery
13
SB_PWRBTN#
+3P3V_SAM
Power Button
PWRBTN#
PWRBTN#
10
RSMRST#
6
12
PCH_DPWROK
SLP_S4# RSMRST#
DSW_PWROK
11
7 SLP_SUS#
B
Signal & Description
1 2 3 4. 5. 6. 7. 8. 9. 10. 11.
Convert any raw power to +3P3VAS +3P3V_SAM / Generate SAM's power SAM_RESET# / Intialize SAM +VSYS / Declare system power ready Intentionally unused PCH_DPWROK / Declare deep power good to PCH SLP_SUS# / Request standby power VSUS_ON / SAM turns on standby power ALL_SUS_PWRGD / Standby power (SUS) power stable RSMRST# / Declare SUS power good to PCH Intentionally unused
12 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24.
PWRBTN# to Silego & SAM SB_PWRBTN# / SAM passes PWRBTN# signal to PCH SLP_S4# / PCH requests exit of S4 state when high SLP_S4_DRV# / SAM drives the power regulators SLP_S3# / PCH requests exit of S3 state when high SLP_S3_DRV# / SAM drives the power regulators ALL_SYS_PWRGD / Regulators declare stablity VCCST_PWRGD / Regulators declare stablity to CPU VRM_PWRGD / Regulators declare CPU power is good PM_PCH_PWROK / SAM delays CPU power good >5ms SYS_PWROK / SAM declares system power stable SVID / VR controller establish protocol to CPU PLTRST# / PCH releases Platform Reaser signal
+V_VDDQ_VTT +1P2V_DUAL +1P8V_DUAL +VCCST_CPU
https://vinafix.com +3P3VSB +5VSB +1P8VSB +0P85VSB +1VSB
PM_PCH_PWROK
TPM
to SAM
SLP_SUS#
PLTRST_BUF#
PCH_PWROK
22
9 ALL_SUS_PWRGD
SYS_PWROK
SYS_PWROK
+1VSB is last one ramp up
PLTRST#
24 PLTRST#
15 SLP_S4_DRV#
AND Gate Buffer B
19
17 SLP_S3_DRV#
VCCST_PWRGD
VCCST_PWRGD
This really goes to SkyLake H
Silego
+3P3VA +1P8VA
+VCCIO +VCCSTG +1P8V +3P3V +5V
18
ALL_SYS_PWRGD page 75
OD
+3P3V_SSD
Power On Sequence Stuff on pgs 66-68
A
+VCCEDRAM +VCCEOPIO VCORE VCCGT VCCGTX VCCSA
5
Intel PCH
21
8 VSUS_ON
1-2
STEP
+VSYS
POWER ON SEQUENCE (TBD)
SLP_S3# C
SAM K22
4
3
EN
VRDY
CPU_VRON
1
24 A
0 ohm
20 VRM_PWRGD 23 SVID
2
5
4
3
U5505 LDO; Iout = 80 mA
+V_ALWAYS_ON
2
PR5569
+3P3VAS 80 mA
PR7202
D
PWR_SL1_F PU5501 BUCK; Iout = 457 mA R6303 EXT_DC_IN
R6319 CHARGER
+VSYS
PR5531
+3P3VA 310 mA
+VCC_RTC 0.2 mA U7201 LSW; Iout = 75 mA
PR3605
+3P3V_HPD 75 mA
VDD_BATA_PACK
PR5626
U5623 BUCK; Iout = 3100 mA
+VCCIO 3100 mA
PR6003
U6001 BUCK; Iout = 7950 mA
+1P2V_DUAL 7950 mA
PR6121
U6101 BUCK; Iout = 5703 mA
+1VSB 5703 mA*
PR6205
PU6202 BUCK; Iout = 1582 mA U6701/U6702 BUCK; Iout = 32000 mA
+1P8VSB 1582 mA +VCORE 32000 mA
R6701
R6702
D
3v3_SAM 147 mA
PU6003 LSW; Iout = 350 mA
U6703 BUCK; Iout = 5100 mA
+VCCPLL_OC 350 mA
+V_VDDQ_VTT 600 mA
LDO
C
1
C
+VCCSA 5100 mA PR5908 +5VSB 4923 mA PR5907 +3P3VSB 5360 mA PR5912 +3P3V_SSD 5187 mA
https://vinafix.com PR5905
PR5906
B
LEGEND
PR5914
S0/S3/S5
R7209
S0/S3
R6901
S0
U5901 BUCK; Iout = 7131 mA U5902 BUCK; Iout = 5360 mA U5903 BUCK; Iout =5187 mA
U7202 LED/BACKLIGHT DRIVER Iout = 105 mA U6901/U6902 BUCK; Iout = 64000 mA U4901 LED DRIVER Iout = 1000 mA
Unknown
+VCC_EDP_BKLT_OUT 105 mA
B
+VCCGT 64000 mA (IR Illuminator) D4902 1000 mA
PR5820
U5821 BUCK; Iout = 3200 mA
+VCCEDRAM 3200 mA
PR5823
U5822 BUCK; Iout = 2000 mA
+VCCEOPIO 2000 mA
A
A
5
4
3
2
5
+5VSB 4923 mA
4
U6408 LSW; Iout = 500 mA
D
R6411
U6405 LSW; Iout = 338 mA
R6417
U4504 LSW; Iout = 1500 mA
R4511
U6404 LSW; Iout = 660 mA U6401 LSW; Iout = 750 mA
+5V_FAN 500 mA
D
Touch
+5V_USBPWR 1500 mA +5V_AUDIO 660 mA
R6407
+5V_SDXC 880 mA U7404 LSW; Iout = 75 mA
USB Power
Vinafix.com
Audio
+5V_KB_CONN 750 mA
Blade Connectivity
SD Card Reader +5VA_SHA_CONN 75 mA
C
+1P8VSB 1582 mA
U6202 LSW; Iout = 260 mA
PR6210
PU6105 LSW; Iout = 240 mA +V1.00A 2849 mA +VCCPRIM_CORE 2574 mA +1VSB_XDP 400 mA
+VCCSTG 40 mA
PR6151
+VCCST_CPU 120 mA
+1P8V_DUAL 620 mA
Memory
PU6201 LSW; Iout = 50 mA
PR6202
+1P8V 50 mA
PU6205 LSW; Iout = 452 mA
PR6209
+1P8V_TS 452 mA
R2624 PR6150
Audio
PR6231
B
PU6103 LSW; Iout = 40 mA
+1P8V_AUDIO 260 mA
U6203 LSW; Iout = 620 mA
https://vinafix.com +1VSB 5703 mA*
1
FAN
+5V_TS 220 mA
R6413
R6412 C
2
+5V 338 mA
R6420
U6407 LSW; Iout = 220 mA
3
+1P8VSUS_ORG 200 mA
Touch
CPU B
CPU
+VCCPLL 120 mA
CPU
PCH
PCH Debug only, not included in total power
A
A
5
4
3
2
5
4
3
2
1
D
D
+3P3VSB 5360 mA
PU6504 LSW; Iout = 450 mA PR6546
PU6501 LSW; Iout = 1500 mA
PR6508
+3P3V_PANEL 450 mA
+3P3V_PMI 2 mA
Power Monitors
PR6514
PR6510
R2612 C
+3VSUS_ORG 123 mA
WiFi
CPU ML_3P3V_PWR_FUSE 500 mA
PU7301 LSW; Iout = 1750 mA
+3P3V_EXPCON 1750 mA PR5201
B
+3P3V_RADIO 1500 mA
+3P3V 500 mA
U4703 LSW; Iout = 500 mA
+1P8V_CAM_R 130 mA
+3P3_SSD_IN 1000 mA +3P3_SSD_IN2 1000 mA
SSD
U4303 BUCK; Iout = 1200 mA
+1P8V_SSD 1200 mA
U4402 BUCK; Iout = 1200 mA
+1P8V_SSD2 1200 mA
U4304 BUCK; Iout = 2100 mA
+1P1V_SSD 2100 mA
U4403 BUCK; Iout = 2100 mA
+1P1V_SSD2 2100 mA
C
mDP
PR5205
https://vinafix.com U5204 LDO; Iout = 120 mA
PR5202
+1P8V_CAM_F 15 mA
PR5209
+1P8V_CAM_IR 55 mA
Cameras
U5202 LDO; Iout = 45 mA
PR5203
2P8V_CAM_R 45 mA
Cameras
U5203 LDO; Iout = 70 mA
PR5204
2P8V_CAM_F 70 mA
Cameras
U5206 LDO; Iout = 20 mA
PR5207
2P8V_CAM_IR 20 mA
Cameras
U5205 LSW; Iout = 200 mA
PR5206
+3P3V_VCM 200 mA
Cameras Autofocus
U5201 LDO; Iout = 200 mA
R4312
+3P3V_SSD 5187 mA
R4413
+3P3V_WWAN 1500 mA
PU6502 LSW; Iout = 500 mA
Panel Logic
+1P2V_CAM_R 120 mA
Cameras
Cameras
B
A
A
5
4
3
2
5
4
3
2
SMBDAT SMBCLK
M
0x??
M
D
I2C0_SDA I2C0_CLK
SMBDAT SMBCLK
64K EEPROM U2505 0x??
I2C_SDA_RCAM I2C_SCL_RCAM
M
R2520 R2521
I2C_SDA_IRCAM I2C_SCL_IRCAM
I2C_SDA_REAR_IR_CAM I2C_SCL_REAR_IR_CAM
M
R2527 R2528
PANEL_I2C_SDA PANEL_I2C_SCL
SEN_1P8V_SDA SEN_1P8V_SCL
Accel & Gyro U3207 0x68
EDP_I2C_SDA EDP_I2C_SCL R5709 R5710
R3216 R3217
PMI0_I2C_SDA_R PMI0_I2C_SCL_R R2873 R2872
PMI1_I2C_SDA_R PMI1_I2C_SCL_R PMI2_I2C_SDA_R PMI2_I2C_SCL_R R2870 R2871
Q2101 Q2102
SEN_SDA SEN_SCL
TS_A_I2C_SDA_CON_NC TS_A_I2C_SCL_CON_NC
FCam Connector J5401 0x?? EDP Connector J5701 0x??
DNP
R3711 R3712
Silego U3501 0x??
R3228 R3230
Skin Temp U3904 0x4B
Ambient Light J3202 0x44
R3227 R3231
Skin Temp U3903 0x4A Skin Temp U3902 0x49 Skin Temp U3901 0x48
SENSOR_SDAr SENSOR_SCLr
https://vinafix.com SAM M
U3600
DNP
R3542 R3543
R7401 R7403
PECI_DATA PECI_CLK
on w/+5VSB
M
R3722 R3723
Blade Accel U7408 0x18 Host Auth U3701 0x60
Q3402 Q3412
CHG_SDA_A CHG_SCL_A PR6304 PR6306
4
3
Touch Conn J3001 0x60 PwrMonitor0 U2813 0x17 PwrMonitor1 U2802 0x12
C
PwrMonitor2 U2803 0x10
PECI U3401
0x2E
B
Charger U6302 0x09
Diag Conn J3100 0x??
R3105 R3106
BAT_SMCLK BAT_SMDATA L7003 L7004
I2C & SMBUS Map 5
D
SEN_SDA SEN_SCL
R2869 R2868
Magnetometer U3208 0x30
A
RCam Connector J5301 0x??
on w/+5VSB rail SAM_SEN_SDA SAM_SEN_SCL
Level shift
SAM_SEN_SDA SAM_SEN_SCL
IRCam Connector J4901 0x??
PMI_I2C_SDA PMI_I2C_SCL
Q2502 Q2501
B
I2C_SDA_FCAM I2C_SCL_FCAM R2522 R2523
R2107 R2110
SML1DATA SML1CLK
I2C_SDA_FCAMr I2C_SCL_FCAMr
M SML0DAT SML0CLK
M
R2510 R2519
C
M PCH_ISH_I2C1_SDA PCH_ISH_I2C1_SCL
M
PANEL_I2C_SDA PANEL_I2C_SCL
XDP Connector J1801 0x??
Debug Conn J3302
Q3102A Q3102B
M
BAT_SMB_SCL SMB_SCL BAT_SMB_SDA on w/+3P3VA railSMB_SDA
PCH U1001
1
2
Battery 0x0B J7001, J7002
A
5
4
3
2
1
EV2.5 18 Oct 2016 34
TP1001 TP1002
H_PECI_R
SP_TP_SMDP58MM SP_TP_SMDP58MM
+VCCST_CPU
C55 D55 B54 C56
SAM_PROCHOT
25,43,44,73 G
Q1001
PCIE_SSD_PERST# 30 TS_IRQ# TP1005
R1035
0
PCIE_SSD_PERST# A6 GPP_E7 A7 BA5 AY5
0201_P28
SP_TP_SMDP58MM
S
SOT-VMT3_1P2XP8XP55_P4MM-1
PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP R1025 49.9 0201_P28
R1024 49.9 0201_P28
C
R1023 49.9 0201_P28
R1022 49.9 0201_P28
RUM002N02GT2L
AT16 AU16 H66 H65
+1VSB
VCC 2
H_PROCHOT#
1
R1020 1K 0201_P28 75
0
PM_THRMTRIP#
10
U1001A SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
B
DDI Port 1: base port
DDI Port 2: SL1
47 47 47 47 47 47 47 47
DDI1_DATA0_DN DDI1_DATA0_DP DDI1_DATA1_DN DDI1_DATA1_DP DDI1_DATA2_DN DDI1_DATA2_DP DDI1_DATA3_DN DDI1_DATA3_DP
71 71 71 71 71 71 71 71
DDI2_DATA0_DN DDI2_DATA0_DP DDI2_DATA1_DN DDI2_DATA1_DP DDI2_DATA2_DN DDI2_DATA2_DP DDI2_DATA3_DN DDI2_DATA3_DP
NC
E55 F55 E58 F58 F53 G53 F56 G56 C50 D50 C52 D52 A50 B50 D51 C51
R1006 24.9 0201_P3
46 46
TP1007 SP_TP_SMDP58MM
BL_INST_ON_HNDSHK
DDPC_CTRL_CLK DDPC_CTRL_DATA RTD3_AUD_PWR 25,62,64 RTD3_AUD_PWR R1040 37,57 BL_INST_ON_HNDSHK ALL EDP_COMP
A
L13 L12
DDPB_CTRL_CLK DDPB_CTRL_DATA INT. PD
1K
N7 N8 N11 N12 E52
INT. PD
Changed DBG_D to ALL EV2.5 25 Oct 2016
100 R1038
4 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 TBL1001
5 4 3
H_PROCHOT_3P3V#
DDI
EDP_AUXN EDP_AUXP EDP_DISP_UTIL
GPP_E18/DDPB_CTRLCLK GPP_E19/DDPB_CTRLDATA GPP_E20/DDPC_CTRLCLK GPP_E21/DDPC_CTRLDATA GPP_E22/DDPD_CTRLCLK GPP_E23/DDPD_CTRLDATA EDP_RCOMP 1 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 TBL1001
DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3 GPP_E17/EDP_HPD EDP_BKLTEN EDP_BKLTCTL EDP_VDDEN
C47 C46 D46 C45 A45 B45 A47 B47
33,37
E45 F45
EDP_TX0_DN EDP_TX0_DP EDP_TX1_DN EDP_TX1_DP EDP_TX2_DN EDP_TX2_DP EDP_TX3_DN EDP_TX3_DP
57 57 57 57 57 57 57 57
EDP_AUX_DN EDP_AUX_DP
57 57
G50 F50 E48 F48 G46 F46 L9 L7 L6 N9 L10
DDPB_AUX_DN DDPB_AUX_DP DDPC_AUX_DN DDPC_AUX_DP
DNP R1019 0 0201_P28
SP_TP_SMDP58MM
DDPB_DP_HPD SL1_DP_HPD
L_BKLTEN 57 L_BKLT_CTRL 57 EDP_VDD_EN 57
SB_PWRBTN# EDP_HPD
22,37 57
TP1009 SP_TP_SMDP58MM
4
3
47 71
25,37
0201_P28
R12 R11 U13
PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS XDP_TRST# 18 PCH_JTAGX 18
C
18 18 18 18
TBL1001
TP1006
SB_PWRBTN_R#
SP_TP_SMDP58MM SP_TP_SMDP58MM SP_TP_SMDP58MM SP_TP_SMDP58MM SP_TP_SMDP58MM SP_TP_SMDP58MM
B
46 46 46 46
R1041LID_CLOSED 0
MTP1004 MTP1001 MTP1005 MTP1003 MTP1000 MTP1002
R1029 49.9 0201_P28
EDP_DISP_UTIL
B52
18
PLACE TP's on BOTTOM,
C1009 0.1u 6.3V 0201_P33
EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3] EDP
XDP_TCK 18 XDP_TDI 18 XDP_TDO 18 XDP_TMS 18 XDP_TRST#_BUF
PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS XDP_TRST# PCH_JTAGX
R1039 10K 0201
TP1008 SP_TP_SMDP58MM
5
PLACE TP's on BOTTOM,
+VCCSTG
eDP x 4
SKL_ULT
DDI1_TXN[0] DDI1_TXP[0] DDI1_TXN[1] DDI1_TXP[1] DDI1_TXN[2] DDI1_TXP[2] DDI1_TXN[3] DDI1_TXP[3] DDI2_TXN[0] DDI2_TXP[0] DDI2_TXN[1] DDI2_TXP[1] DDI2_TXN[2] DDI2_TXP[2] DDI2_TXN[3] DDI2_TXP[3]
PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP
B56 D59 A56 C59 C61 A59
https://vinafix.com
DISPLAY SIDEBANDS
46 46
+VCCIO
Y GND
R1018 0201_P28
H_THERMTRIP#
A
PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_TRST# JTAGX
XDP_TCK B61 XDP_TDI D60 XDP_TDO A61 XDP_TMS C60 XDP_TRST#_BUF B59
+3P3VA
SOT1226_P85XP85XP35_P48
10,63,66
GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3
U1002 74AUP1G07GX
+VCCST_CPU
PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST#
BPM#[0] BPM#[1] BPM#[2] BPM#[3]
R1030 1K DNP0201_P28
XDP_BPM0 XDP_BPM1 BPM#[2] BPM#[3]
XDP_BPM0 XDP_BPM1
JTAG
CPU MISC
R1026 49.9 0201_P28
18 18 TP1004 TP1003
D
SP_TP_SMDP58MM
PM_THRMTRIP#
DNP R1005 49.9 0201_P28
SP_TP_SMDP58MM
10
CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#
R1004 49.9 0201_P28
R1021 0201_P28
0402_P4-S
D63 A54 C65 C63 PROC_DETECT# A65
H_PROCHOT#_R
R1027 49.9 0201_P28 R1028 100
DNP R1037 100
SP_TP_SMDP58MM SP_TP_SMDP58MM SP_TP_SMDP58MM SP_TP_SMDP58MM SP_TP_SMDP58MM
SKL_ULT
TP_CATERR#_R
R1017 100K 0201_P28
H_PROCHOT#
R1002 499 0201_P28 C1008 47p 0201_P33 0
U1001D SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
R1033 1M 0201_P28
DNP R1016 49.9 0201_P28
R1008 1K 0201_P28
Added termination when PECI trans is DNP Intel recommended 200-400 Ohm PD
37
MTP1012 MTP1013 MTP1014 MTP1015 MTP1016
+VCCSTG
ALL
10,63,66
D
+VCCSTG
R1001 330
R1032 100K 0201_P28
D
2
5
4
3
16
16
M_A_D0 M_A_D1 M_A_D2 M_A_D3 M_A_D4 M_A_D5 M_A_D6 M_A_D7 M_A_D8 M_A_D9 M_A_D10 M_A_D11 M_A_D12 M_A_D13 M_A_D14 M_A_D15 M_A_D32 M_A_D33 M_A_D34 M_A_D35 M_A_D36 M_A_D37 M_A_D38 M_A_D39 M_A_D40 M_A_D41 M_A_D42 M_A_D43 M_A_D44 M_A_D45 M_A_D46 M_A_D47 M_B_D0 M_B_D1 M_B_D2 M_B_D3 M_B_D4 M_B_D5 M_B_D6 M_B_D7 M_B_D8 M_B_D9 M_B_D10 M_B_D11 M_B_D12 M_B_D13 M_B_D14 M_B_D15 M_B_D32 M_B_D33 M_B_D34 M_B_D35 M_B_D36 M_B_D37 M_B_D38 M_B_D39 M_B_D40 M_B_D41 M_B_D42 M_B_D43 M_B_D44 M_B_D45 M_B_D46 M_B_D47
M_A_D[15:8]
16
M_A_D[39:32]
16
M_A_D[47:40]
C
17
M_B_D[7:0]
17
M_B_D[15:8]
17
M_B_D[39:32]
17
M_B_D[47:40]
B
AL71 AL68 AN68 AN69 AL70 AL69 AN70 AN71 AR70 AR68 AU71 AU68 AR71 AR69 AU70 AU69 BB65 AW65 AW63 AY63 BA65 AY65 BA63 BB63 BA61 AW61 BB59 AW59 BB61 AY61 BA59 AY59 AY39 AW39 AY37 AW37 BB39 BA39 BA37 BB37 AY35 AW35 AY33 AW33 BB35 BA35 BA33 BB33 AY31 AW31 AY29 AW29 BB31 BA31 BA29 BB29 AY27 AW27 AY25 AW25 BB27 BA27 BA25 BB25
DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47]
DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1] DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[3] DDR0_MA[4] DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5] DDR0_ALERT# DDR0_PAR DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ
DDR CH - A
DDR_VTT_CNTL
AU53 AT53 AU55 AT55 BA56 BB56 AW56 AY56 AU45 AU43 AT45 AT43
M_A_DIM0_CLK#0 M_A_DIM0_CLK0 M_A_DIM0_CLK#1 M_A_DIM0_CLK1
16 16 16 16
M_A_DIM0_CKE0 M_A_DIM0_CKE1 M_A_DIM0_CKE2 M_A_DIM0_CKE3
16 16 16 16
M_A_DIM0_CS#0 M_A_DIM0_CS#1 M_A_DIM0_ODT0
16 16 16
16
M_A_CAA0 M_A_CAA1 M_A_CAA2 M_A_CAA3 M_A_CAA4 M_A_CAA5 M_A_CAA6 M_A_CAA7 M_A_CAA8 M_A_CAA9
M_A_CAA[9:0]
16 16
M_A_D[55:48]
16
M_A_D[63:56]
AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52
M_A_CAB0 M_A_CAB1 M_A_CAB2 M_A_CAB3 M_A_CAB4 M_A_CAB5 M_A_CAB6 M_A_CAB7 M_A_CAB8 M_A_CAB9
M_A_CAB[9:0]
16
AM70 AM69 AT69 AT70 BA64 AY64 AY60 BA60 BA38 AY38 AY34 BA34 BA30 AY30 AY26 BA26 AW50 AT52 AY67 AY68 BA67
M_A_DQS#0 M_A_DQS0 M_A_DQS#1 M_A_DQS1 M_A_DQS#4 M_A_DQS4 M_A_DQS#5 M_A_DQS5 M_B_DQS#0 M_B_DQS0 M_B_DQS#1 M_B_DQS1 M_B_DQS#4 M_B_DQS4 M_B_DQS#5 M_B_DQS5
16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17
M_A_D16 M_A_D17 M_A_D18 M_A_D19 M_A_D20 M_A_D21 M_A_D22 M_A_D23 M_A_D24 M_A_D25 M_A_D26 M_A_D27 M_A_D28 M_A_D29 M_A_D30 M_A_D31 M_A_D48 M_A_D49 M_A_D50 M_A_D51 M_A_D52 M_A_D53 M_A_D54 M_A_D55 M_A_D56 M_A_D57 M_A_D58 M_A_D59 M_A_D60 M_A_D61 M_A_D62 M_A_D63 M_B_D16 M_B_D17 M_B_D18 M_B_D19 M_B_D20 M_B_D21 M_B_D22 M_B_D23 M_B_D24 M_B_D25 M_B_D26 M_B_D27 M_B_D28 M_B_D29 M_B_D30 M_B_D31 M_B_D48 M_B_D49 M_B_D50 M_B_D51 M_B_D52 M_B_D53 M_B_D54 M_B_D55 M_B_D56 M_B_D57 M_B_D58 M_B_D59 M_B_D60 M_B_D61 M_B_D62 M_B_D63
M_A_D[31:24]
BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54
17
M_B_D[23:16]
17
M_B_D[31:24]
D SKL_ULT
M_A_D[23:16]
16 SKL_ULT
M_A_D[7:0]
AF65 AF64 AK65 AK64 AF66 AF67 AK67 AK66 AF70 AF68 AH71 AH68 AF71 AF69 AH70 AH69 AT66 AU66 AP65 AN65 AN66 AP66 AT65 AU65 AT61 AU61 AP60 AN60 AN61 AP61 AT60 AU60 AU40 AT40 AT37 AU37 AR40 AP40 AP37 AR37 AT33 AU33 AU30 AT30 AR33 AP33 AR30 AP30 AU27 AT27 AT25 AU25 AP27 AN27 AN25 AP25 AT22 AU22 AU21 AT21 AN22 AP22 AP21 AN21
DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63]
DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1] DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[3] DDR1_MA[4] DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]
https://vinafix.com DDR0_ALERT#
DIMM_VREF_CA DIMM0_VREF_DQ DIMM1_VREF_DQ
17
M_B_D[55:48]
17 R1135 0201_P28
M_B_D[63:56] 0
19 19 19
AW67
DDR1_ALERT# DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]
DDR CH - B
3 OF 20
REV = JKS BUILD-OPT = TBL1001 Source Package = SKL_ULT_1356BGA_R1
2 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001
+1P2V_DUAL U1102 74AUP1G07GX VCC DDR_PG_CTRL_S
2 1
DNP R1117 10K 0201_P28
A
Y
NC GND
+3P3VSB
+3P3V
R1114 220K 0201_P26 DNP
SOT1226_P85XP85XP35_P48
5 4
R1115 4.99K 0201_P28 DNP DDR_PG_CTRL
3
C1101 0.1u 6.3V 0201_P33 DNP
DNP
60
R1113 2M 0201_P28 DNP
A
5
1
U1001C SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
U1001B SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
D
2
4
3
2
AN45 AN46 AP45 AP46 AN56 AP55 AN55 AP53 BB42 AY42 BA42 AW42
M_B_DIM0_CLK#0 M_B_DIM0_CLK#1 M_B_DIM0_CLK0 M_B_DIM0_CLK1
17 17 17 17
M_B_DIM0_CKE0 M_B_DIM0_CKE1 M_B_DIM0_CKE2 M_B_DIM0_CKE3
17 17 17 17
M_B_DIM0_CS#0 M_B_DIM0_CS#1 M_B_DIM0_ODT0
17 17 17
AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52
M_B_CAA0 M_B_CAA1 M_B_CAA2 M_B_CAA3 M_B_CAA4 M_B_CAA5 M_B_CAA6 M_B_CAA7 M_B_CAA8 M_B_CAA9
M_B_CAA[9:0]
17
BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47
M_B_CAB0 M_B_CAB1 M_B_CAB2 M_B_CAB3 M_B_CAB4 M_B_CAB5 M_B_CAB6 M_B_CAB7 M_B_CAB8 M_B_CAB9
M_B_CAB[9:0]
17
AH66 AH65 AG69 AG70 AR66 AR65 AR61 AR60 AT38 AR38 AT32 AR32 AR25 AR27 AR22 AR21
M_A_DQS#2 M_A_DQS2 M_A_DQS#3 M_A_DQS3 M_A_DQS#6 M_A_DQS6 M_A_DQS#7 M_A_DQS7 M_B_DQS#2 M_B_DQS2 M_B_DQS#3 M_B_DQS3 M_B_DQS#6 M_B_DQS6 M_B_DQS#7 M_B_DQS7
C
16 16 16 16 16 16 16 16 17 17 17 17 17 17 17 17
DDR1_ALERT# AN43 AP43 AT13 AR18 SM_RCOMP_0 1% 200 AT18 SM_RCOMP_1 80.6 AU18 SM_RCOMP_2 1% 162
R1136 0201_P28
0
+1P2V_DUAL SM_DRAMRST# R1111 0201_P26 R1134 0201_P28 0402_P4-S R1112
DNP R1118 1M 0201_P28 B
5
4
+1P2V_DUAL
1
22u 6.3V 0603_1-W
D
Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001 SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
1u
VCCPLL_K20 VCCPLL_K21
+VCCST_CPU
VCCIO_SENSE VSSIO_SENSE C1249 1u 6.3V
VSSSA_SENSE VCCSA_SENSE
0402_P56
0
1u
6.3V 0402_P56
C1264
1u
6.3V 0402_P56
C1263
1u
6.3V 0402_P56
C1266
1u
6.3V 0402_P56
C1265
C1280 10u 6.3V 0402_P7-W
C1279 10u 6.3V 0402_P7-W
C1278 10u 6.3V 0402_P7-W
C1276 10u 6.3V 0402_P7-W
C1277 10u 6.3V 0402_P7-W
10u 6.3V 0402_P7-W
1u
6.3V 0201_P35-W
C1271
1u
6.3V 0201_P35-W
C1267
1u
6.3V 0201_P35-W
C1269
1u
6.3V 0201_P35-W
C1268
1u
6.3V 0201_P35-W
C1275
1u
6.3V 0201_P35-W
C1274
1u
+VCCSA
AM23 AM22 H21 H20
U1001L SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
VCCIO_SENSE
56
VSSSA_SENSE VCCSA_SENSE
66 66
C1281 10u 6.3V 0402_P7-W
C1282 10u 6.3V 0402_P7-W
C1283 10u 6.3V 0402_P7-W
C1284 10u 6.3V 0402_P7-W
C1286 10u 6.3V 0402_P7-W
C1285 10u 6.3V 0402_P7-W
https://vinafix.com
Place on secondary side, underneath the package +VCCEDRAM
C1252 1u 6.3V
C1253 1u 6.3V
C1250 1u 6.3V
0201_P35-W
0201_P35-W
0201_P35-W
K32 AK32
+1P8V
C1254 1u 6.3V
C1255 1u 6.3V
C1256 1u 6.3V
0201_P35-W
0201_P35-W
0201_P35-W
H63 G61
C1251 6.3V 1u 0201_P35-W
Needed for 2+3e
+VCCEOPIO
C1231 10u 6.3V 0402_P7-W
58 VCCOPC_SENSE U23E EV2.5 21 Oct 2016 Changed to U23E
C1230 10u 6.3V 0402_P7-W
Place on secondary side, underneath the package
4
AB62 P62 V62
58
VCCEOPIO_SENSE
AC63 AE63 AE62 AG62 AL63 AJ62
RSVD_K32
VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42 VCC_J30 VCC_J33 VCC_J37 VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43
VCC_SENSE VSS_SENSE
RSVD_AK32 VIDALERT# VIDSCK VIDSOUT
VCCOPC_AB62 VCCOPC_P62 VCCOPC_V62
VCCSTG_G20 VCC_OPC_1P8_H63
E32 E33 B63 A63 D64 G20
B
+VCCST_CPU
VCC_CORE_SENSE VSS_CORE_SENSE H_CPU_SVIDALERT# H_CPU_SVIDCLK H_CPU_SVIDDAT
66 66 R1216 R1209 R1207
220 0201_P28 0 0201_P28 0 0201_P28
100 0201_P28
B
VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30
+VCORE
G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43
R1212
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SKL_ULT CPU POWER 1 OF 4
56 0201_P28
A30 A34 A39 A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40 AM32 AM33 AM35 AM37 AM38 G30
R1215
+VCORE
Needed for 2+3e
C
REV = JKS
0402_P56
5
Place on secondary side, underneath the package
14 OF 20 C1248 1u 6.3V
A
+VCCSA AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30
C1272
6.3V 0402_P56
VCCPLL_OC
K20 K21
AK28 AK30 AL30 AL42 AM28 AM30 AM42
6.3V 0201_P35-W
VCCSTG_A22
0402_P4-S
C1228 10u 6.3V 0402_P7-W
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
VCCST
AL23 DNP
0402_P56
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VDDQC
A18
SLP_S4 (S3 rail)
A22
C1247
C1246 1u 6.3V
+VCCPLL_OC DNP R1202
AM40
VDDQC
from 1VSB, control +VCCSTG Place on secondary side, underneath the package
DNP 1u C1245
6.3V 0201_P35-W
10u 6.3V 0402_P7-W C1290 C
+VCCST_CPU
+VCCIO
VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51
C1273
10u 6.3V 0402_P7-W C1238
10u 6.3V 0402_P7-W
0
0402_P4-S
Place on secondary side, underneath the package
R1201
C1239
10u 6.3V 0402_P7-W C1240
C1241 10u 6.3V 0402_P7-W
SKL_ULT CPU POWER 3 OF 4
AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51
C1270 10u 6.3V 0402_P7-W
C1289
22u 6.3V 0603_1-W C1288
22u 6.3V 0603_1-W
2
Refer to Table 52-4 in PDG2.0 Do not route VCCPLL, VCCPLL_OC, VCCST closest adjacent layer over any power net other than ground U1001N
D
C1287
3
SVID_ALERT# VIDSCLK 66 VIDSOUT 66
66
+VCCSTG +VCCSTG is control by SLP_S0, but it can overwrite by XDP, that means it need power for XDP intrafece
VCC_OPC_1P8_G61 VCCOPC_SENSE VSSOPC_SENSE VCCEOPIO VCCEOPIO
A
VCCEOPIO_SENSE VSSEOPIO_SENSE 12 OF 20 REV = JKS BUILD-OPT = TBL1001 Source Package = SKL_ULT_1356BGA_R1
3
2
5
4
U1001M SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
+VCCGT
D
C
66 66
VCCGT_SENSE VSSGT_SENSE
+VCCGT
SKL_ULT CPU POWER 2 OF 4
A48 A53 A58 A62 A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71 J43 J45 J46 J48 J50 J52 J53 J55 J56 J58 J60 K48 K50 K52 K53 K55 K56 K58 K60 L62 L63 L64 L65 L66 L67 L68 L69 L70 L71 M62 N63 N64 N66 N67 N69 J70 J69
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66
VCCGT_SENSE VSSGT_SENSE
3
VCCGTX_SENSE VSSGTX_SENSE
N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62
2
1
THIS IS PLACE ON VCCGTX pins (they are connected to +VCCGT)
+VCCGT
Place on secondary side, underneath the package only for 23e U23E C1390 10u 6.3V 0402_P7-W
U23E C1391 10u 6.3V 0402_P7-W
U23E C1389 10u 6.3V 0402_P7-W
U23E C1393 10u 6.3V 0402_P7-W
U23E C1392 10u 6.3V 0402_P7-W
U23E C1394 10u 6.3V 0402_P7-W
U23E C1395 10u 6.3V 0402_P7-W
U23E C1396 10u 6.3V 0402_P7-W
D
only for 23e
only for 23e
U23E C13101 22u 6.3V 0603_1-W
ALL C1376 22u 6.3V 0603_1-W
ALL C1397 22u 6.3V 0603_1-W
ALL C1398 22u 6.3V 0603_1-W
ALL C1399 22u 6.3V 0603_1-W
ALL C1308 22u 6.3V 0603_1-W
U23E C13100 22u 6.3V 0603_1-W
ALL C13102 22u 6.3V 0603_1-W
+VCCGT +VCCGT
Place on secondary side, underneath the package AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66
C1355 10u 6.3V 0402_P7-W
C1353 10u 6.3V 0402_P7-W U23E
C1352 10u 6.3V 0402_P7-W
C1350 10u 6.3V 0402_P7-W
C1358 10u 6.3V 0402_P7-W
C1354 10u 6.3V 0402_P7-W
C1368 10u 6.3V 0402_P7-W
C1369 10u 6.3V 0402_P7-W
C1370 10u 6.3V 0402_P7-W
C13122 10u 6.3V 0402_P7-W
C13123 10u 6.3V 0402_P7-W
U23E
C1361 1u 6.3V
C1360 1u 6.3V
0201_P35-W
0201_P35-W
C1366
C1367 1u 6.3V
1u 6.3V 0201_P35-W
C1351 10u 6.3V 0402_P7-W
C1357 1u 6.3V 0201_P35-W
C1364 1u 6.3V 0201_P35-W
0201_P35-W
C1359 1u 6.3V
C1349
0201_P35-W
C1365 1u 6.3V
C1356 1u 6.3V
1u 6.3V 0201_P35-W
C1363
0201_P35-W
C13196 1u 6.3V 0201_P35-W
0201_P35-W
C1362 1u 6.3V
1u 6.3V 0201_P35-W
C13197 1u 6.3V 0201_P35-W
0201_P35-W
C
AK62 AL61
13 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 TBL1001 +VCORE
B
Place on secondary side, underneath the package
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C1315 10u 4V 0402_P65-W
C1314 10u 6.3V 0402_P7-W
C1317 10u 6.3V 0402_P7-W
C1316 10u 6.3V 0402_P7-W
C1310 10u 4V 0402_P65-W
C1311 10u 6.3V 0402_P7-W
C1312 10u 4V 0402_P65-W
C1313 10u 6.3V 0402_P7-W
C1318 10u 4V 0402_P65-W
C13179 10u 6.3V 0402_P7-W
C13182 10u 6.3V 0402_P7-W
C13180 10u 6.3V 0402_P7-W
C13184 10u 6.3V 0402_P7-W
C13178 10u 6.3V 0402_P7-W
C13183 10u 6.3V 0402_P7-W
C13181 10u 6.3V 0402_P7-W
C13185 10u 6.3V 0402_P7-W
C13186 10u 6.3V 0402_P7-W
C13188 10u 6.3V 0402_P7-W
C13191 10u 6.3V 0402_P7-W
C13189 10u 6.3V 0402_P7-W
C13193 10u 6.3V 0402_P7-W
C13187 10u 6.3V 0402_P7-W
C13192 10u 6.3V 0402_P7-W
C13190 10u 6.3V 0402_P7-W
C13194 10u 6.3V 0402_P7-W
C13195 10u 6.3V 0402_P7-W
U23E C1373 47u 6.3V 0805_1
U23E C1371 47u 6.3V 0805_1P45MM
C1382 22u 6.3V 0603_1-W
U23E C1372 47u 6.3V 0805_1P45MM
C1381 22u 6.3V 0603_1-W
C1384 22u 6.3V 0603_1-W
U23E C1374 47u 6.3V 0805_1P45MM
U23E C1375 47u 6.3V
only for 23e
0805_1P45MM
C1383 22u 6.3V 0603_1-W
C1377 22u 6.3V 0603_1-W
U23E C1387 22u 6.3V 0603_1-W
U23E C1388 22u 6.3V 0603_1-W
B
C1378 22u 6.3V 0603_1-W
C1379 22u 6.3V 0603_1-W
U23E
C1328 10u 6.3V 0402_P7-W
C1327 10u 6.3V 0402_P7-W
C1326 10u 6.3V 0402_P7-W
C1325 10u 6.3V 0402_P7-W
C1324 10u 6.3V 0402_P7-W
C1331 10u 6.3V 0402_P7-W
C1329 10u 6.3V 0402_P7-W
C1334 1u 6.3V
C1335 1u 6.3V
C1332 1u 6.3V
C1333 1u 6.3V
C1323 1u 6.3V
C1330 1u 6.3V
C1301 1u 6.3V
C1300 1u 6.3V
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
U23E C13166 47u 6.3V
C13165 47u 6.3V 0805_1P45MM
U23E C1380 22u 6.3V 0603_1-W C1306 1u 6.3V
C1307 1u 6.3V
C1304 1u 6.3V
C1305 1u 6.3V
C1302 1u 6.3V
C1303 1u 6.3V
C1309 1u 6.3V
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
C13108 1u 6.3V
C1322 1u 6.3V
C13104 1u 6.3V
C13103 1u 6.3V
C13106 1u 6.3V
C13105 1u 6.3V
C13107 1u 6.3V
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
0201_P35-W
C13115 1u 6.3V
C13109 1u 6.3V
C13111 1u 6.3V
C13110
C13113
0201_P35-W
1u 6.3V 0201_P35-W
C13114 1u 6.3V
0201_P35-W
1u 6.3V 0201_P35-W
C13112 1u 6.3V
0201_P35-W
0201_P35-W
0201_P35-W
U23E C13164 47u 6.3V
0805_1P45MM
0805_1P45MM
U23E C1385 22u 6.3V 0603_1-W
U23E C1386 22u 6.3V 0603_1-W
only for 23e
+VCORE
A
A
C1338 10u 4V 0402_P65-W
C1337 10u 4V 0402_P65-W
C1341 22u
C1342 22u
CAP_2P2X1P25X2_1P65MM
C13121 1u 6.3V
C13116 1u 6.3V
C13119 1u 6.3V
0201_P35-W
0201_P35-W
0201_P35-W
5
C13117
C13120
1u 6.3V 0201_P35-W
1u 6.3V 0201_P35-W
C13118 1u 6.3V
C1336 10u 4V 0402_P65-W
C1343 22u
C1320 10u 6.3V 0402_P7-W
C1345 22u
C1321 10u 4V 0402_P65-W
C1319 10u 4V 0402_P65-W
EV2.5 26 Oct 2016
CAP_2P2X1P25X2_1P65MM CAP_2P2X1P25X2_1P65MM CAP_2P2X1P25X2_1P65MM
C1339 10u 4V 0402_P65-W
C1348 47uF 0805S_1P25
C1347 Removed. C1348 => 47uF
0201_P35-W
4
3
2
C1340 10u 4V 0402_P65-W
C1344 47uF
C1346 47uF
0805S_1P25
0805S_1P25
5
4
3
U1001P SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
D
C
B
A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AL65 AL66 AM13 AM21 AM25 AM27 AM43 AM45 AM46 AM55 AM60 AM61 AM68 AM71 AM8 AN20 AN23 AN28 AN30 AN32 AN33 AN35 AN37 AN38 AN40 AN42 AN58 AN63 AP10 AP18 AP20 AP23 AP28 AP32 AP35 AP38 AP42 AP58 AP63 AP68 AP70 AR11 AR15 AR16 AR20 AR23 AR28 AR35 AR42 AR43 AR45 AR46 AR48 AR5 AR50 AR52 AR53 AR55 AR58 AR63 AR8 AT2 AT20 AT23 AT28 AT35 AT4 AT42 AT56 AT58
AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38 AV1 AV68 AV69 AV70 AV71 AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57 AW6 AW60 AW62 AW64 AW66 AW8 AY66 B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71 BA1 BA10 BA14 BA18 BA2 BA23 BA28 BA32 BA36 F68 BA45
16 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001
5
SKL_ULT
SKL_ULT
GND 2 OF 3
GND 3 OF 3
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41
F8 G10 G22 G43 G45 G48 G5 G52 G55 G58 G6 G60 G63 G66 H15 H18 H71 J11 J13 J25 J28 J32 J35 J38 J42 J8 K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71 L11 L16 L17
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
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VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
L18 L2 L20 L4 L8 N10 N13 N19 N21 N6 N65 N68 P17 P19 P20 P21 R13 R6 T15 T17 T18 T2 T21 T4 U10 U63 U64 U66 U67 U69 U70 V16 V17 V18 W13 W6 W9 Y17 Y19 Y20 Y21
18 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001
17 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001 4
1
U1001R SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
U1001Q SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
SKL_ULT GND 1 OF 3
A5 A67 A70 AA2 AA4 AA65 AA68 AB15 AB16 AB18 AB21 AB8 AD13 AD16 AD19 AD20 AD21 AD62 AD8 AE64 AE65 AE66 AE67 AE68 AE69 AF1 AF10 AF15 AF17 AF2 AF4 AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13 AH6 AH63 AH64 AH67 AJ15 AJ18 AJ20 AJ4 AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69 AK8 AL2 AL28 AL32 AL35 AL38 AL4 AL45 AL48 AL52 AL55 AL58 AL64
2
3
D
C
B
5
4
3
2
1
U1001S SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
TP1516
SKL_ULT RESERVED SIGNALS-1 D
E68 B67 D65 D67 E70 C68 D68 C67 F71 G69 F70 G68 H70 G71 H69 G70
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
CFG16 CFG17
18 18
CFG18 CFG19
E63 F63 E66 F66 CFG_RCOMP
R1507 49.9 0201_P28
C
CFG4
18
0 Default
enable eDP
1
Disable eDP
E60 E8
ITP_PMODE
AY2 AY1 R1501 1K 0201_P28
D1 D3 K46 K45 AL25 AL27
CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]
RSVD_TP_BB68 RSVD_TP_BB69 RSVD_TP_AK13 RSVD_TP_AK12 RSVD_BB2 RSVD_BA3 TP5 TP6 RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2
CFG[16] CFG[17]
RSVD_B3 RSVD_A3
CFG[18] CFG[19]
RSVD_AW1 CFG_RCOMP RSVD_E1 RSVD_E2
ITP_PMODE RSVD_AY2 RSVD_AY1
RSVD_BA4 RSVD_BB4
RSVD_D1 RSVD_D3
RSVD_A4 RSVD_C4
RSVD_K46 RSVD_K45
TP4 RSVD_A69 RSVD_B69
https://vinafix.com C71 B70
F60
U1001T SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
A52 BA70 BA68
B SKL_ULT SPARE
+1P8VSUS_ORG
ALL C1501 1u 0402_P56 6.3V
AW69 AW68 AU56 AW48 C7 U12 U11 H11
RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11
RSVD_F6 RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52
F6 E3 C11 B11 A11 D12 C12 F52
J71 J68 F65 G65 F61 E61
RSVD_AL25 RSVD_AL27
RSVD_AY3
RSVD_C71 RSVD_B70
RSVD_D71 RSVD_C70
RSVD_F60 RSVD_C54 RSVD_D54
RSVD_A52 RSVD_TP_BA70 RSVD_TP_BA68
TP1 TP2
RSVD_J71 RSVD_J68
VSS_AY71 ZVM#
VSS_F65 VSS_G65
RSVD_TP_AW71 RSVD_TP_AW70
RSVD_F61 RSVD_E61
MSM# PROC_SELECT#
BB68 BB69 AK13 AK12
D
TP1503 SP_TP_SMDP58MM TP1502 SP_TP_SMDP58MM
RSVD_TP_AK13 RSVD_TP_AK12
BB2 BA3 AU5 AT5 D5 D4 B2 C2 B3 A3 AW1 C
E1 E2 BA4 BB4 A4 C4 BB5 A69 B69 AY3
RSVD_AY3
R1502
0
0201_P28
D71 C70
DNP
C54 D54 AY4 BB3
B
AY71 AR56
AP56 C64 PROC_SELECT#
REV = JKS TBL1001 Source Package = SKL_ULT_1356BGA_R1
R1540 0201_P28 DNP
100K
W x H 367 x 237 mm
TP1517
A
5
4
3
58
MSM#
58
+VCCST_CPU
19 OF 20 20 OF 20 REV = JKS TBL1001 Source Package = SKL_ULT_1356BGA_R1
ZVM#
AW71 AW70
2
SP_TP_SMDP58MM
DQS1 DQS1#
P10 P11
DQS2/NC DQS2#/NC
D10 D11
M_A_DQS5 M_A_DQS#5
DQS3/NC DQS3#/NC
B2 B5 C5 E4 E5 F5 H2 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5
+1P2V_DUAL
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19
VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5
0201_P33
0201_P33
0201_P33
C1609 1u 6.3V
C1610 1u 6.3V
0402_P56
0402_P56
Please refer to PDG 2.0 Figure 4-55 Pink circles C1608 1u 6.3V
+1P8V_DUAL
C1611 1u 6.3V
GND
C1659 100p 25V
M_A_CAB0 M_A_CAB1 M_A_CAB2 M_A_CAB3 M_A_CAB4 M_A_CAB5 M_A_CAB6 M_A_CAB7 M_A_CAB8 M_A_CAB9
R1615 R1616 R1617 R1618 R1619 R1620 R1621 R1622 R1623 R1624
68 68 68 68 68 68 68 68 68 68
5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28
11,16 11,16 11,16 11,16 11,16 11,16 11,16
M_A_DIM0_ODT0 M_A_DIM0_CS#0 M_A_DIM0_CS#1 M_A_DIM0_CKE0 M_A_DIM0_CKE1 M_A_DIM0_CKE2 M_A_DIM0_CKE3
R1629 R1634 R1635 R1637 R1638 R1639 R1640
80.6 80.6 80.6 80.6 80.6 80.6 80.6
0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28
11,16 11,16 11,16 11,16
M_A_DIM0_CLK0 M_A_DIM0_CLK#0 M_A_DIM0_CLK1 M_A_DIM0_CLK#1
R1630 R1631 R1632 R1633
37.4 37.4 37.4 37.4
0201_P28 0201_P28 0201_P28 0201_P28
A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9
TBL1601
+1P2V_DUAL C1658 100p 25V 0201_P33 C
GND
F2 G2 H3 L2 M2
+1P2V_DUAL
C3 D3 F4 G3 G4 J4 M4 P3
B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12
+V_VREF_CA_DIMM +V_VREF_DQ_DIMM0 M_A_DIM0_ODT0
11,16
0201S_P26 0201S_P26
C4 K9 R3
VSSCA1 VSSCA2 VSSCA3 VSSCA4 VSSCA5 VSSCA6 VSSCA7 VSSCA8
GND GND
Please refer to PDG 2.0 Figure 4-57 Edge of VTT island. Caps shown in green
VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17
+1P2V_DUAL
VREFCA VREFDQ ODT ZQ0 ZQ1 NC1 NC2 NC3
A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11
+1P2V_DUAL
Please refer to PDG 2.0 Figure 4-56 Blue circles Distributed
H4 J11 J8 B3 B4 C4 K9 R3
C1615 10u
6.3V
C1616 10u
6.3V
+V_VREF_CA_DIMM +V_VREF_DQ_DIMM0 M_A_DIM0_ODT0 ZQ1603 ZQ1604
ALL R1603 R1604 TBL1601
GND
11,16 243 243
B
C1617 10u
6.3V
Please refer to PDG 2.0 Figure 4-56 Yellow circles Distributed
0201S_P26 0201S_P26
C1667 10u 6.3V
GND
C1666 10u 6.3V
GND
Please refer to PDG 2.0 Figure 4-55 4 near each device
TBL1601
+V_VDDQ_VTT
C1618 1u 6.3V
C1619 1u 6.3V
C1621 1u 6.3V
C1620 1u 6.3V
Red Circles
C1622 1u 6.3V
C1624 1u 6.3V
C1623 1u 6.3V
C1628 1u 6.3V
C1612 10u 6.3V
GND
Please refer to PDG 2.0 Figure 4-55 Yellow Circles-- 2 near each device
0201_P33
C1614 10u 6.3V
GND
C1631 1u 6.3V
C1625 1u 6.3V
C1627 1u 6.3V
GND
C1626 1u 6.3V
C1629 1u 6.3V
C1630 1u 6.3V
C1635 1u 6.3V
C1633 1u 6.3V
C1634 1u 6.3V
W x H 602 x 390 mm
GND
0201_P33
Please refer to PDG 2.0 Figure 4-55 Red Circles-- 2 near each device C1636 0.1u 6.3V
C1637 0.1u 6.3V
C1638 0.1u 6.3V
C1639 0.1u 6.3V
GND 4
3
Please refer to PDG 2.0 Figure 4-56 Red circles Distributed
Please refer to PDG 2.0 Figure 4-55 Blue Circles-- 3 near each device 0402_P56
C1662 100p 25V
C1665 22u 6.3V 0603_1-W
GND
5
C1613 10u 6.3V
+V_VDDQ_VTT C1646 1u 6.3V
D
0201_P33
GND
GND A
0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28
https://vinafix.com
+1P2V_DUAL
ALL ZQ1601 R1601 243 ZQ1602 R1602 243 TBL1601
VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8 VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20
5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
11
0402_P56
C1644 1u 6.3V
G10 G11
GND M_A_D[47:40]
0402_P56
C1643 1u 6.3V
11 11
TBL1601
0402_P56
C1641 1u 6.3V
M_A_DQS6 M_A_DQS#6
0402_P7-W 6.3V
68 68 68 68 68 68 68 68 68 68
0402_P7-W
NC1 NC2 NC3
B3 B4
M_A_DQS4 M_A_DQS#4
11 11
0402_P7-W 6.3V
R1605 R1606 R1607 R1608 R1609 R1610 R1611 R1612 R1613 R1614
0402_P7-W
ZQ0 ZQ1
J8
GND
11 11
0402_P7-W 6.3V
0402_P7-W
ODT
H4 J11
Please refer to PDG 2.0 Figure 4-57 Distribute along terminations - Caps in blue 0402_P56
0402_P56
+V_VDDQ_VTT
VREFCA VREFDQ
A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11
0201_P33
DQS0 DQS0#
C1607 10u
0402_P56
GND
VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17
F2 G2 H3 L2 M2
C1661 100p 25V
L10 L11
M_A_DQS7 M_A_DQS#7
A3 A4 A5 A6 A10 U3 U4 U5 U6 U10
C1606 10u
0402_P56
B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12
B
VSSCA1 VSSCA2 VSSCA3 VSSCA4 VSSCA5 VSSCA6 VSSCA7 VSSCA8
VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5
11 11
+1P2V_DUAL
VDD1_1 VDD1_3 VDD1_5 VDD1_7 VDD1_9 VDD1_2 VDD1_4 VDD1_6 VDD1_8 VDD1_10
C1605 10u
0402_P56
C3 D3 F4 G3 G4 J4 M4 P3
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19
0201_P33
GND
DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 DNU9 DNU10 DNU11 DNU12
11
M_A_CAA0 M_A_CAA1 M_A_CAA2 M_A_CAA3 M_A_CAA4 M_A_CAA5 M_A_CAA6 M_A_CAA7 M_A_CAA8 M_A_CAA9
M_A_CAB[9:0]
11,16
0402_P56
B2 B5 C5 E4 E5 F5 H2 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5
DQS3/NC DQS3#/NC
C1660 100p 25V
A1 A2 A12 A13 B1 B13 T1 T13 U1 U2 U12 U13
GND
0402_P56
D10 D11
DQS2/NC DQS2#/NC
GND
+1P8V_DUAL
DM0 DM1 DM2 DM3/NC
M_A_D[55:48]
GND
Please refer to PDG 2.0 Figure 4-56 Pink circles
0402_P56
M_A_DQS1 M_A_DQS#1
C
DQS1 DQS1#
CS#0 CS#1
L8 G8 P8 D8
GND
M_A_CAA[9:0]
C1604 47000p 6.3V
0402_P56
11 11
P10 P11
A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9
L3 L4
GND +1P8V_DUAL
C1603 47000p 6.3V
0402_P56
M_A_DQS3 M_A_DQS#3
VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8 VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20
M_A_DIM0_CS#0 M_A_DIM0_CS#1
11
C1602 47000p 6.3V
0402_P56
M_A_DQS0 M_A_DQS#0
11 11
DQS0 DQS0#
A3 A4 A5 A6 A10 U3 U4 U5 U6 U10
11,16 11,16 11
M_A_D[39:32]
C1601 47000p 6.3V
11,16
+V_VREF_DQ_DIMM0
0201_P33
11 11
G10 G11
VDD1_1 VDD1_3 VDD1_5 VDD1_7 VDD1_9 VDD1_2 VDD1_4 VDD1_6 VDD1_8 VDD1_10
M_A_D[15:8]
CKE0 CKE1
+V_VREF_CA_DIMM
0201_P33
M_A_DQS2 M_A_DQS#2
DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 DNU9 DNU10 DNU11 DNU12
0402_P56
11 11
L10 L11
DM0 DM1 DM2 DM3/NC
K3 K4
11
0402_P7-W
A1 A2 A12 A13 B1 B13 T1 T13 U1 U2 U12 U13
GND
CS#0 CS#1
M_A_DIM0_CKE0 M_A_DIM0_CKE1
M_A_D[63:56]
M_A_D58 M_A_D61 M_A_D56 M_A_D57 M_A_D60 M_A_D59 M_A_D62 M_A_D63 M_A_D37 M_A_D38 M_A_D32 M_A_D36 M_A_D33 M_A_D39 M_A_D34 M_A_D35 M_A_D52 M_A_D51 M_A_D50 M_A_D48 M_A_D53 M_A_D54 M_A_D55 M_A_D49 M_A_D41 M_A_D45 M_A_D44 M_A_D46 M_A_D40 M_A_D47 M_A_D42 M_A_D43
0402_P56
L8 G8 P8 D8
11,16 11,16
P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8
0402_P56
L3 L4
CK CK#
11
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16/NC DQ17/NC DQ18/NC DQ19/NC DQ20/NC DQ21/NC DQ22/NC DQ23/NC DQ24/NC DQ25/NC DQ26/NC DQ27/NC DQ28/NC DQ29/NC DQ30/NC DQ31/NC
0402_P7-W
M_A_DIM0_CS#0 M_A_DIM0_CS#1
CKE0 CKE1
M_A_D[31:24]
J3 J2
M_A_DIM0_CLK0 M_A_DIM0_CLK#0
11,16 11,16
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9
0402_P7-W
11,16 11,16
K3 K4
11
R2 P2 N2 N3 M3 F3 E3 E2 D2 C2
0402_P56
M_A_DIM0_CKE2 M_A_DIM0_CKE3
M_A_D[7:0]
M_A_CAB0 M_A_CAB1 M_A_CAB2 M_A_CAB3 M_A_CAB4 M_A_CAB5 M_A_CAB6 M_A_CAB7 M_A_CAB8 M_A_CAB9
0201_P33
11,16 11,16
11
M_A_D[23:16]
M_A_D16 M_A_D17 M_A_D23 M_A_D18 M_A_D21 M_A_D20 M_A_D22 M_A_D19 M_A_D7 M_A_D0 M_A_D4 M_A_D1 M_A_D6 M_A_D3 M_A_D5 M_A_D2 M_A_D29 M_A_D28 M_A_D31 M_A_D26 M_A_D25 M_A_D24 M_A_D27 M_A_D30 M_A_D9 M_A_D12 M_A_D15 M_A_D11 M_A_D13 M_A_D8 M_A_D14 M_A_D10
0402_P56
D
P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8
0402_P56
CK CK#
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16/NC DQ17/NC DQ18/NC DQ19/NC DQ20/NC DQ21/NC DQ22/NC DQ23/NC DQ24/NC DQ25/NC DQ26/NC DQ27/NC DQ28/NC DQ29/NC DQ30/NC DQ31/NC
0402_P7-W
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9
1
+V_VDDQ_VTT
0402_P7-W
J3 J2
M_A_DIM0_CLK1 M_A_DIM0_CLK#1
11,16 11,16
R2 P2 N2 N3 M3 F3 E3 E2 D2 C2
2
0402_P56
M_A_CAA0 M_A_CAA1 M_A_CAA2 M_A_CAA3 M_A_CAA4 M_A_CAA5 M_A_CAA6 M_A_CAA7 M_A_CAA8 M_A_CAA9
3
U1602 H9CCNNN8JTALAR-NTD BGA178_11P1X11P6X1_P8XP65
M_A_CAB[9:0]
0402_P56
M_A_CAA[9:0]
11,16
0201_P33
11,16
4
U1601 H9CCNNN8JTALAR-NTD BGA178_11P1X11P6X1_P8XP65
0402_P56
5
2
C1632 1u 6.3V
A
B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12
GND
VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
VREFCA VREFDQ ODT ZQ0 ZQ1
C3 D3 F4 G3 G4 J4 M4 P3
M_B_DIM0_ODT0 ALL ZQ1701 R1701 ZQ1702 R1702
B3 B4
B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12
+V_VREF_CA_DIMM +V_VREF_DQ_DIMM1
J8
243 243
11,17
0201S_P26 0201S_P26
TBL1601
NC1 NC2 NC3
C4 K9 R3
GND GND
TBL1601
Please refer to PDG 2.0 Figure 4-57 Edge of VTT island. Caps shown in green
0603_1-W
C1735 1u 6.3V
0402_P56
0402_P56
0402_P56
0402_P56
C1733 1u 6.3V
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19
VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5
VSSCA1 VSSCA2 VSSCA3 VSSCA4 VSSCA5 VSSCA6 VSSCA7 VSSCA8 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17
VREFCA VREFDQ ODT ZQ0 ZQ1
C1742 1u 6.3V
C1751 22u 6.3V
0201_P33
0201_P33
0402_P56
C1711 1u 6.3V
11,17 11,17 11,17 11,17
GND
5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28
M_B_CAB0 M_B_CAB1 M_B_CAB2 M_B_CAB3 M_B_CAB4 M_B_CAB5 M_B_CAB6 M_B_CAB7 M_B_CAB8 M_B_CAB9
R1714 R1716 R1715 R1717 R1719 R1720 R1721 R1735 R1722 R1723
68 68 68 68 68 68 68 68 68 68
5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28
R1724 R1725 R1726 R1727 R1728 R1729 R1730
80.6 80.6 80.6 80.6 80.6 80.6 80.6
0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28 0201_P28
R1731 R1732 R1733 R1734
37.4 37.4 37.4 37.4
0201_P28 0201_P28 0201_P28 0201_P28
M_B_DIM0_ODT0 M_B_DIM0_CS#0 M_B_DIM0_CS#1 M_B_DIM0_CKE0 M_B_DIM0_CKE1 M_B_DIM0_CKE2 M_B_DIM0_CKE3 M_B_DIM0_CLK0 M_B_DIM0_CLK#0 M_B_DIM0_CLK1 M_B_DIM0_CLK#1
D
C
+1P2V_DUAL C1759 100p 25V 0201_P33
Please refer to PDG 2.0 Figure 4-56 Red circles Distributed
Please refer to PDG 2.0 Figure 4-56 Blue circles Distributed
Please refer to PDG 2.0 Figure 4-56 Yellow circles Distributed
GND C1745 10u 6.3V
C1744 10u 6.3V
C1743 10u 6.3V
C1746 10u 6.3V
C1747 10u 6.3V
GND
F2 G2 H3 L2 M2
Please refer to PDG 2.0 Figure 4-55 4 near each device
+1P2V_DUAL
A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11
C1719 1u 6.3V
C1712 1u 6.3V
C1714 1u 6.3V
C1713 1u 6.3V
C1715 1u 6.3V
Red Circles
C1718 1u 6.3V
C1716 1u 6.3V
C1724 1u 6.3V
+1P2V_DUAL
GND
Please refer to PDG 2.0 Figure 4-55 Blue Circles-- 3 near each device
C1726 1u 6.3V
C1720 1u 6.3V
C1722 1u 6.3V
C1721 1u 6.3V
Please refer to PDG 2.0 Figure 4-55 Yellow Circles-- 2 near each device
C1723 1u 6.3V
C1725 1u 6.3V
C1727 1u 6.3V
C1728 1u 6.3V
C1730 1u 6.3V
B
C1729 1u 6.3V
GND
H4 J11
Please refer to PDG 2.0 Figure 4-55 Red Circles-- 2 near each device
+V_VREF_CA_DIMM +V_VREF_DQ_DIMM1
J8
M_B_DIM0_ODT0 ALL ZQ1703 R1703 ZQ1704 R1704
243 243
11,17
C1736 0.1u 6.3V
C1737 0.1u 6.3V
C4 K9 R3
C1738 0.1u 6.3V
C1739 0.1u 6.3V
0201S_P26 0201S_P26 GND
GND
TBL1601
+V_VDDQ_VTT
Vinafix.com
C1761 100p 25V
GND GND
4
C1710 1u 6.3V
11,17 11,17 11,17 11,17 11,17 11,17 11,17
+1P2V_DUAL
GND
5
0402_P7-W
0402_P7-W
C1709 1u 6.3V
0402_P56
C1708 1u 6.3V
0402_P56
Please refer to PDG 2.0 Figure 4-55 Pink circles
TBL1601
NC1 NC2 NC3
M_B_CAB[9:0]
GND
A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9
B3 B4
0201_P33
0201_P33
+1P8V_DUAL C1760 100p 25V 0201_P33
+V_VDDQ_VTT
+V_VDDQ_VTT
C1731 1u 6.3V
DQS3/NC DQS3#/NC
11,17
C1706 10u 6.3V
GND
https://vinafix.com
+1P2V_DUAL
H4 J11
DQS2/NC DQS2#/NC
C1705 10u 6.3V
68 68 68 68 68 68 68 68 68 68
0402_P56
+1P2V_DUAL
A11 C12 E8 E12 G12 H8 H9 H11 J9 J10 K8 K11 L12 N8 N12 R12 U11
D10 D11
DQS1 DQS1#
11
R1718 R1705 R1706 R1707 R1708 R1709 R1710 R1711 R1712 R1713
GND
Please refer to PDG 2.0 Figure 4-56 Pink circles
0402_P7-W
M_B_DQS7 M_B_DQS#7
P10 P11
M_B_D[63:56]
GND
C1704 47000p 6.3V
0402_P56
11 11
G10 G11
B2 B5 C5 E4 E5 F5 H2 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5
Please refer to PDG 2.0 Figure 4-57 Distribute along terminations - Caps shown in blue A
M_B_DQS4 M_B_DQS#4
GND
+1P8V_DUAL
C1703 47000p 6.3V
0402_P56
F2 G2 H3 L2 M2
M_B_DQS5 M_B_DQS#5
11 11
11
C1702 47000p 6.3V
0402_P7-W
GND
11 11
VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8 VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20
GND
M_B_CAA0 M_B_CAA1 M_B_CAA2 M_B_CAA3 M_B_CAA4 M_B_CAA5 M_B_CAA6 M_B_CAA7 M_B_CAA8 M_B_CAA9
0402_P56
VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17
VSSCA1 VSSCA2 VSSCA3 VSSCA4 VSSCA5 VSSCA6 VSSCA7 VSSCA8
C1758 100p 25V 0201_P33
DQS0 DQS0#
C1701 47000p 6.3V
0402_P56
VDDCA1 VDDCA2 VDDCA3 VDDCA4 VDDCA5
L10 L11
M_B_DQS6 M_B_DQS#6
+1P2V_DUAL
A3 A4 A5 A6 A10 U3 U4 U5 U6 U10
+V_VREF_DQ_DIMM1
0402_P56
B
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19
11 11
A8 A9 D4 D5 D6 G5 H5 H6 H12 J5 J6 K5 K6 K12 L5 P4 P5 P6 U8 U9
VDD1_1 VDD1_3 VDD1_5 VDD1_7 VDD1_9 VDD1_2 VDD1_4 VDD1_6 VDD1_8 VDD1_10
M_B_D[39:32]
M_B_CAA[9:0]
0402_P56
C3 D3 F4 G3 G4 J4 M4 P3
DQS3/NC DQS3#/NC
GND
DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 DNU9 DNU10 DNU11 DNU12
+V_VREF_CA_DIMM
11
0402_P56
B2 B5 C5 E4 E5 F5 H2 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5
DQS2/NC DQS2#/NC
+1P8V_DUAL C1749 100p 25V 0201_P33
A1 A2 A12 A13 B1 B13 T1 T13 U1 U2 U12 U13
DM0 DM1 DM2 DM3/NC
M_B_D[47:40]
0402_P56
D10 D11
DQS1 DQS1#
GND
CS#0 CS#1
+V_VDDQ_VTT 11,17
0402_P56
M_B_DQS1 M_B_DQS#1
P10 P11
L8 G8 P8 D8
11
0201_P33
11 11
G10 G11
L3 L4
M_B_DIM0_CS#0 M_B_DIM0_CS#1
11
CKE0 CKE1
M_B_D[55:48]
M_B_D54 M_B_D53 M_B_D49 M_B_D48 M_B_D55 M_B_D52 M_B_D50 M_B_D51 M_B_D45 M_B_D47 M_B_D42 M_B_D46 M_B_D44 M_B_D43 M_B_D41 M_B_D40 M_B_D33 M_B_D32 M_B_D37 M_B_D36 M_B_D34 M_B_D38 M_B_D39 M_B_D35 M_B_D56 M_B_D59 M_B_D60 M_B_D62 M_B_D57 M_B_D58 M_B_D61 M_B_D63
P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8
0402_P7-W
M_B_DQS2 M_B_DQS#2
VDD2_1 VDD2_2 VDD2_3 VDD2_4 VDD2_5 VDD2_6 VDD2_7 VDD2_8 VDD2_9 VDD2_10 VDD2_11 VDD2_12 VDD2_13 VDD2_14 VDD2_15 VDD2_16 VDD2_17 VDD2_18 VDD2_19 VDD2_20
11,17 11,17 M_B_D[15:8]
K3 K4
M_B_DIM0_CKE2 M_B_DIM0_CKE3
11,17 11,17
CK CK#
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16/NC DQ17/NC DQ18/NC DQ19/NC DQ20/NC DQ21/NC DQ22/NC DQ23/NC DQ24/NC DQ25/NC DQ26/NC DQ27/NC DQ28/NC DQ29/NC DQ30/NC DQ31/NC
0402_P56
M_B_DQS3 M_B_DQS#3
11 11
DQS0 DQS0#
A3 A4 A5 A6 A10 U3 U4 U5 U6 U10
11
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9
0402_P56
11 11
VDD1_1 VDD1_3 VDD1_5 VDD1_7 VDD1_9 VDD1_2 VDD1_4 VDD1_6 VDD1_8 VDD1_10
M_B_D[23:16]
J3 J2
M_B_DIM0_CLK1 M_B_DIM0_CLK#1
11,17 11,17
U1702 H9CCNNN8JTALAR-NTD BGA178_11P1X11P6X1_P8XP65
R2 P2 N2 N3 M3 F3 E3 E2 D2 C2
1
0201_P33
C
L10 L11
M_B_DQS0 M_B_DQS#0
DNU1 DNU2 DNU3 DNU4 DNU5 DNU6 DNU7 DNU8 DNU9 DNU10 DNU11 DNU12
11
M_B_CAB0 M_B_CAB1 M_B_CAB2 M_B_CAB3 M_B_CAB4 M_B_CAB5 M_B_CAB6 M_B_CAB7 M_B_CAB8 M_B_CAB9
0402_P56
11 11
A1 A2 A12 A13 B1 B13 T1 T13 U1 U2 U12 U13
M_B_CAB[9:0]
0402_P56
GND
DM0 DM1 DM2 DM3/NC
M_B_D[31:24]
11,17
0201_P33
L8 G8 P8 D8
CS#0 CS#1
11
0402_P7-W
L3 L4
M_B_DIM0_CS#0 M_B_DIM0_CS#1
M_B_D[7:0]
M_B_D0 M_B_D1 M_B_D4 M_B_D3 M_B_D2 M_B_D6 M_B_D5 M_B_D7 M_B_D25 M_B_D29 M_B_D27 M_B_D26 M_B_D24 M_B_D28 M_B_D30 M_B_D31 M_B_D19 M_B_D23 M_B_D21 M_B_D16 M_B_D22 M_B_D18 M_B_D17 M_B_D20 M_B_D13 M_B_D15 M_B_D10 M_B_D11 M_B_D12 M_B_D8 M_B_D9 M_B_D14
0402_P56
11,17 11,17
CKE0 CKE1
P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8
0402_P56
K3 K4
M_B_DIM0_CKE0 M_B_DIM0_CKE1
11,17 11,17
CK CK#
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16/NC DQ17/NC DQ18/NC DQ19/NC DQ20/NC DQ21/NC DQ22/NC DQ23/NC DQ24/NC DQ25/NC DQ26/NC DQ27/NC DQ28/NC DQ29/NC DQ30/NC DQ31/NC
0402_P56
J3 J2
M_B_DIM0_CLK0 M_B_DIM0_CLK#0
11,17 11,17
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9
0402_P7-W
R2 P2 N2 N3 M3 F3 E3 E2 D2 C2
0402_P56
U1701 H9CCNNN8JTALAR-NTD BGA178_11P1X11P6X1_P8XP65
M_B_CAA0 M_B_CAA1 M_B_CAA2 M_B_CAA3 M_B_CAA4 M_B_CAA5 M_B_CAA6 M_B_CAA7 M_B_CAA8 M_B_CAA9
2
0402_P56
D
M_B_CAA[9:0]
3
0201_P33
11,17
4
0201_P33
5
3
2
A
5
4
3
2
1
PRIMARY XDP connector D
D
15,18
CFG3
ROUTE WITH MINIMAL STUB WITH RESPECT TO CFG R1841 1K +1VSB_XDP
+1VSB
21
R1846
SPI0_MOSI_XDP
15,18
XDP_MOSI_R
CFG0 21
PC1804 0.1u 6.3V
GND
PC1805 10 0.1u 6.3V
GND
PCH_JTAG_TCK 10 XDP_TCK 10
PCH_JTAGX
CFG4 CFG5
21
R1821
0 DNP R1853 R1811
R1843
0
XDP_CFG0
CFG10 CFG11
15 15
CFG19 CFG18
15 15
CFG12 CFG13
15 15
CFG14 CFG15
15 15
CLK_XDP_R_DP CLK_XDP_R_DN
+3P3V
15 15
+1VSB_XDP
CFG8 CFG9
15 15
DNP R1825 49.9 Place R1825 within 1100mil from CPU
XDP_RST#_R XDP_DBRESET#_R
https://vinafix.com DNP
SMBDATA SMBCLK
XDP_TCK1
0 0
61 63
GND
B
MTG1 MTG3
GND
21
XDP_SPI0_IO2
XDP_TDO_BUF
R1805 R1806 R1837 R1808 R1810
0 0 0 1K 0
R1809 R1849 R1851
0 0 0
R1845
0
R1822
0
R1848
0
R1847
0
DNP
R18175
1K
XDP_PRESENT#
A
For the signals only go to XDP, the 0R should be close to XDP connector. For the signals to both XDP and target circuit, the option resistor locaction should follow the target signal routing.
4
3
B
GND 0
R1854
5
DNP R1852 0
GND GND
CLK_XDP_DP 20 CLK_XDP_DN 20 ITP_PMODE 15 PLT_RST_BUF# 22,33,37,38,43,44,73,75 PCH_SYS_RST# 22 XDP_TRST#_BUF 10 XDP_TDO 10 XDP_TRST# 10 XDP_TDI 10 XDP_TMS 10
DNP
C1801 0.01u 10V
62 64
MTG2 MTG4
C
+VCCSTG
1K
15 15
15 CFG6 15 CFG7 PM_RSMRST_PWRGD_XDP PM_PWRBTN#_XDP
GND R1807 R1804
XDP_BPM0 XDP_BPM1
CFG17 CFG16
R1823
R1826 1.5K
R1842 22,33,37 RSMRST# 22 XDP_PCH_PWRBTN# 31,33,35 PWRBTN#
CFG2 CFG3
10 10
DNP C1803 1u 6.3V
1K 0 0 DNP 0
15 15,18
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 XDP_TDI_R 58 60 XDP_PIN60
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
+1VSB_XDP
+3P3VSB
CFG0 CFG1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
1K
+1VSB_XDP C
RECEPTACLE
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
XDP_PREQ# XDP_PRDY# 15,18 15
X869110-001
CONN_B2B-R_60-X869110-001
R1844
24 24
0
XDP_D J1801
XDP_PIN1
0
R1803
R1838
R1840 DNP 49.9
+1VSB_XDP
61
PCH_JTAG_TDI
10
PCH_JTAG_TMS
10
PCH_JTAG_TDO
10
5
4
3
2
1
LPDDR3 Vref M3: CPU driven VREF path is stuffed be default. M1: VREF_DQ driven by a Voltage Divider Network during Processor power-off D
D
+1P2V_DUAL
+1P2V_DUAL
R1901 8.2K
+V_VREF_DQ_DIMM0
R1909 8.2K
+V_VREF_CA_DIMM
0201_P26
11
R1903
DIMM0_VREF_DQ
0201_P26
10
R1911
0402_P4-S
5.1
DIMM_VREF_CA
0201_P26
C1901 0.022u 16V 0201_P33
11
C1903 0.022u 16V 0201_P33 R1902 8.2K
DIMM0_VREF_DQ_C
R1910 8.2K
0201_P26
0201_P26
R1904 24.9 0402_P4-S
R1912 24.9 0402_P4-S
DNP R1913 0
C
DIMM_VREF_CA_C
C
0201_P28
GND GND +1P2V_DUAL
R1905 8.2K 0201_P26
11
R1907
DIMM1_VREF_DQ
+V_VREF_DQ_DIMM1
https://vinafix.com
10
0402_P4-S
C1902 0.022u 16V 0201_P33 R1906 8.2K
N1902
0201_P26 B
B
R1908 24.9 0402_P4-S
Intel 0203 M3+M1: Default Recommendation GND
+V_VREF_DQ_DIMM0
+VDDQ_VREF DNP R1914 0 0402_P4-S DNP R1915 0 0402_P4-S DNP R1916 0 0402_P4-S
A
5
4
3
+V_VREF_CA_DIMM
+V_VREF_DQ_DIMM1
5
4
3
2
1
+3P3V
R2048 10K 0201_P28
U1001J SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
SSD_PCIECLK_REQ_BUF#
20
SSD2_PCIECLK_REQ_BUF#
43 43
PCIECLK_SSD_DN PCIECLK_SSD_DP
B42 A42 AT7
44 44
PCIECLK_SSD2_DN PCIECLK_SSD2_DP
D41 C41 AT8
32 73
EXPSSD_PCIECLK_REQ#
CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 GPP_B5/SRCCLKREQ0#
XTAL24_IN XTAL24_OUT
CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 GPP_B8/SRCCLKREQ3#
XCLK_BIASREF RTCX1 RTCX2
CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 GPP_B9/SRCCLKREQ4#
A1
C
VCCA
VCCB
0.1u R2086
0201_P28
A
B
C2
XCLK_BIASREF RTC_X1 RTC_X2
R2005 0201_P28 C2001 15p 25V 0201_P33 2%
R2002 20K
R2021 20K
0201_P28
0201_P28
R2090
CTAL_1
1
2
DNP R2022 60.4
X2001 32.768KHZ
0201_P28
XTAL_3P2X1P5XP9_2P5MM
C2002 15p 25V 0201_P33 2% C
20 C2004 1u
+3P3VSB
1K
0
10M
RTC_RST#
+1P8V_SSD
B2
R2036 1% 2.7K 0402_P4-S R2001 0201_P28
+VCC_RTC
DNP OE
0201_P33
R2009 1K 0201_P28
C2003 1u 6.3V
0402_P56
U1001G SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
0402_P56
G
RTCRST_CTRL_FET
0
6.3V
RTCRST_CTRL
37
R2084 Q2002 100K RUM002N02GT2L R2081 S
GND
C2006 10p 50V
+VCCCLK5_R
10K
TBL4301 B1
E42 AM18 AM20
CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 GPP_B10/SRCCLKREQ5#
SSD_PCIECLK_REQ_BUF# C1
SSD_PCIECLK_REQ#
E37 E35
REV = JKS Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001
A2
C2015 33,43
6.3V 0201
D
TP2001SP_TP_SMDP58MM
XTAL_24M_IN XTAL_24M_OUT
10 OF 20 C2016
X948599-001
50V 10p 0201_P33
SUSCLK
U2004 TXS0101YZPR
0.1u 6.3V 0201
24MHz X2002 1 0 3 4 2 GND
C2007
18 18
AN18 AM16
SRTCRST# RTCRST#
+3P3V +1P8V_SSD
CLK_XDP_DN CLK_XDP_DP
BA17
GPD8/SUSCLK
E40 E38 AU7
PCIE_WIFI_RCLK_DN PCIE_WIFI_RCLK_DP
PCIE_WIFI_CLKREQ#
F43 E43
CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P
CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 GPP_B7/SRCCLKREQ2#
B40 A40 AU8
PCIECLK_EXP_DN PCIECLK_EXP_DP
R2083 0201_P28
CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 GPP_B6/SRCCLKREQ1#
D40 C40 AT10
BACK0_SHALL
73 73 50 50
33,50
D42 C42 AR10
BACK1_NHALL
1M
D
32 20
XTAL_24M_OUTR2035 0201_P28
SKL_ULT CLOCK SIGNALS
SRTC_SRST#
D
XTAL_24M_IN
R2087 TBL4301
U2001A SN74LVC2G66YZPR
B2
VCC 1A 1B EN GND
R2004 100K 0201_P28
0201_P33
AK7 AK6 AK9 AK10
MEM_ID1 MEM_ID0 MEM_ID2 MEM_ID3
H5 D7
CAM_IRCAM_XO_EN CAM_IR_PWR_DN#
49
A2
TOP_SWAP
B1 D1
D8 C8 AW5
INT. PD
U2001B SN74LVC2G66YZPR
TOP_SWAP_2A_2EN
D2
ALL R2008 100K 0201_P28
A16 swap override Strap/ Top-Block swap override jumper
2A 2B 2EN
HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD
SDIO/SDXC
GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3 GPP_G5/SD_CD# GPP_G6/SD_CLK GPP_G7/SD_WP
GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD
GPP_A17/SD_PWR_EN#/ISH_GP7 GPP_A16/SD_1P8_SEL
GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0
SD_RCOMP
GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1
GPP_F23
C2011 0.1u 6.3V 0201
+1P8V_SSD2 U2003 TXS0101YZPR C2012 A1
VCCA
VCCB
A2
SSD2
SSD2
10K
0201_P28
SSD2 33,44
C1
SSD2_PCIECLK_REQ#
B1
High=Enabled A16 swap override/ Top-Block swap override
A
B
GND
OE
R2089 0
0201 DNP
6.3V 0201
0.1u R2085
A
SSD2_PCIECLK_REQ_BUF# +1P8V_SSD2
C2 B2
R2091
1K
SSD2
Low=Default
5
4
TP2011 SD_RCOMP
AF13
3
2
20
54 53
SP_TP_SMDP58MM
AB7
+3P3V R2007 49.9K 0201_P28
PCB_ID0 23 PCB_ID1 23 PCB_ID2 23 PCB_ID3 23 PCB_ID4 23 PCB_ID5 23 CAM_LED_F_EN CAM_LED_R_EN
BA9 BB9
GPP_B14/SPKR
C2
Port G 3.3V
AB11 AB13 AB12 W12 W11 W10 W8 W7
7 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001
BGA8_P9X1P9XP5_P5MM
C1
STP_A16OVR:
2p
C2005
BA22 AY22 BB22 BA21 AY21 AW22 J5 AY20 AW20
https://vinafix.com
C2008
2p 23 23 23 23
0.1u 25V 49 0402_P55-S
BGA8_P9X1P9XP5_P5MM
A1
C2010
+3P3VA
R2006 1K 0201_P28 TOP_SWAP_1A
UEFI_TOP_SWAP
HDA_SYNC_R HDA_BCLK_R HDA_SDO_R INT. PD was HDA_SDI0_R
33 33 33
+3P3V
2.HDA_SDOwhich sample high on the rising edge of PWROK Will also disable Intel ME.
37
R2020 R2053 R2054
2p C2009 0201_P33
AZ_SYNC_1 AZ_BITCLK_1 AZ_SDATA_OUT_1 AZ_SDATA_IN0
HDA_SDO: 1.Flash descriptor security: Sampled Low: in effect. Sampled High: override
B
0201_P28 0201_P28 0201_P28
0201_P33
40 40 40 40
SKL_ULT
AUDIO
0201 0
B
MEM_DBG1
23
R2080 200 0201_P26
5
4
2
R2107 1K
R2110 1K
R2104 1K
0201_P28
R2103 1K
0201_P28
R2102 1K
0201_P28
7bit i2c Address 0x4D
U1001E SKL_ULT_1356BGA_R1 PCB Footprint = bga1356_47x30_42x24x1p27mm-SKL
0201_P28
Close to PCH
R2134 1K 0201_P28 DBG_D
0201_P28
R2133 1K 0201_P28 DBG_D
1
+3P3VSB
XDP_SPI0_IO2 SPI0_MOSI_XDP
0201_P28
18 18
3
R2106 1K
TP2130
SP_TP_SMDP58MM
SKL_ULT SPI - FLASH D
21 21 21 21 21 21
15 15 15 15 15 15
R2136 R2135 R2139 R2137 R2138 R2141
SPI_CLK SPI_SO SPI_SI SPI_WP_IO2 SPI_HOLD#_IO3 SPI_CS#0
0201_P26 0201_P26
SPI_CLK_R SPI_SO_R SPI_SI_R SPI_WP_IO2_R SPI_HOLD#_IO3_R SPI_CS#0_R
AV2 AW3 AV3 AW2 AU4 AU3 AU2 AU1
SMBUS, SMLINK
1
SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#
GPP_C3/SML0CLK GPP_C4/SML0DATA GPP_C5/SML0ALERT# GPP_C6/SML1CLK GPP_C7/SML1DATA GPP_B23/SML1ALERT#/PCHHOT#
SPI - TOUCH
30,33,57 30,33,57 30,33 30,33,57
TS_SPI_CLK TS_SPI_MISO TS_SPI_MOSI TS_SPI_CS#
R2109 R2105 R2101
15 15 15
0201_P26 0201_P26 0201_P26
TS_SPI_CLK_R TS_SPI_MISO_R TS_SPI_MOSI_R
R2112
15
0201_P26
TS_SPI_CS_N_R
M2 M3 J4 V1 V2 M1
GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#
GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3 GPP_A5/LFRAME#/ESPI_CS# GPP_A14/SUS_STAT#/ESPI_RESET#
R2158 10K 0201_P28
C LINK
C
AW13
RCIN#
AY11
DNP C2105 100p 0201_P33
+3P3V +3VSUS_ORG R2132 8.2K 0201_P26 38
PCH_SERIRQ
CL_CLK CL_DATA CL_RST#
GPP_A9/CLKOUT_LPC0/ESPI_CLK GPP_A10/CLKOUT_LPC1 GPP_A8/CLKRUN#
GPP_A0/RCIN#
SML0CLK SML0DAT SD_CD#_PCH
INT. PD
W3 V3 AM7 INT. PD
AY13 BA13 BB13 AY12 BA12 BA11
SD_CD#_PCH
R2156 R2153 R2152 R2151 R2157
33 33 33 33 33
LAD0 LAD1 LAD2 LAD3 LFRAME#
TPM_PD#
0201_P28
CK_24M_TPM_R
SPI1_CS#0 SPI1_SO SPI1_WP#
1 2 3 4 9
CS# DO(IO1) WP#(IO2) GND1 GND2
R2129
22
5%
CK_24M_TPM
R2150
49.9K DNP
CS_ENTRY#
24,25,33,37,64
R2122 1K DNP
R2131 8.2K 0201_P26
SPI1_HOLD# SPI1_CLK SPI1_SI
PM_CLKRUN#
MTP2101 MTP2102 MTP2103 MTP2104 MTP2105 MTP2106 SPI1_CLK SPI1_SI SPI1_SO SPI1_WP# SPI1_HOLD# SPI1_CS#0
A
R2127 R2128 R2146 R2130 R2147 R2149
0 0 0 0 0 0
A3 B3 A2 A4 B5 C5 A5
GND N.C. NC1 NC2 NC3 NC4 NC5 NC6
NO1 NO2 NO3 NO4 NO5 NO6
+3VSUS_ORG
21
SML1CLK
DBG_D
DBG_D
DBG_D
SPI1_WP#_DBG SPI1_HOLD#_DBG
R2125 100K 0201
IN1/IN2 = L => COM to NC => NC to COM
DNP IN1/IN2 = H R2126 100K
R2108 10K 0201_P28 DNP
Q2102 RUM002N02GT2L SOTFL-3_1P3XP9XP55_P4
MTP2107 21
SML1DATA
S
D
SAM_SEN_SDA
31,33,35,37,39,74
DNP
DBG_D SPI1_EXT 33,37 SPI1_CLK_DBG 33,71 SPI1_SI_DBG 33,71 SPI1_SO_DBG 33,71 SPI1_CS#_DBG
GPP_C2/SMBALERT#
33,71
SPI_CLK 21 SPI_SI 21 SPI_SO 21 SPI_WP_IO2 21 SPI_HOLD#_IO3 21 SPI_CS#0 21
3
31,33,35,37,39,74
SOTFL-3_1P3XP9XP55_P4
DNP
G
R2124 1K
6.3V
DBG_N DBG_N DBG_N DBG_N DBG_N DBG_N
4
D SAM_SEN_SCL Q2101 RUM002N02GT2L G
C2110 0.1u
R2148 1K
Populate for production only
5
S
+3VSUS_ORG
C3 E2 E3 E4 D5 D4 E5
38
+5VSB
+3VSUS_ORG DBG_D U2103 TS3A27518EZQSR SPI_CLK = 20/33/50Mhz BGA24_5X5_3X3X1_P5MM SPI1_CLK A1 C2 V+ SPI1_SI B1 COM1 SPI1_SO C1 COM2 C4 COM3 EN# SPI1_WP# D1 SPI1_HOLD# E1 COM4 B4 IN1 D3 SPI1_CS#0 D2 COM5 COM6 IN2
SPI_CLK SPI_SI SPI_SO SPI_WP_IO2 SPI_HOLD#_IO3 SPI_CS#0
C
0201_P33 50V
UEFI SPI ROM B
38
DNP C2103 10p
https://vinafix.com VCC HOLD#(IO3) CLK DI(IO0)
SP_TP_SMDP58MM
+3P3V
0201 6.3V
8 7 6 5
38
38
C2111 0.1u
U2102 W25Q128FVPIQ SON9_5X6XP8_1P27MM
48
+3P3VSB
38 38 38 38
TP2128
AW9 AY9 AW11
D
18
SML1CLK 21 SML1DATA 21
SMB1ALERT#
LAD0_R LAD1_R LAD2_R LAD3_R LFRAME#_R
5 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 +3VSUS_ORG BUILD-OPT = TBL1001
R2120 1K DNP
ALL
Serial Interrupt Request
R9 W2 W1
18
SMBDATA
GPP_A6/SERIRQ
(128Mb=16MB @104MHz) R2121 1K
SMBCLK
R7 R8 R10 INT. PD
R2140 150K 0201_P26 LPC
+3P3V G3 G2 G1
GPP_C0/SMBCLK GPP_C1/SMBDATA GPP_C2/SMBALERT#
2
0 Default
Disable ME crypto TLS
1
Enable ME crypto TLS
B
5
4
3
2
1
+3P3V
C2202 6.3V 0.1u 0201_P33
U2202 74AUP1G08FS3-7
D
GND
R2224 49.9K 0201_P28
C2204 100p 25V
R2223
C2203 470p 25V 0201_P33
0201_P33
Note: Place C2204 next to U2202.2 0201_P28
U1001K SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
AN10 B5 AY17
0 PM_RSMRST_R
75
VCCST_PW RGD
SP_TP_SMDP58MM TP2211 R2257 60.4
SYS_PW ROK_R
ALL R2231 0201_P28
RSMRST#
AR13 AP11
C
PCH_DPW ROK_R
SYS_PW ROK
R2228 0201_P28
BB15 AM15 AW17 AT15
W AKE# 49.9 SP_TP_SMDP58MM
37
B6 BA20 BB20
PCH_DPW ROK_R
PCH_SYS_RST#
PCH_SYS_RST#
18,33,37
VCCST_PWRGD_R
DNP R2239 0 0201_P28
TP2216
LANPHYPC
R2251 49.9K 0201_P28
LAN_WAKE#
18
A68 B65
PROCPW RGD
0402_P4-S
R2225 10K 0201_P28
+3P3VSB
100 R2252 0201_P28
100K
TP2208 SP_TP_SMDP58MM TP2202 SP_TP_SMDP58MM
SYSTEM POWER MANAGEMENT SKL_ULT
DNP
+3P3V
TP2220 SP_TP_SMDP58MM TP2221 SP_TP_SMDP58MM
GPP_B12/SLP_S0# GPD4/SLP_S3# GPD5/SLP_S4# GPD10/SLP_S5#
GPP_B13/PLTRST# SYS_RESET# RSMRST#
SLP_SUS# SLP_LAN# GPD9/SLP_WLAN# GPD6/SLP_A#
PROCPWRGD VCCST_PWRGD SYS_PWROK PCH_PWROK DSW_PWROK
GPD3/PWRBTN# GPD1/ACPRESENT GPD0/BATLOW#
GPP_A13/SUSWARN#/SUSPWRDNACK GPP_A15/SUSACK# GPP_A11/PME# INTRUDER#
WAKE# GPD2/LAN_WAKE# GPD11/LANPHYPC GPD7/RSVD
GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT#
11 OF 20
SLP_S0# SLP_S3# SLP_S4# SLP_S5#
AN15 AW15 BB17 AN16
SLP_SUS# SLP_LAN# SLP_W LAN# SLP_A#
SLP_S0# SLP_S3# SLP_S4# TP2217 SP_TP_SMDP58MM
28,33,37,56,60,61 22,37,56,75 33,37,60
BA15 AY15 AU13
SLP_SUS# 33,37 TP2219SP_TP_SMDP58MM TP2203SP_TP_SMDP58MM TP2218SP_TP_SMDP58MM XDP_PCH_PW RBTN# R2232 0 SB_PW RBTN# 10,37 AC_PRESENT_R 0201_P28 BATLOW #_R
AU11 AP16
PME# INTRUDER#
AM10 AM11
VRALERT#_R
SP_TP_SMDP58MM TP2209 R2256 1M 0201_P28
+3P3VSB
REV = JKS Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001
18
+VCC_RTC
R2220 10K 0201_P28
C
R2258 10K 0201_P28 for VR hot indicator (may not be used)
R2259 20K 0201_P28
PM_PCH_PW ROK_R
AT11 AP15 BA16 AY16
+3P3VSB
2 1
10K 0201_P28
3
A B
R2226
VCC Y
+3P3VSB
PLT_RST_BUF#
DFN5_P85XP85XP4_P48
10K 0201_P28 DNP
18,33,37,38,43,44,73,75
5 4
R2254
D
https://vinafix.com
DV 11_30
+3P3VSB 37
PCH_DPW ROK
R2235 0201_P28 R2253 0201_P28
0
PCH_DPW ROK_R 0201
100K
C2205 0.1u 6.3V
+3P3VSB B
22,37,56,75
SLP_S3#
ALL R2260
0
U2203
0201_P28
2 1
DNP R2203 10K 0201_P28 SUSW ARN#
If SUSWARN #/SUS_ACK # handshake is not used, these signals are tied on the board ALL R2241 49.9 SUSACK# 0201_P28
A B
GND
R2261 37
PM_PCH_PW ROK
VCC Y
0
5 4
PM_PCH_PW ROK_R B
3
SN74AUP1G08DPWR
0201_P28
ALL
+3P3VSB
0201_P28 DNP R2255 100K
R2212 10K 0201_P28
DNP R2229
0 0201_P28
A
A
5
4
3
2
5
4
3
2
TBL2301
1
TBL2302 Reference Info Only. For Build Options used for LPDDR3, see TBL1601 on Sheet 16.
D
D
C
C
+1P8VSB
U1001I SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
49 49
54 54 54 54
CSI2_F4_DN CSI2_F4_DP CSI2_F5_DN CSI2_F5_DP
A36 B36 C38 D38 C36 D36 A38 B38 C31 D31 C33 D33 A31 B31 A33 B33
CSI2_IRCAM8_DN CSI2_IRCAM8_DP
A29 B29 C28 D28 A27 B27 C27 D27
SKL_ULT
CSI2_DN0 CSI2_DP0 CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3
CSI2_CLKN0 CSI2_CLKP0 CSI2_CLKN1 CSI2_CLKP1 CSI2_CLKN2 CSI2_CLKP2 CSI2_CLKN3 CSI2_CLKP3
CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7
CSI2_COMP GPP_D4/FLASHTRIG
CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11
E13 B7
20 20 20 20 25
53 53 54 54
MEM_ID0 MEM_ID1 MEM_ID2 MEM_ID3 MEM_ID4 +1P8VSB
0201_P28 R2322 100 PCH_W AKE_R R2331
GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7 GPP_F21/EMMC_RCLK GPP_F22/EMMC_CLK GPP_F12/EMMC_CMD EMMC_RCOMP
AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1 AM2 AM3 AP4 AT1
MEM_ID3
CAM_F_PWR_DN#_R R2326
EMMC_RCOMP_R
TBL1601 R2312 10K 0201_P28
4
3
2
1
0
+3P3VSB
+3P3VSB
+3P3VSB
+3P3VSB
+3P3VSB
Port G 3.3V
CAM_R_PW R_DN# 53
20 20 20
25,53 25,54 23 CAM_F_PW R_DN# 54 +1P8VSB +1P8VSB DNP R2330 10K
DNP R2323 10K 0201_P28
20 20 20
PCB_ID4
PCB_ID4 PCB_ID0 PCB_ID1
TBL3801 R2303 10K 0201_P28
TBL2301 R2307 10K 0201_P28
TBL2301 R2305 10K 0201_P28
TBL2301 R2306 10K 0201_P28
TPM
TBL2301 R2304 10K 0201_P28
PCB_ID0 PCB_ID1 PCB_ID2
PCB_ID2 PCB_ID3 PCB_ID5
PCB_ID3
RFU ALL R2324 10K 0201_P28
DNP R2327
TBL3801 R2301 10K 0201_P28
TBL2301 R2310 10K 0201_P28
TBL2301 R2309 10K 0201_P28
TBL2301 R2308 10K 0201_P28
TBL2301 R2302 10K 0201_P28
10K
0201_P28
0201_P28
ALL R2328 10K
23 20
ALL R2329 A
10K
Vinafix.com 4
TBL1601 R2314 10K 0201_P28
B
MEM_DBG0 MEM_DBG1
5
TBL1601 R2313 10K 0201_P28
5
0201_P28
330MEM_DBG0 0201_P28
TBL1601 R2316 10K 0201_P28
+3P3VSB
330 CAM_R_XO_EN CAM_F_XO_EN
MEM_ID4
TBL1601 R2317 10K 0201_P28
PE_W AKE# 73
R2325
R2311 200 0201_P26 1%
A
MEM_ID2
DNP
0201_P28
TBL1601 R2321 10K 0201_P28
R2332 49.9K
CAM_R_PWR_DN#_R
+1P8VSB
TBL1601 R2319 10K 0201_P28
MEM_ID1
0201_P28
0
0201_P28
+1P8VSB
TBL1601 R2320 10K 0201_P28
MEM_ID0
ALL R2333 20K
CSI2_COMP
+1P8VSB
TBL1601 R2315 10K 0201_P28
https://vinafix.com 49 49
TP2301SP_TP_SMDP58MM
EMMC
9 OF 20 REV = 1 BUILD-OPT = TBL1001 Source Package = SKL_ULT_1356BGA_R1
CSI2_R0_CLK_DN CSI2_R0_CLK_DP CSI2_F1_CLK_DN CSI2_F1_CLK_DP CSI2_CLK2_IRCAM_DN CSI2_CLK2_IRCAM_DP
C37 D37 C32 D32 C29 D29 B26 A26
0201_P28
B
CSI2_R0_DN CSI2_R0_DP CSI2_R1_DN CSI2_R1_DP CSI2_R2_DN CSI2_R2_DP CSI2_R3_DN CSI2_R3_DP
0201_P28
CSI-2
53 53 53 53 53 53 53 53
+1P8VSB
TBL1601 R2318 10K 0201_P28
3
2
5
4
3
2
1
U1001H SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL D
D SKL_ULT SSIC / USB3
PCIE/USB3/SATA
PCIE BGA EXPANSION
73 73 73 73
PCIE_EXP_RX0_DN PCIE_EXP_RX0_DP PCIE_EXP_TX0_DN PCIE_EXP_TX0_DP
73 73 73 73
PCIE_EXP_RX1_DN PCIE_EXP_RX1_DP PCIE_EXP_TX1_DN PCIE_EXP_TX1_DP
H13 G13 B17 A17
ALL
C24010.22u C24020.22u
6.3V0201ALL 6.3V0201
G11 F11 D16 C16
ALL
C24030.22u C24040.22u
6.3V0201ALL 6.3V0201
PCIE WIFI C
PCIE BGA SSD2
PCIE_WIFI_RX_DN PCIE_WIFI_RX_DP PCIE_WIFI_TX_DN PCIE_WIFI_TX_DP
44 44 44 44
PCIE_SSD2_RX0_DN PCIE_SSD2_RX0_DP PCIE_SSD2_TX0_DN PCIE_SSD2_TX0_DP
44 44 44 44
PCIE_SSD2_RX1_DN PCIE_SSD2_RX1_DP PCIE_SSD2_TX1_DN PCIE_SSD2_TX1_DP
ALL ALL
C2405
0.1u
C2406
0.1u 6.3V
G15 F15 B19 A19
C2409 C2410
0.22u
6.3V0201
SSD2
0.22u
6.3V0201
SSD2
0.22u
6.3V0201
SSD2
0.22u
6.3V0201
SSD2
43 43 43 43
ALL
B
0201_P28
+3VSUS_ORG
43 43 43 43
R2421 10K
PCIE_SSD_RX0_DN PCIE_SSD_RX0_DP PCIE_SSD_TX0_DN PCIE_SSD_TX0_DP
F16 E16 C19 D19
PCIE_SSD_RX1_DN PCIE_SSD_RX1_DP PCIE_SSD_TX1_DN PCIE_SSD_TX1_DP
ALL
XDP_PRDY# XDP_PREQ#
SP_TP_SMDP58MM TP2418 SP_TP_SMDP58MM
TP2417 TP2419 SP_TP_SMDP58MM
6.3V0201
ALL
C24130.22u C24140.22u
R2401 100 0201_P28 18 18
6.3V0201ALL
6.3V0201ALL 6.3V0201
PCIE_RCOMPN PCIE_RCOMPP
PIRQA#
USB2N_1 USB2P_1
PCIE5_RXN PCIE5_RXP PCIE5_TXN PCIE5_TXP
G18 F18 D20 C20
USB2N_2 USB2P_2 USB2N_3 USB2P_3
PCIE6_RXN PCIE6_RXP PCIE6_TXN PCIE6_TXP
USB2N_4 USB2P_4
PCIE7_RXN/SATA0_RXN PCIE7_RXP/SATA0_RXP PCIE7_TXN/SATA0_TXN PCIE7_TXP/SATA0_TXP
G21 F21 D21 C21
C24110.22u C24120.22u
USB3_4_RXN USB3_4_RXP USB3_4_TXN USB3_4_TXP
PCIE4_RXN PCIE4_RXP PCIE4_TXN PCIE4_TXP
F20 E20 B21 A21
PCIE BGA SSD1
USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP
PCIE3_RXN PCIE3_RXP PCIE3_TXN PCIE3_TXP
6.3V
C2407 C2408
USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP
PCIE2_RXN/USB3_6_RXN PCIE2_RXP/USB3_6_RXP PCIE2_TXN/USB3_6_TXN PCIE2_TXP/USB3_6_TXP
H16 G16 D17 C17 50 50 50 50
USB3_1_RXN USB3_1_RXP USB3_1_TXN USB3_1_TXP
PCIE1_RXN/USB3_5_RXN PCIE1_RXP/USB3_5_RXP PCIE1_TXN/USB3_5_TXN PCIE1_TXP/USB3_5_TXP
PCIE8_RXN/SATA1A_RXN PCIE8_RXP/SATA1A_RXP PCIE8_TXN/SATA1A_TXN PCIE8_TXP/SATA1A_TXP
E22 E23 B23 A23
PCIE9_RXN PCIE9_RXP PCIE9_TXN PCIE9_TXP
F25 E25 D23 C23
USB2N_6 USB2P_6
USB2N_8 USB2P_8 USB2N_9 USB2P_9
USB2N_10 USB2P_10 USB2_COMP USB2_ID USB2_VBUSSENSE
PCIE_RCOMPN PCIE_RCOMPP
D56 D61 BB11
GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#
PROC_PRDY# PROC_PREQ# GPP_A7/PIRQA#
E28 E27 D24 C24 E30 F30 A25 B25
J6 H6 B13 A13
PCIE11_RXN/SATA1B_RXN PCIE11_RXP/SATA1B_RXP PCIE11_TXN/SATA1B_TXN PCIE11_TXP/SATA1B_TXP PCIE12_RXN/SATA2_RXN PCIE12_RXP/SATA2_RXP PCIE12_TXN/SATA2_TXN PCIE12_TXP/SATA2_TXP
GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2 GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_E8/SATALED#
45 45 45 45
USB3_CONN_RX_DN USB3_CONN_RX_DP USB3_CONN_TX_DN USB3_CONN_TX_DP
C2415
0.1u
C2416
0.1u 6.3V 6.3V
J10 H10 B15 A15 E10 F10 C15 D15
73 73 73 73
EXPANSION DEBUG
USB3_SL1_RX_DN USB3_SL1_RX_DP USB3_SL1_TX_DN USB3_SL1_TX_DP
71 71 71 71
USB3 SL1
USB3_SDXC_RX_DN USB3_SDXC_RX_DP USB3_SDXC_TX_DN USB3_SDXC_TX_DP
AB9 AB10
USB Type A
USB3_EXP_RX_DN USB3_EXP_RX_DP USB3_EXP_TX_DN USB3_EXP_TX_DP
USB2_CONN_DN USB2_CONN_DP
48 48 48 48 45 45
USB3.0 SDXC USB Type A C
AD6 AD7 AH3 AJ3
USB2_EXP_DN USB2_EXP_DP
73 73
USB EXPANSION DEBUG
USB2_SL1_DN USB2_SL1_DP
71 71
USB SL2
AD9 AD10 AJ1 AJ2
USB2_BT_DN USB2_BT_DP
50 50
BT
AF6 AF7
https://vinafix.com USB2N_7 USB2P_7
PCIE10_RXN PCIE10_RXP PCIE10_TXN PCIE10_TXP
F5 E5
USB2N_5 USB2P_5
USB2
H8 G8 C13 D13
AH1 AH2
USB2_BLADE_DN USB2_BLADE_DP
74 74
USB2 BLADE
AF8 AF9
+3VSUS_ORG
AG1 AG2
TP2424 TP2422SP_TP_SMDP58MM TP2423SP_TP_SMDP58MM TP2425SP_TP_SMDP58MM
AH7 AH8 AB6 AG3 AG4
SP_TP_SMDP58MM
USB2_COMP
R2402 113 0201_P28
R2419
10K
A9 C9 D9 B9 J1 J2 J3
PCIE_WIFI_DISABLE# PCIE_WIFI_PERST# WLAN_PWD#
H2 H3 G4
TCON_VENDOR_ID TS_BRD_REV[1] TS_BRD_REV[0]
H1
GPP_E8
45
0201_P28
GND USB_CONN_OC# WWAN_PWREN CS_ENTRY# 5V_USB_EN_R
B
USB_CONN_OC#
ALL
TP2420 SP_TP_SMDP58MM R2403
1K
WWAN_PWREN 25,65 CS_ENTRY# 21,25,33,37,64 MTP2421 SP_TP_SMDP58MM 5V_USB_EN 45 PCIE_WIFI_DISABLE# 50 PCIE_WIFI_PERST# 50 WLAN_PWD# 33,50 TCON_VENDOR_ID TS_BRD_REV[1] TS_BRD_REV[0] GPP_E8
25,57 25,30 25,30
33
8 OF 20 REV = JKS Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001
R2417 49.9K 0201_P28
W x H 412 x 267 mm
A
5
4
3
2
A
5
4
3
2
1
+3VSUS_ORG
TP2518SP_TP_SMDP58MM MTP2535 SKL_ULT
SKL_NO_REBOOT
DNP
R2543
PCH_SAM_INT
INT. PD
AN8 AP7 AP8 AR7
INT. PD
AM5 AN7 AP5 AN5
R2579
0 0
0201_P28 0201_P28
R2520 R2521
0 0
0201_P28 0201_P28
GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL GPP_D15/ISH_UART0_RTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
2K 0201_P28
R2580
DNP
DNP
2K
0201_P28
0.1u
C2502
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5 GPP_A12/BM_BUSY#/ISH_GP6
GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL
0201_P28
RTD3_TPANEL_PWR 0201_P28 R2515 EDP_I2C_INT
N1 N2
PCH_ISH_I2C1_SDA R2510 PCH_ISH_I2C1_SCL R2519
MTP2530 SP_TP_SMDP58MM
MEM_ID4
AC1 AC2 AC3 AB4
R2513 R2505
AY8 AGYRO_INT1#_R R2512 GPP_A19 BA8 GPP_A20 BB7 BA7 AY7 GPP_A22 TP2514 AW7 GPP_A23 TP2521 AP13 GPP_A12 TP2519
U2502
R2596 10K 0201_P28 DNP
R2558 2KDBG_D
TPANEL_RST#
R2578 49.9K 0201_P28 ALL
DBG_D
DBG_D GND 25,52
B2
VCC
SCL
VSS
SDA
A2
I2C4_SCL
25,30
LID_CLOSED
B1
I2C4_SDA
R2502 49.9K CAM_R_XO_EN 23,53 0201_P28 ALL R2503 49.9K CAM_F_XO_EN 0201_P28 ALL
M24C64S-FCU BGA4_P853XP853XP3_P5XP4 GND SP_TP_SMDP58MM TP2531 SP_TP_SMDP58MM TP2530
SP_TP_SMDP58MM
R2514 49.9K 0201_P28 ALL
A
R2501 10K 0201_P28
DBG_D R2525 1K 0201_p28
AGYRO_INT1#
32
R2561 R2562 R2563
LED_ISH_DBG_A
K DBG_D LED_0402_P55 LED2501
A
Red
R2599 0 ISH_DBG 0201_P28 DBG_D B
+1P8VSUS_ORG Because this is an i2c pullup... it should run on same rail as the master. Changed values of R2555 & R2256 from 4.7K to 2K to bring i2c rise time into spec when operating on 1.8v rail.
10,37
R2556 2K
R2555 2K 0201_P28
Level Shifter Removed SEN_SDA
23,54
PCIE_SSD_PERST#
49.9K 49.9K 49.9K
TCON_VENDOR_ID TS_BRD_REV[0] TS_BRD_REV[1]
SEN_SCL
32,33,37
MTP2539
10,43,44,73
24,57 24,30 24,30
3
32,33,37
MTP2540
+3P3VSB
4
C
+3VSUS_ORG
Remove redundant MTP's?
R2592 49.9K 0201_P28 ALL
0201_P28 0201_P28 0201_P28
TP2527SP_TP_SMDP58MM +3VSUS_ORG
TP2534 TP2532
-4mA sync capability on 3.3V GPIO
W x H 417 x 270mm
25,33,37 0.1u
RTD3_CAM_PWREN
TP2501
0
SP_TP_SMDP58MM
https://vinafix.com 0201_P28
0201_P28
C2501
R2530 49.9K 0201_P28
PCH_UART1_RXD 33,71 PCH_UART1_TXD 33,71 SAM_PCH_INT 25,33,37 PCIE_WIFI_WAKE# 33,50
PCIE_WIFI_WAKE#
0201_P28
A1 SAM_PCH_INT
0 0
RED
+1P8VSUS_ORG
5
MTP2501 SP_TP_SMDP58MM
U1 U2 U3 U4
R2539 49.9K CS_ENTRY# 21,24,33,37,64 0201_P28 DNP R2572 49.9K WWAN_PWREN 24,65 0201_P28 ALL R2595 49.9K RTD3_AUD_PWR 10,62,64 0201_P28 ALL R2559 49.9K RTD3_TPANEL_PWR 25,62,64 0201_P28 ALL
+1P8VSUS_ORG
R2554 DBG_D 2K
33,57 MTP2538
+3VSUS_ORG
SP_TP_SMDP58MM
B
+3VSUS_ORG
EDP_I2C_INT
Net labels corrected.
23
REV = JKS Source Package = SKL_ULT_1356BGA_R1 BUILD-OPT = TBL1001
+1P8V_CAM_F
10K
SEN_SDA SEN_SCL
0 0
SP_TP_SMDP58MM
MTP2537 MTP2536
DNP 0201_P28
0201_P28 0201_P28
AD11 AD12
D
TPANEL_RST# 25,30 RTD3_TPANEL_PWR 25,62,64 25,52 RTD3_CAM_PWREN FLASH_PROTECT# 30
1K
6 OF 20
+1P8V_CAM_R
R2591
0
0
M4 N3
0201_P28
R2504
SP_TP_SMDP58MM
GPP_F10/I2C5_SDA/ISH_I2C2_SDA GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL
AH11 AH12 AF11 AF12
0201_P28
R2527 R2528
I2C_SDA_REAR_IR_CAM I2C_SCL_REAR_IR_CAM I2C4_SDA I2C4_SCL
I2C PU can be placed anywhere along the net SP_TP_SMDP58MM
GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#
GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL
AH9 AH10
4.99K
0 0
I2C_SDA_IRCAM I2C_SCL_IRCAM
I2C_SDA_FCAM_R I2C_SCL_FCAM_R
4.99K
49 49
R2522 R2523
0201_P28
I2C_SDA_RCAM I2C_SCL_RCAM
U7 U6 U8 U9
R2508
53 53
GND
4.99K
I2C_SDA_FCAM I2C_SCL_FCAM
TXS0102YZPR 0 0201_P28 0 0201_P28
DNP
PMI_I2C_SDA PMI_I2C_SCL
PMI_I2C_SDA PMI_I2C_SCL
54 54
B2 A2 A1 B1
0201_P28
28 28
R2597 R2598
VCCB B1 B2 GND
R2581
ALL ALL
C
GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL
0201_P28 R2511 0201_P28 R2517
TPANEL_RST#_R
R2589
R2584
MTP2534 MTP2531 MTP2533 MTP2532
VCCA A1 A2 OE
R2507
SP_TP_SMDP58MM
AD1 AD2 AD3 AD4
U2503 C1 D2 D1 C2
DNP
R2506
SP_TP_SMDP58MM
GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL
P2 P3 P4 P1
0201_P28
10K
4.99K
SP_TP_SMDP58MM
AB1 AB2 W4 AB3
33,37 SAM_PCH_TX 33,37 SAM_PCH_RX 31,33,35 VOL_UP# 31,33 VOL_DOWN#
0201_P28
SP_TP_SMDP58MM
2K
2K R2582 GND 0201_P28
+3P3VSB
DV 11_18
GPP_D9 GPP_D10 GPP_D11 GPP_D12
GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI
SP_TP_SMDP58MM
0 DNP
0201_P28
0201_P28
PANEL_I2C_SCL PANEL_I2C_SDA
R2583
33,57 33,57
GPP_B22
TP2529
GND
GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI
1K
+1P8V_PANEL 499K R2588
ISH
100K
DUAL_SSD_DET# BACK1_SHALL EXPCON_DET#
43 32 73 +3P3V 33,37
DUAL_SSD_DET#
R2590
LPSS D
100K
100K
U1001F SKL_ULT_1356BGA_R1 bga1356_47x30_42x24x1p27mm-SKL
R2509
100K
TP2523SP_TP_SMDP58MM
R2524
No reboot strap SP_TP_SMDP58MM Low: Disable (Default) High:Enable TP2525
2
A
5
4
3
2
1
+1VSB
+3VSUS_ORG D1 D S=1 => D2 D
GND TS3A5223
DBG_D DBG_D
24
USB3_SL1_RX_DP
24
USB3_SL1_RX_DN
4 M71L2
1
USB3_SL1RX_DP
3
2
USB3_SL1RX_DN
1
USB3_SL1TX_DP
2
USB3_SL1TX_DN
PWR_SL1
24
USB3_SL1_TX_DP
24
USB3_SL1_TX_DN
C7102 0.1u
USB3_SL1_TX_C_DP
4
USB3_SL1_TX_C_DN
3
M71L1
6.3V
C7101 0.1u
70
SL1_HPD1A
6.3V
USB3_SL1_RX
4
0 0 M71L6
SL1 Lane2 Pair
https://vinafix.com
SL1_LANE0_DP
MTP_BF7104 B
MTP_BF7102 +5V +3P3VA
GND
21,33 21,33
499K R7115
6.3V DBG_D
DBG_D
SWD_CLK SWD_DIO
+3P3VA
7 10 8 +3P3VA 1
1M
UEFI_SEL_OUT
R7106 499K
2 1
35,37,71 SAM_DBG_MODE SL1_DBG_SWD_UEFI_SEL
A B DBG_D
R7119 499K DNP
VCC Y GND
R7118
U7121
37
5 4 3
6.3V DBG_D
6
S1A S1B SEL1 S2A S2B SEL2 VCC GND
3
OUT1
9
OUT2
C7130 0.1u
6
6.3V DBG_D
S2A S2B SEL2 VCC GND
3
OUT1
R7107
0
DBG_N
R7108
0
DBG_N
S=0 => D1 D S=1 => D2 D U7102 TS3USB30E
MTP_BF7101
DBG_D
TS3A5223
C7132 0.1u
DBG_D
1 2
USB2_SL1_DN PCH_UART1_RXD
25,33 37
7 6
USB2_SL1_DP PCH_UART1_TXD
10 8
PCH_DBG_EN
D1+ D2+
VCC
U7101
D+
D1D2-
D-
S OE
GND
9 3
USB2_SL1_DN/PCH_UART_RXD USB2_SL1_DP_R/PCH_UART_TXD
B
GND C1 ID C2 DM_I B2 DP_I A2
USB2_SL1_DN/PCH_UART_RXD_R USB2_SL1_DP_R/PCH_UART_TXD_R
bga6_2x3ns_p95x1p34xp6_p4mm
5 4
DM_O B1 A1 DP_O
A
C7114 0.1u 6.3V DBG_D
R7114 0 DBG_D
20160422sjs0730 -Power button press for 20 seconds will enable SAM to force in debug mode for flashing the FW. With the addition of the FETand the OR gate, this will ensure MUX is forced into this mode irrespective of SAM state for FW programming through SL. 4
62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
+3P3VSB
qfn10_1p8x1p4xp55_p4mm
MTP_BF7103
24
Out1 = S1A Out1 = S1B Out2 = S2A Out2 = S2B
8 7 6 5 9
MTG22 MTG21 MTG20 MTG19 MTG18 MTG17 MTG16 MTG15 MTG14 MTG13 MTG12 MTG11 MTG10 MTG9 MTG8 MTG7 MTG6 MTG5 MTG4 MTG3 MTG2 MTG1
dfn9_1p7x1p35xp55_p4mm
25,33
DBG_D
O1 O2 O3 O4 GND
SL1_HPD1B
C
9
OUT2
24
TS3A5223
SEL1 = 0 SEL1 = 1 SEL2 = 0 SEL2 = 0
S1A S1B SEL1
SL1_CFG1_CON/SPI1_SO_DBG/SWD_DIO
U7109 12p I1 I O I2 I3 I4 GND PAD
74AUP1G32GX 6.3V DBG_D
5
C7113 0.1u DNP
DBG_D
7 10 8 1
U7111 5 2 4
1M
C7133 0.1u SPI1_CS#_DBG SPI1_SO_DBG
33,36 33,36
A
SPI1_CS#_DBG/SWD_CLK SPI1_SO_DBG/SWD_DIO
1M
3
GND
74AUP1G32GX
DNP
+3P3VA
DNP
A B DBG_D
R7121 499K
5 2 4 +3P3VA
5 4
R7113
SAM_DBG_MODE SL1_DBG_EN
GND
1 2 3 4
DBG_N DBG_N
U7108
SL1_CONFIG1r
R7120 DBG_N 0 +3P3VA RUM002N02GT2L
35,37,71 37,71
GND
SL1_DP_HPD_CON/SPI1_CS#_DBG/SWD_CLK
QFN10_1P4X1P8XP55_P4MM
0
U7122 VCC Y
0 0
+3P3VA
R7117
R7104
SL1_CONFIG1
2 1
R7122 R7123
SL1_DP_HPDr
D SOTFL-3_1P3XP9XP55_P4
QFN10_1P4X1P8XP55_P4MM
46
GND
SAM_DBG_RX SAM_DBG_TX
S
SL1_DP_HPD
GND
R7112 499K
G
Q7102 10
GND
SL1 Lane0 Pair 70 SL1_CFG1_CON/SPI1_SO_DBG/SWD_DIO_CON
2 DNP
R7103 100K
SMB_SDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
SAM_DBG_TX_CON
SL1_LANE0_DN
SL1_DP_HPD_CON/SPI1_CS#_DBG/SWD_CLK_CON
3
1
SAM_DBG_RX_CON
3 RES_4_1P1X1P1XP45 4RES_4_1P1X1P1XP45
DIO_SON2_P66XP36XP32 A2 A1 D7112 TPD1E01B04
SAM_DBG_RX SAM_DBG_TX
0 0 M71L8
SPI_SI_DBG
SL1 Lane1 Pair
DIO_SON2_P66XP36XP32 A2 A1 D7111 TPD1E01B04
33,37 33,37
SL1_LANE1_DP
DIO_SON2_P66XP36XP32 A2 A1 D7110 TPD1E01B04
DDI2_DATA0_DP
SL1_LANE1_DN
2
DIO_SON2_P66XP36XP32 A2 A1 D7109 TPD1E01B04
10
PCH_UART_RXD
SL1_HPD2 SL1_HPD2
RES_4_1P1X1P1XP45
1
DIO_SON2_P66XP36XP32 A2 A1 D7108 TPD1E01B04
DDI2_DATA0_DN
PCH_UART_TXD
SL1_AUX_DN SPI_CLK_DBG SMB_SCL SAM DBG TX SL1_CFG1_CON SPI1_SO_DBG SWD_DIO_CON
RES_4_1P1X1P1XP45
DNP
4
SWD_CLK
USB2_SL1_DN
SL1_AUX_DP
3 4
3 RN7104B 2 RN7104A 1
SPI1_CS#_DBG
SAM DBG RX USB2_SL1_DP
SL1_LANE2_DP
2
0 0 4 M71L7
DDI2_DATA1_DP
10
70,71 70,71
SL1_LANE2_DN
1
DNP
DDI2_DATA1_DN
10
SL1_DP_HPD
3 RES_4_1P1X1P1XP45 4RES_4_1P1X1P1XP45
3
RN7103B 2 RN7103A 1 10
SL1 Lane3 Pair
DIO_SON2_P66XP36XP32 A2 A1 D7107 TPD1E01B04
DDI2_DATA2_DP
SL1_LANE3_DN
DIO_SON2_P66XP36XP32 A2 A1 D7106 TPD1E01B04
10
SL1_LANE3_DP
2
DIO_SON2_P66XP36XP32 A2 A1 D7105 TPD1E01B04
DDI2_DATA2_DN
1
DNP RN7102B 2 RN7102A 1
10
RES_4_1P1X1P1XP45
3
DIO_SON2_P66XP36XP32 A2 A1 D7104 TPD1E01B04
DDI2_DATA3_DN
DIO_SON2_P66XP36XP32 A2 A1 D7103 TPD1E01B04
DDI2_DATA3_DP
10
DIO_SON2_P66XP36XP32 A2 A1 D7102 TPD1E01B04
10
USB3_SL1_TX PAIR
4 3RES_4_1P1X1P1XP45
DIO_SON2_P66XP36XP32 A2 A1 D7101 TPD1E01B04
C
1 0 RN7101A 2 0 RN7101B M71L5 4
J7101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
2
5
4
3
+3P3VAS
R7201 499K 0201_P3 ALL
U7201 +3P3V_HPD_VIN A1 B1 C7209 10u 6.3V 0402_P7-W
C3 +3P3V_HPD_ILIMITC2
+3P3V_HDP_EN
DNP
MTP_BF7200
VIN_A1 VOUT_A3 VIN_B1 VOUT_B3 ON
OCFLAGB
GND
GND_A2 GND_B2
ISET
A3 B3 C7202 10u 6.3V 0402_P7-W
A2 B2
C7203 10u 6.3V 0402_P7-W
R7205 499K 0201_P3 D
FPF2495UCX G
SL1_HPD2_EN#
37
MTP7283 SP_TP_SMDp58mm
C1
D
D
1
+3P3V_HPD
0
R7203
MTTP_BF7200
2
EV2.5 26 Oct 2016 Changed DBG to DBG_R +3P3VAS DBG_R R7202 0.01 0402_p55-w
S
R7206 499K 0201_P3
GND R7204 20K
Q7201 RUM002N02GT2L SOTFL-3_1P3XP9XP55_P4 ALL
GND
GND GND
+3P3V_HPD OCP Imin=42 mA Inom=50 mA Imax=58 mA
GND GND
GND
+VCC_EDP_BKLT_IN_REG
+VSYS
Replace with ZRB18AR61E106ME01-01 if audible noise is encountered.
28
SP-tp-c0p381 SP-tp-c0p381 PMTP7221 PMTP7222 DV 6 Dec 2017
Q7203
Novatek 15dec14: Ipeak(Vin=6V) = 1.144A
+VCC_EDP_BKLT_IN EffCap ([email protected]) = 1.4uF Novatek: Cin = 4.7uF
SOT23_2P9X1P3X1P12_P95MM
C
S
G
C7212 1000p 25V 0201_P33
1
R7213 100K 0201_P28
3
BKLT_EDP_IN_DRI
L7204
Changed 0402 DBG to 0603 DBG_R C7213 R7210 0.1u 16V 4.99K 0201_p28mm GND
R7211 4.99K 0201_p28mm R7207
0201_p3
SOT363_6_2x1p25X1_P65MM BKLT_EDP_IN_DRI_R
R7214 100K 0201_P28
BKLT_EDP_IN_R
2
GND
GND
G
10V 1u
S
57
L_BACKLIGHT_PWM
R7226 1K
MTP7225
VCC
OUT
VIN
C7207
C7208
2.2u 50V
2.2u 50V
2.2u 50V
GND
GND
GND
SW
Look into Pola Tan cap or low noise caps
18 20
BST
SP_TP_SMDp58mm
MTP7288 MTP7287 MTP7289 MTP7285
PWM
SP_TP_SMDp58mm
21
SP_TP_SMDp58mm SP_TP_SMDp58mm SP_TP_SMDp58mm
MTP7224
GND SOT363_6_2x1p25X1_P65MM
57
L_BACKLIGHT_EN
BKLT_EN_R
2
R7208 1K
6 7
SP_TP_SMDp58mm
+VCC_EDP_BKLT_IN SMB_SCL_R
GND
24
5
BKLT_PWM_R
C7206
U7202 1
+VCC_BKLT
C
SP_TP_SMDp58mm
R7228 47
https://vinafix.com
Q7202B
0 0402_P4-S
C7211 0.1u
C7214 0402_P55-S
GND
MTP7201
+VCC_EDP_BKLT_OUT_R
0603S_P6-W
C7204 1u 10V 0402_P55-S
Q7202A S
B
22K
IND_5P4X5P2X1P8MM
GND
1
R7215 0201_p26
M1016438-001 Rdc = 154mOhm
10u 0603 16V
R7227 +VCC_EDP_BKLT_SW
10
4
D
+3P3V_PANEL
C7220
10u 0603 16V
0603_p6-s
G
6
5
C7201
10u 0603 16V
+VCC_EDP_BKLT_IN_DISC
D
3
R7212 200K
15uH 2.5A
C7210
GND
+VCC_EDP_BKLT_OUT
EV2.5 25 Oct 2016 - manually changed MSPN to 15uH
DBG_R R7209 0.01 0603S_P75-W1
D
2
+VCC_EDP_BKLT_IN Imax=??A TDC=??A
SMB_SDA_R
GND
4 3 23
R7229 10K DBG_D
25 GND
EN A0 A1 SCL SDA FT
LED8 LED7 LED6 LED5 LED4 LED3 LED2 LED1 NC22 NC19 NC17
AGND_EP PGND
8 9 10 11 12 13 14 15
BKLT_FB8 BKLT_FB7 BKLT_FB6 BKLT_FB5 BKLT_FB4 BKLT_FB3 BKLT_FB2 BKLT_FB1_R
BKLT_FB1
22 19 17
BKLT_FB8 BKLT_FB7 BKLT_FB6 BKLT_FB5 BKLT_FB4 BKLT_FB3 BKLT_FB2 BKLT_FB1
57 57 57 57 57 57 57 57
B
R7225 0
16
MTP7200 SP_TP_SMDp58mm
MTP7290 GND
SP_TP_SMDp58mm
MTP7286 SP_TP_SMDp58mm
MTP7284
G
2
MP3376AGR-0004-Z M1016236-003
SP_TP_SMDp58mm
DV1.0 14 Decv 2016 - Linked to new part in CIS, same symbol/footprint 31,33,34,37,63,71
6
SMB_SCL
D
S
1
7-bit I2C Address = 0x28
Q7204A DBG_D
3
SMB_SDA
W x H 402 x 260 mm
G
DNP or leave as DBG_D (Removed for Non-Debug)? 31,33,34,37,63,71
isolated ground on layer 2 to tie Cin GND, Cout GND, and controller PGND together. Then tie this isolated ground plane to main GND under the exposed pads. ????
5
A
D
S
4
DBG_D Q7204B 5
4
3
2
A
5
4
3
2
1
PCIe/USB Debug Expansion Connector D
23
C7301, C7302, C7303, C7304, Use 100nF capacitors for Toshiba SSD, For Samsung SSD use 220nF capacitors
PE_WAKE#
+3P3V_EXPCON
+3P3V_EXPCON
C7309
J7301
TP7301
6.3V 0.1u DBG_D
20
U7301
50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
EXPSSD_PCIECLK_REQ#
74AUP1G08FS3-7 DFN5_P85XP85XP4_P48
2 1
18,22,33,37,38,43,44,75 PLT_RST_BUF# 10,25,43,44 PCIE_SSD_PERST#
A B
VCC Y GND
5 4
EXPSSD_PERST#
3
DBG_D
R7305 100K
DBG_D
C
0201_P28
25
B
DBG_D C7313
DBG_D C7311
6.3V
6.3V
1u 0402
1u 0402
DBG_D C7315 0.1u 6.3V 0201
DBG_D C7314 0.1u 6.3V 0201
D
DBG_D C7310 6.3V 22u 0603
PEDET(NC-PCIE/GND-SATA) SUSCLK(32KHZ) PEWAKE#/NC3 CLKREQ#/NC4 PERST#/NC5 3.3V_1 3.3V_2 3.3V_3 GND1 GND2 GND3 DEVSLP 3.3V_4 3.3V_5 3.3V_6 3.3V_7 DAS/DSS#/LED1# GND13 HSTX+ HSTXGND14 3.3V_8 3.3V_9 VBUS GND15
GND4 REFCLKP REFCLKN GND5 PETP0/SATA-A+ PETN0/SATA-AGND6 PERP0/SATA-BPERN0/SATA-B+ GND7 PETP1 PETN1 GND8 PERP1 PERN1 GND9 SSTX+ SSTXGND10 SSRX+ SSRXGND11 D+ DGND12
https://vinafix.com DET2 DET1
EXPCON_DET#
52
DBG_D C7312 6.3V 22u 0603
49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
PCIECLK_EXP_DP PCIECLK_EXP_DN PCIE_EXP_TX0_DP PCIE_EXP_TX0_DN PCIE_EXP_RX0_DP PCIE_EXP_RX0_DN PCIE_EXP_TX1_DP PCIE_EXP_TX1_DN
20 20 24 24 24 24 24 24
PCIE_EXP_RX1_DP PCIE_EXP_RX1_DN
24 24
USB3_EXP_TX_DP USB3_EXP_TX_DN
24 24
USB3_EXP_RX_DP USB3_EXP_RX_DN USB2_EXP_DP USB2_EXP_DN
C
24 24 24 24
DETECT2 DETECT1
DNP
MTG2
MTG1
M1006756-001 DET_GND
51
J7301 is only used for Test on a limited number of units, and is not populated for general EV builds.
B
R7306 1K 0201_p28
DBG_D
+3P3VSB
+3P3V_EXPCON PU7301
C2 PC7316 1u 6.3V 0201_P35-W
IN_A2 IN_B2
OUT_A1 OUT_B1
EN
GND
DBG_D PR7307 0402_p55-w
A1 B1
0.01
SP_TP_SMDp58mm
TP7307 SP_TP_SMDP58MM
C1
TP7308 TP7306 SP_TP_SMDP58MM
PC7317 1u 6.3V 0201S_P39-W
NCP451AFCT2G DBG_D
W x H 357 x 231 mm
A2 B2
GND
A
GND
35,37,47,56,61,62,64,65,75
5
GND
SLP_S3_DRV#
4
3
2
A
5
4
EV2.5 25 Oct 2016 Changed DBG to DBG_R
+5VSB
R7420
SHA_VIN
SP-tp-c0p381
U7408 21,31,33,35,37,39 21,31,33,35,37,39
Rds(on)=120mOhm (typ) Iq=170uA
R7417 100K
0603_1mm
6 3 4
SHA_OC#
BLADE_AUTH_PWR_EN
1
OUT
GND GNDPAD
2
ILIM
R7416 2.2K
R7419 0
C7416 0.1u
AP2553FDC
6.3V
SHA_ILIMIT
ACC plug
A1 A2
B1 B2
OE
DIR2 DIR1
5 4 1 10 C7409 0.1u
GND
QFN10_1P8X1P4XP55_P4MM
6.3V
R7414 R7404
OT_RX_BLADE_IN_R OT_TX_BLADE_OUT_R
6.3V
SN74AVC2T245 Icca=8uA Iccb=8uA
R7402 71.5K 0402_P4-S
3.6V
10 10
A K D7401 BZX584C3V6
3
C7414 1u
VCCB
6
BMA223 INT1
NC_4 CSB
INT2 SDO GNDIO GND_9
+3P3VA 7 3 11 4 C7422 10 0.1u 6.3V
C7423 1u
1 8 9
6.3V
D
ACC Remove
MUX RX TX
BLADE_AUTH_RXTX
6
A K D7402 BZX584C3V6
2
VCCA
5
0
Local RailSource
No ACC
+5V_SHA_CONN
DNP
+1P8VSB
8 9
0
VDD VDDIO PS
25V
U7406
BLADE_RX BLADE_TX
DNP
SCX SDX
C7418 1u 6.3V
R7421 33K
37 37
R7407
12 2
C7419 22p
+3P3VA
7
R7405
BLADE_ACCEL#
0 0
7bit i2c Address 0x18
+5VSB
FAULT EN
5 7
R7418 1M
R7413 499K
IN
R7401 R7403
SAM_SEN_SCL SAM_SEN_SDA
+5V_SHA_CONN
+5V_SHA_CONN Imax=75mA
U7404
D
37
1
37
C7417 10u PMTP7422 6.3V
SP-tp-c0p381
2
Imax = 1.4A 50mA NC COM6.3V
A
4
D1+ D2+
9
U7407 TS3USB30E
6.3V
5
10 8
VCC
MTP7401 SP_TP_SMDp58mm
A1 C7401 0.1u
SP_TP_SMDp58mm
qfn10_1p8x1p4xp55_p4mm
5V_KB_F
L7404
MTP7416
120 OHM @100Mhz 0402_p55-s
B 120 OHM @100MHz 0402_p55-s 1.2A
M1012176-001
A1 B2
+5VSB
CONN_B2B_8_M1012176-001
BLADE_AUTH_EN
+5VSB
10uA
A
R7422 150K
SN74LVC2G66YZPR 37
+5VSB
K
+5VSB R7408 499K
DNP
+5VSB
R7415 150K C7403 100p 25V
2
C7402 100p 25V
A
5
4
3
2
ALL_SYS_PWRGD
58,66
1
+3P3VSB
+VCCST_CPU
+3P3VSB +3P3V
D
22,37,56
C7505 0.1u 6.3V 0201_P33
SLP_S3#
PR7502 4.99K 0201_p28mm
37,61
U7503
2 1
GND
PD7502 RB520CS3002L dio_sod882_1xp6xp5_p7mm K A 30V 200mA
ALL_SUS_PWRGD
GND
VCC Y
A B
5 4
ALL
R7503
0
2
R7504
3
1
SN74AUP1G08DPWR X2SON5 DFN5_P85XP85XP4_P48 TP7501
U7502 74AUP1G07GX SOT1226_P85XP85XP35_P48 5 VCC
A
C7504 0.1u 6.3V 0201_P33
D
R7502 1K 0201_p28
GND
4
Y
NC
VCCST_PWRGD
22
3
GND GND
GND
0 DNP
+3P3VA
60
PD7503 RB520CS3002L dio_sod882_1xp6xp5_p7mm K A 30V 200mA
+1P2V_DUAL_PWRGD
Main power enable 35,37,47,56,61,62,64,65,73
SLP_S3_DRV# PR7508 100K 0201_P28
+VCCIO_PWRGD
200mA 30V
+3P3VSB
PD7501 RB520CS3002L dio_sod882_1xp6xp5_p7mm
PR7503 665K 0201_P28-W
ALL_SYS_PWRGD_R
PR7507 0201_P28
VRM_PWRGD
0
VRM_PWRGD_R
VCC Y
A B
GND
5 4
ALL_SYS_PWRGD_DRI
2
3
GND
PC7502 22u 6.3V 0603_1-W X869827-001
GND
Changed DBG_D to ALL EV2.5 25 Oct 2016
+VCCST_CPU
B
33,36,75
PQ7501B NX3008NBKS SOT363_6_2X1P25X1P1_P65MM
GND PQ7501A NX3008NBKS SOT363_6_2X1P25X1P1_P65MM
https://vinafix.com 1
DFN5_P85XP85XP4_P48
2 1
5
6
0201_P33
74AUP1G08FS3-7
37,58,66
SAM_RESET#
4
PC7501 0.1u 6.3V
U7501
C
3
PD7504 RB520CS3002L dio_sod882_1xp6xp5_p7mm K A 30V 200mA
A
56
K
C
B
PR7505 330 0201_P28 H_THERMTRIP#_BASE DNP R7501 0201_P28
1
PC7503 0201_P33
10
H_THERMTRIP#
2
0.1u
6.3V
GND H_THERMTRIP#_SW
3 PQ7504
0
PQ7505 RUM002N02GT2L SOTFL-3_1P3XP9XP55_P4 S
D
SAM_RESET#
33,36,75
A
18,22,33,37,38,43,44,73
5
W x H 357 x 231 mm
X910413-001
G
SOT883B_3_1P013XP613XP53_P35MM
PLT_RST_BUF#
4
3
2
A
5
4
3
2
1
Check actual placement of RF Fence pairs
RFT7602
DV 2 Dec
SHIELD
Check actual placement of RF Fence pairs
DV 2 Dec
1
DV 2 Dec D
H7609 C2P50D
H7608 M1022851-001 RFT7600
MTG_HOLE_C2P50D_LYNX
T7
H7610 C2P50D
B6 T2
Removed DV 6 Dec 2016
Removed DV 6 Dec 2016
Removed DV 6 Dec 2016
D
FENCE_M1022851-001
DV 2 Dec
1
M1014696-002
1
1
SHIELD 1
M1022779-002
M1022771-002
RFB7601
SHIELD 1
M1022851-001 FENCE_M1022851-001
H7616 H7618
T6
SP-MHOLE_SLOT_1P1X2P1_P6X1P6D
M1022867-001 ZID = 00 ZOD = 00
SP-MHOLE_SLOT_1P1X2P1_P6X1P6D
H7612
M1024828-002
1
RFB7603
SHIELD
MTG_SLOT_N3P2X1P25R_4P5X1P9
H7603 C2P50D
1
1
M1022867-001 ZID = 00 ZOD = 00
DV 2 Dec C
C
T4 M1022756-002
1
H7601 C2P10D
H7617 SP-MHOLE_SLOT_1P1X2P1_P6X1P6D
T5
H7611
T1
Removed DV 6 Dec 2016
1
https://vinafix.com
T3
MTG_SLOT_N3P2X1P25R_4P5X1P9
1
H7606 C2P50D
1
1
1
H7604 H7605 C2P50D C2P50D
M1024826-002
H7607 C2P50D
M1024825-002 M1022730-002
Removed DV 6 Dec 2016
T8 M1024829-002 H7615
B
B
SP-MHOLE_SLOT_1P1X2P1_P6X1P6D
H7613
1 MTG_SLOT_N3P2X1P25R_4P5X1P9
MP7603
MP7604
X941473-001 W7601 X934367-001
X941473-001
SP-PEM_NUT-X934094-001
SP-PEM_NUT-X934094-001
for M1.2 screw
for M1.2 screw 1
1
WASHER-X934367-001
MP7601
MP7602
X941473-001
X941473-001
SP-PEM_NUT-X934094-001
SP-PEM_NUT-X934094-001
1
for M1.2 screw 1
for M1.2 screw
W x H 427 x 276 mm
A
5
4
3
2
A
20160819sjs0452 Name is: Shields, TPs, & Mechanical
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