MSI Combinational Logic (II) : Digital Logic Design Lab [PDF]

Zitiervorschau

International University

Digital Logic Design Lab

MSI Combinational Logic (II) Submitted by Nguyễn Hữu Minh Nhật ITITIU20062 Nguyễn Lê Minh ITITIU20112 Date Performed: October 27th Date Submitted: October 28th Lab Section: Lab 3 Course Instructor: M. Eng Trang Kien

1

GRADING GUIDELINE FOR LAB REPORT Number 1

2

Content Format (max 9%) -

Font type

Yes

No

-

Font size

Yes

No

-

Lab title

Yes

No

-

Page number

Yes

No

-

Table of contents

Yes

No

-

Header/Footer

Yes

No

-

List of figures (if exists)

Yes

No

-

List of tables (if exists)

Yes

No

-

Lab report structure

Yes

No

Comment

English Grammar and Spelling (max 6%) Yes No - Grammar -

3

Score

Spelling

Yes

No

Data and Result Analysis (max 85%)

Total Score

Signature: Date:

2

Table of Contents List of Figures ........................................................................................….….............................. 3 List of Tables .................................................................................................……....................... 4 Discussion of Fundamentals.......................................................................................................... 5 Objectives......................................................................................................................................10 Experimental Procedure.............................................................................................…….........10 Conclusion ...................................................................................................................................25

List of Figures Figure 1-....................................................................................................... 5 Figure 2 – .................................................................................................... 6 Figure 3 – .................................................................................................... 6 Figure 4 – .................................................................................................... 7 Figure 5 – .................................................................................................... 7 Figure 6 – .................................................................................................... 8 Figure 7 –..................................................................................................... 8 Figure 8 –.................................................................................................... 8 Figure 9 –..................................................................................................... 9 Figure 10 – .................................................................................................. 9 Figure 11–................................................................................................... 10 Figure 12 –.................................................................................................. 11 Figure 13 –.................................................................................................. 12 Figure 14 –.................................................................................................. 13 Figure 15 – ................................................................................................. 14 Figure 16 – ................................................................................................. 15 Figure 17 – ................................................................................................. 16 Figure 18 –.................................................................................................. 17 Figure 19 – ................................................................................................. 18 Figure 20 – ................................................................................................. 18 Figure 21 – ................................................................................................. 19 Figure 22 – ................................................................................................. 20 Figure 23 – ................................................................................................. 21 Figure 24 – ................................................................................................. 22 Figure 25 – ................................................................................................. 23

List of Tables

3

Table 1 –............................................................................................................ 10 Table 2 –............................................................................................................ 12 Table 3 –............................................................................................................ 13 Table 4 –............................................................................................................ 14 Table 5 – ........................................................................................................... 18 Table 6 – ........................................................................................................... 19 Table 7 – ............................................................................................................ 20 Table 8 –............................................................................................................. 22

Discussion of Fundamentals 1) Boolean Expression In computer science, a Boolean expression is an expression used in programming languages that produces a Boolean value when evaluated. A Boolean value is either true or false. A Boolean expression may be composed of a combination of the Boolean constants true or false, Boolean-typed variables, Boolean-valued operators, and Boolean-valued functions. Boolean expressions correspond to propositional formulas in logic and are a special case of Boolean circuits. 2) AND, OR, NOT, NAND, NOR, XOR Gates A. AND Gate The AND gate is a basic digital logic gate that implements logical conjunction from mathematical logic – it behaves according to the truth table above. A HIGH output (1) results only if all the inputs to the AND gate are HIGH (1). If none or not all

4

inputs to the AND gate are HIGH, LOW output results. The function can be extended to any number of inputs.

Figure 1 B. OR Gate The OR gate is a digital logic gate that implements logical disjunction (∨) from mathematical logic – it behaves according to the truth table above. A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is high, a LOW output (0) results. In another sense, the function of OR effectively

5

finds the maximum between two binary digits, just as the complementary AND function finds the minimum.

Figure 2 C. NOT Gate The NOT gate performs logical negation on its input. If the input is true, then the output will be false. Similarly, a false input results in a true output.

Figure 3

D. NAND Gate In digital electronics, a NAND gate (NOT-AND) is a logic gate which produces an output which is false only if all its inputs are true, thus its output is complement to that of an AND gate. A low output results only if all the inputs to the gate are high,

6

if any input is low, the result will be a high output. A NAND gate is made using transistors and junction diodes.

Figure 4 E.NOR Gate The NOR gate is a digital logic gate that gives the opposite result to that of the OR gate. If any input of the NOR gate is high, the result of the NOR gate will be the low output.

Figure 5

F. XOR Gate XOR gate is a digital logic gate that gives a high result when the number of true inputs is odd. An XOR gate implements an exclusive OR gate which is a high

7

output if one and only one of the inputs is true. If both inputs are high or low, then the result will be a low output. XOR gate represent the inequality function.

Figure 6 3) Full Adder and Half Adder a) Full Adder Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is designated as S which is SUM.

Figure 7 b) Half Adder The addition of 2 bits is done using a combination circuit called Half adder. The input variables are augend and addend bits and output variables are sum & carry bits. A and B are the two input bits.

Figure 8 8

4) IC Logic Gate a) 74HC148 74HC148 encodes eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enableinput EI and enable output EO) is provided to allow octal expansion without the need for external circuitry. The data inputs and outputs are active at the low logic level.

Figure 9 b) 74HC138 The device accepts a three-bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remain seven being high.

Figure 10 c) 74HC139 9

74HC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application.

Figure 11 Objectives In this laboratory, students will study: -

Understand the operation of combinational logic circuit.

- The operation of some combinational ICs such as: full adder, decoder,

encoder. Experimental Procedure 1. Design the adder with two one-bit binary. a) Design the half adder two one-bit binary. The circuit that detects BCD number includes 4 inputs (A, B, C, D) and 1 output Y. The output Y is HIGH when the BCD numbers in the inputs. Two inputs are A, B. Two outputs are S and C Build the truth table and the expression A B 0 0 0 1 1 0 1 1

S 0 1 1 0

C 0 0 0 1

Table 1 10

The simplified expressions: S=A’B+AB’=A B C=AB Implement the circuit and paste the result

Figure 12 Comment XOR Gate is the SUM output and AND Gate is the CARRY b) Design the full adder two one-bit binary. Three inputs are Cin, A, B. Two outputs are S and Cout Build the truth table and the expressions A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C in 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

C out 0 0 0 1 0 1 1 1 11

Table 2 The simplified expressions: S=A’B’C+A’BC’+AB’C’+ABC= A B C in C out=A’BC+AB’C+ABC’+ABC=C in(A+B)+AB Implement the circuit and paste the result

Figure 13 Comment The first two inputs are A and B, the third input is an input carry as C-IN. This generate SUM and Cout is true only when either two of three inputs are HIGH, then the Cout will be HIGH 2. 8-to-3 Priority Encoder (Interrupt sorter) – IC 74HC148

a) Investigate IC – 74HC148 Construct the circuit as below:

12

Figure 14 The outputs are connected to LED displays to determine the logic levels. Choose the input data D0 - D7 by switches in the order from SW0 to SW7. Control EI by using switch. Observe the results and fulfill the truth table of 74HC148. What are the functions of GS and EO? EI D0 1 X 0 1 0 X 0 X 0 X 0 X 0 X 0 X 0 X 0 0

Input D1 D2 D3 X X X 1 1 1 X X X X X X X X X X X X X X 0 X 0 1 0 1 1 1 1 1

D4 X 1 X X X 0 1 1 1 1

D5 X 1 X X 0 1 1 1 1 1

D6 X 1 X 0 1 1 1 1 1 1

D7 X 1 0 1 1 1 1 1 1 1

GS

Output A2 A1 A0

E0

1

1

1

1

1

1

1

1

1

0

0

0

0

0

1

0

0

0

1

1

0

0

1

0

1

0

0

1

1

1

0

1

0

0

1

0

1

0

1

1

0

1

1

0

1

0

1

1

1

1

Table 3 Implement the circuit and paste the result

13

Figure 15 b) Priority encoder Let’s EI equal to 0, fill the outputs A2, A1, A0 in the following cases A2

A1

A0

Case 1: I3 = I2 = I1 = 0 I7 = I6 = I5 = I4 = I0 = 1.

1

0

0

Case 2: I7 = I2 = 0. I6 = I5 = I4 = I3 = I1= I0 =1

0

0

0

Case 3: All 8 inputs are equal to 0.

0

0

0

Table 4 Case 1: 14

Implement the circuit and paste the result

Figure 16 Comment E0 is high when E1 is low and not all of the input is high When only the A2 is high, just D0, D4, D5, D6, D7 are currently high because the priority encoder starting to check from the D7. And if the D7 high, the encoder will move to another next inputs to check and it will stop when input is low. Only A2 and E0 are high. D7 is the priority. Case 2: Implement the circuit and paste the result 15

Figure 17 Comment The comment is still the same with case 1 and D7 is also still the priority. E0 is the only output show high. Case 3: Implement the circuit and paste the result

16

Figure 18 Comment The comment is still the same with case 1 and D7 is also still the priority. E0 is the only output show high. 3. 2-to-4 Decoder - IC74HC139

Construct the circuit as below:

17

Figure 19 - 4 outputs (Y0-Y3) are connected to LED display (Led 1-4). - The data inputs (A, B) and control input (G) are connected to switches. - Change the states of inputs to fulfill the truth table of IC

74HC139. Inputs Control Data G B A 0 0 0 0 0 1 0 1 0 0 1 1 1 X X

Outputs Y0

Y1

Y2

Y3

0

1

1

1

1

0

1

1

1

1

0

1

1

1

1

0

0

0

0

0

Table 5 Implement the circuit and paste the result

18

Figure 20 Briefly describe the operation of the IC 74HCT139 decoded two binary weighted address inputs (A00, A01) to four exclusive outputs (Y00 to Y03). Each decoder features an enable input (E0). When E0 is HIGH all outputs are forced HIGH. 4. 3-TO-8 Decoder– IC 74HC138

Construct the circuit as below:

Figure 21 - 8 outputs are connected by using LEDs. - The inputs are controlled by switches. - Observe the results and fulfill the truth table INPUT OUTPUT E3 E2 E1 C B A Y0 Y1 Y2 Y 3 Y4 Y 5 Y 6 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 X X X X X 1 1 1 1 1 1 1 1 X 1 X X X X 1 1 1 1 1 1 X X 1 X X X 1

Y7 1 1 1 1 1 1 1 0 1 1 1

Table 6 Implement the circuit and paste the result 19

Figure 22 Briefly describe the operation of the IC 74HC138 accept a three-bit binary weighted address on input pins A0, A1 and A2, when enabled will produce one active low output with the remain seven are going to be high. 5. Design combinational circuits using decoders and OR gate - Implement Boolean expression using IC 74HC138 & OR gate. - The data inputs A, B, C are connected to switches. - The control inputs are in suitable levels. - Implement the circuit and verify the truth table

a) 𝒇 = 𝒙′𝒚𝒛′ + 𝒙𝒛 Establish the truth table x y 0 0 0 0 0 1 0 1 1 0 1 0

z 0 1 0 1 0 1

f 0 0 1 0 0 1 20

1 1

1 1

0 1

0 1

F(x,y,z)=E(2,5,7) Table 7 Implement the circuit and paste the result

Figure 23

21

Figure 24 Comment 2 Figure are having the same result although we change x, y, z b. 𝒇 = 𝒙′𝒚𝒛 + 𝒙 + 𝒚′𝒛′ Establish the truth table x y 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

z 0 1 0 1 0 1 0 1

f 1 0/1 0 1 1/0 1 1 1

Table 8 F(x,y,z)=E(0,3,4,5,6,7) Implement the circuit and paste the result

22

Figure 25 Comment Still remain the same Conclusion After this experiment, we can understand the operation of logic circuits and ICs such as: full adder, half adder, decoder, encoder.

23