K-Touch Confidential: Id Mark [PDF]

Zitiervorschau

5

4

3

2

1

cap Close to BB IC

C102

U101H

cap Close to BB IC

100nF/10V T25 U25

VIO18_PMU

R25 P25

DVDD18_MIPIRX DVSS18_MIPIRX

AVDD28_DAC

F1

AVDD18_AP

E5

DVDD18_MIPITX DVSS18_MIPITX

DVDD18_PLLGP

U9

VIO18_PMU

AVDD18_MD AVSS18_MD AVSS18_MD AVSS18_MD AVSS18_MD

D3 A1 A4 C3 E2

VIO18_PMU

H23 G24 G23

AVDD18_USB AVDD33_USB AVSS33_USB

C101

C108

100nF/10V

100nF/10V

F6

REFP C107

REFP

TP101

C103 C129

100nF/10V

BG

J101 D

TP102

暗码

明码

1

C105

C104 C106

1uF/6.3V 100nF/10V

ID MARK 1

D

VIO18_PMU VUSB_PMU

VTCXO_PMU

100nF/10V

SN二维条码

TP103

100nF/10V

1 TP104 1

G6

1uF/6.3V

REFN MT6572T

dedicate VSS ball, must return to cap then to main GND: 1. REFN(G6) => C107 2. DVSS18_MIPIRX(U25) => C101 3. DVSS18_MIPITX(P25) => C108

GND GND GND GND GND

DVDD18_MC0 DVDD18_CAM DVDD18_VIO_1 DVDD18_VIO_2 DVDD18_VIO_3 DVDD18_LCD

AA1 K20 L3 J19 H13 AB24

VIO18_PMU

DVDD3_MC1

K24

R101

0

DVDD3_LCD

W24

DVDD28_BPI

C10

100nF/10V

VMC_PMU C111

1uF/6.3V

VIO28_PMU C113

VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU VCCK_CPU

NC

1uF/6.3V

P6 T7 P7 P8 P9 R6 R7 R8 R9 T6 U6 T9 T8 U7

Based on your system level design , if better FM performance is needed on your system , please refer to FM desense performance enhance proposal

Close to BB IC, recommand < 150mil

120mil

VCC Core

J9 J15 M9 K6 K7 K8 K9 K11 K14 K15 M10 K16 K17 U17 J8 L7 L8 L9 L17 M6 M7 M8 J10 J11 J14 T16 L6 K12 T17 J16 J17 U12 U13 U14 U15 U16 M17 R17

C115

C117

h

C119

100nF/10V 1uF/6.3V C114

C116

C121

1uF/6.3V

C118

100nF/10V 100nF/10V 1uF/6.3V

C123

1uF/6.3V

C125

VPROC_PMU VPROC_PMU 3

B

C127

2.2uF/6.3V 10uF/6.3V 10uF/6.3V

C120

C122

1uF/6.3V

2.2uF/6.3V 4.7uF/6.3V 10uF/6.3V

C124

C126

Vproc remote sense : differential 4mil with good shielding, from the BB to PMIC

4mil - defferential - GND shielding

VPROC_PMU

Co n

VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK

3

uc To K-

If double-sided SMT, put C109 & C110 below BB. If single-sided SMT, put C109 & C110 around memory.

C112 VCC CPU

Dummy

4

100nF/10V

C128

MT6572T

5

C110

100nF/10V

C

DVDD Peripheral

A

A26

C109

l

U10 U11 V13 W11 Y21

VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI VCCIO_EMI

VCC Memory

ti a

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

1.8V IO for DDR1 1.2V IO for DDR2

de n

B

AC21 AB11 AF13 AD11 AC8 AB5 AB14 W26 T15 W23 T14 AF26 G3 K21 L11 L12 L14 L15 L16 M5 M11 M12 M13 M14 M15 M16 N10 N8 N9 N11 N12 N13 N14 N15 N16 N22 P10 P11 P12 P13 P14 P15 P16 R10 R11 R12 R13 R14 R15 R16 T10 T11 T12 T13 AF1

W9 W12 W14 W16 W19

fi

C

VIO_EMI U101B

3

A

Title

BB- Power 2

Size C

Document Number

Date:

Friday, June 13, 2014

Rev V1.0

MT6572 REF PHONE Sheet 1

1

of

15

4

C514 22pF/50V

3

1K

R551

BPI_0

2

1K

R550

BPI_1

2

2

C515 22pF/50V

J502

2

C551 C552 22pF/50V 22pF/50V

1 R515 10K

VAPC1

1

VBAT

3

3

3

C513 C510 100nF/10V 22pF/50V

TRX1 TRX2 TRX3 TRX4 TRX5 TRX6

TX_LB_IN

C504 NC

3

2 IN

C505 NC

4

J501

GND GND

1

39pF/50V

2G_HB 2G_LB

19 20 21 22 23 24

ASM_ANT_1

C503

R509

0

R507

0

0 C180 NC

ECT818000001

L501 1

12nH 2

2GLB_RXP

1(VIO18) 1(VIO18)

1(VTXCO28) 1(VTXCO28)

VXODIG

VM1

R529

0

[2]

VM0

R531

0

0

4 3 6

L5121

W_PA_OUT_B1

21.0nH

C542 NC

C541 NC

C543 NC

B1_CPL_OUT

2

R538

27

R539

27

PDET

4.7pF/25V

W_PA_OUT_B1

RF_IN

CPL_IN

RF_OUT

U504 RF7248

VEN

L5161

B10 C10

B11

D11 DET

GND GND

VTXHF

C7 J7 C8 J8 C9

NC

L508

R549

2GLB_TX

2GHB_TX

3GB8_RXN

A10

3GB8_RXP

A9

A6

A8

B6

B5

B8

3GH1_TX

3GH2_TX

2GHB_TX

3GB2_RXN

3GB8_RXP

A5 3GB2_RXP

3GB8_RXN

BSI-A_DAT2

2

H8

BSI-A_DAT1

2

B7 J6 D8 E8

GND GND GND GND

GND GND

BSI_CLK

BSI_DATA0 F8

E7 J5

BSI_EN

G8

C6 D6 E6 F6

H6

K9

RX_IN

RX_QP

RX_IP

VRXLF

VXODIG

R523 2K

L10

BSI-A_DAT0

2

BSI-A_CK

2

BSI-A_EN

2

B

4.7pF/25V

L524 2.0nH

C547 NC

h

Co n

3

uc

3GB8_RXN

L5131

9

VPA_PMU

C540 NC

C550 2.2uF/6.3V

CPL_OUT

21.0nH

L514 22nH

6

W_PA_OUT_B8 C544 NC

B8_CPL_OUT

1.8nH 2

U505

L520 33nH

L519 NC

fi

C548

4

To

5

1

TRXB1

2

2 4 5 7 9

2

0

WCDMA B1 ( remove this block if no B1)

K-

8

0

2

R537

should be 4.3pf

5

[2] W_PA_B8_EN

R536

1

U506 SAYRF1G95HQ0F0A 6 TX ANT RX RX

G G G G G

3 1 8

C534 1uF/6.3V

C539 120pF/25V

2

1

2

L522 4.3nH

1

1

2

NC

L523 NC

3GB1_RXN

R541 51R

3GB8_RXP

L515 NC C546

RCAL

J10 K11

L5251

1.8nH 2

8 1 3

RX RX TX

L5171

21.0nH

ANT

A

TRXB8

1

9

1

A

R520 100K,1%,NTC

VRF18-1

C527 TXBPI470nF/10V2

L518 9.1nH

L521 27nH

2

CPL_OUT

R540 36

C545

0 470nF/10V

R520 close to 3G PA VTXLF_VRF18

J11 H10

1

VEN

should be 4.3pf 3GB1_RXP

R517

C524

2

L11

2

RF_OUT

U503 RF7241

56pF/25V R534

7 11

5

VTCXO28-1

2

2

CPL_IN

W_PA_B8_IN C538

GND GND

0

2

TX_I_P TX_I_N

VRF18-1

C533 1.5nF/10V

C549 2.2uF/6.3V

7 11

R535

GND GND GND GND GND

W_PA_B1_IN [2]

VPA_PMU

C537 NC

B8_CPL_IN

[2] W_PA_B1_EN

2

TX_Q_N

GND GND

RF_IN

8

C536 1.5nF/10V

VMODE_0 VMODE_1

4 3 2

B8_CPL_OUT R552 NC

TX_Q_P

3GTX_QN

VBAT

C532 1uF/6.3V

0

R533 NC

3GTX_QP

C530

de n

R532

C531 1.5nF/10V

1 10

18pF/25V

3GTX_IN

Reserved LC filter

G G G G G

0

3GTX_IP

F11

1

0

R530

V28

E10

F10

470nF/10V

VXODIG

VXODIG

VCC1 VCC2

C535

R528

VM0

VMODE_0 VMODE_1

W_PA_B1_IN

VM1

[2]

3GB1_RXN

0

VBAT [2]

W_PA_B8_IN

2nH R527

C529 1uF/6.3V

1(VTXCO28) VTCXO28-1

3GB1_RXP

XO1 DCXO_32K

VIO18

XMODE

VTCXO28-1

B3

XO2

XMODE

RX(I/Q)

K10

J4 C5 D5 E5 F5 D7

XO4

XMODE

VIO18_PMU

0(GND)

DCXO + 32K-Less

GND GND GND GND

3 CLK4_Audio 6 SYSCLK_WCN 2 CLK1_BB 3 DCXO_32K

VXODIG

B

DCXO + 32K XO

BSI_DATA1

GND GND GND GND

TMEAS

C11

G10 G11

l

DCXO_32K_EN

BSI_DATA2

26M output

XO3

C

D9 E9 F9 G9 H9 J9 D10

ti a

NC

R544 0

XMODE

32K_EN

TST1

BSI

CLK_SEL

2 RX_Q_N

R543

VTCXO28-1

Logic DCXO_

TST2

EN_BB

MT6166V

MODE

B4

32K_EN

L2 E4 F4 G4 H4

AVDD_VIO18

SRCLKENA

RCAL

Test pin

L7

SRCLKENA

2,3

VTCXO28

L8

L1 K2

TXBPI

XO

K8

EN_BB CLK_SEL

0 C528 470nF/10V

2,3

K1 G1

connect to main GND

TXVCO_MON VTXLF

XTAL2

K7

VTCXO28_IC

3GTX_QN

XTAL1

K6

R542

VTCXO28-1

RFVCO_MON

J1 H2

DCXO_32K_EN

MT6166

VRXHF

G2

XTAL1

2

3GTX_QP

VRXLF_VRF18

R524 0

F2

XTAL2

3

3GTX_IN

TX(I/Q)

RX_I_P

GND

3GTX_IP

HB_RXP HB_RXN

RX_I_N

Close to each other and nearby X600

Connect TSX/XTAL GND to GND_AUXADC first than connect to main GND

X_TAL

X1E000021043400

R522 NC

Route AUXADC_REF/AUXADC_TSX as differential trace with well GND shielding and route AUXADC_GND with 24mil trace width under AUXADC_TSX/AUXADC_REF trace to provide return current path.

X_TAL

V28

TDD RX

LB_RXN

VIO18_VGPIO

Route AUXADC_GND with 24mil trace width under AUXADC_REF/AUXADC_TSX trace

VRF18-1

GND

TMEAS

LB_RXP

2 4 5 7 9

0

1

B40_RXN

GND GND GND GND GND GND

R526

4

VRXHF_VRF18

470nF/10V

X501 R521 NC

F1

2

1uF/6.3V

Route AUXADC_TSX with 4mil trace width

AUXADC_TSX

VTCXO28-1

E1

GND GND GND GND GND GND

TXO

2

C526

D1

XMODE

VRF18-1

R519 0

C1

470nF/10V PDET

DETGND

L5

R518 NC

C525

2GLB_RXP 2GLB_RXN 2GHB_RXP 2GHB_RXN

FDD RX

VRF18-1 C521 VTXHF_VRF18

B40_RXP

B1

connect to main GND

3

GND GND GND GND GND GND

A1

3GB5_RXP

F3 G3 H3 J3 C4 D4

Route AUXADC_REF with 4mil trace width

AUXADC_REF

GND GND GND GND GND

U502

Two Application Circuit Conditions, 1.TSX Circuit : X600=TSX, R653=R656=NC, R654=100K+-1%, R655=R657=0ohm 2.XTAL Circuit :X600=Mobile XTAL, R653=R656=0ohm, R654=R655=R657=NC

3

A2

2GHB_RXN

3GB1_RXP

6.2nH 2

C

3GB5_RXN

L511 1

A3

2

L510 7.5nH

A11

2GHB_RXP

L509 NC

3GB1_RXN

RFBLN2012090BM5T25

2GLB_TX

2GLB_RXN

G6

6.2nH 2

3GL5_TX

12nH 2

L507 1

RX_QN

L505 1

8

6

2 RX_Q_P

9

7

OUT32K

HBout

2

2 HBout

HBin

5

C523 1.5pF/25V

LBout

GND

XO2

C522 NC

LBout

GND

XO1

4

XO4

3

L4

LBin

2

K5

1 C519 NC

23.0nH

K4

2.2nH 2

1L506

1

1L504 C518 NC

2

22pF/25V

L503 39nH

1

22pF/25V

GND

C517

2G_HBC520

GND

2G_LB

10

L502 NC

K3

SKY77590 control logic table Enable VctC VctB VctA LB_GMSK_TX H L L H HB_GMSK_TX H L H H LB_EDGE_TX H H L H HB_EDGE_TX H H H H TRX1 L H L L TRX2 L H H L TRX3 L H L H TRX4 L H H H TRX5 L L H L TRX6 L L L H

Z501

VRF18_PMU

C507 NC

TRXB8

1

EDGE TXM

0

D

0 C506 NC

TRXB1

1 10

R505 NC

R525

TP3

R508

SKY77590-11

R506 NC

VTCXO_PMU

TP2

K3.1.21.0065 K3.1.21.0065 K3.1.21.0065 R512

6

ANT

1

R504 0

29 28 27 25 15 8 7 6 5 4 3 2 1

C502 56pF/25V

ASM_CPL

26

GND GND

12

11

14 13 VCC VBATT

BS1

16

TX_HB_IN

GND GND GND GND GND GND GND GND GND GND GND GND GND

10

2GLB_TX

TP1

U501

ANT

1

C508 10uF/6.3V

5

R502 NC

9

C509 10uF/6.3V

4

R503 NC

MODE

18 D

R501 0

TX_EN

C501 18pF/25V

VRAMP

2GHB_TX

BS2

17

C516 220pF/50V

1

ECT818000157

4

ECT818000157 R516 24K

J503

3

4

2

1

VCC1 VCC2

1K

2

1K

R514

4

R513

BPI_3

E3 D3 C3 J2 C2

BPI_2

2

2

2

2

5

6

SAYFH897MHC0F0A W_PA_OUT_B8

WCMDA B8 ( remove this block if no B8)

Title

RF-2G Size A1

Document Number

Rev V1.0

MT6572 REF PHONE

Date: 2

Friday, June 13, 2014 1

Sheet

1

of

1

P1版本 -----------------------------------------------------------------------------------------------------------------------------------------------------------------

V0001:初始版本 V0002:删除R402 V0003:添加C327/TP1104;更改CONN_XO_IN网络位置;link原理图库 V0004:增加R718;更改后camera为MIPI接口 V0005:添加mark点和二维明码 V0006:R718变更位置，添加L712/L713 P1.1版本 -----------------------------------------------------------------------------------------------------------------------------------------------------------------

V0001:更改GPIO_TORCH_EN使用GPIO109;PL-Sensor放到FPC上 V0002:添加L714/L715 V0003:更改L716位置 P1.2版本 V0001:EMMC兼容NAND的线上串0ohm电阻（R417-R426) V0002:R403,R404,R405,R407,R412,R413,R414,R415更换为0201封装

To

uc

h

Co n

fi

de n

ti a

l

C202

K-

P2版本 V0001:添加C201

5

4

3

5 5 5 5

RX_I_P RX_I_N RX_Q_P RX_Q_N

5 5 5 5

D

A2 B2 B4 B3

TX_I_P TX_I_N TX_Q_P TX_Q_N

DL_I_P DL_I_N DL_Q_P DL_Q_N UL_I_P UL_I_N UL_Q_P UL_Q_N

VM0 VM1

A8 A7

VM0 VM1

5

TXBPI

D5

TXBPI

5

VAPC1

F2

APC

F3

VBIAS

BPI_BUS0 BPI_BUS1 BPI_BUS2 BPI_BUS3

B12 B11 C12 A11

BPI_BUS4 BPI_BUS5 BPI_BUS6

D11 C11 A13

BPI_BUS7 BPI_BUS8 BPI_BUS9 BPI_BUS10 BPI_BUS11 BPI_BUS12 BPI_BUS13 BPI_BUS14 BPI_BUS15

A10 B10 D10 E9 E8 B9 B8 E7 D7

BSI_DATA2 BSI_DATA1 BSI_DATA0 BSI_EN BSI_CLK

D6 C7 F9 F11 G11

BPI_0 BPI_1 BPI_2 BPI_3 PWM_BL_ctrl

5 5 5 5

U101D

9 EINT_HP

1

HW trapping PIN PMIC_SPI_CS 20K: VM=1.8V NC : VM=1.2V

U101A

D2 C2 B1 C1

2

3 AUD_MISO 3 AUD_CLK 3 AUD_MOSI

7

W_PA_B1_EN [6]

L2 L5 L4 K2

PMIC_SPI_MOSI PMIC_SPI_MISO PMIC_SPI_SCK PMIC_SPI_CSN

3,4 WATCHDOG 3,5 SRCLKENA 3 EINT_PMIC

WATCHDOG SRCLKENA EINTX

3 SIM1_SCLK 3 SIM1_SIO

H5 M3

SIM1_SCLK SIM1_SIO

3 SIM2_SCLK 3 SIM2_SIO

J5 M1

SIM2_SCLK SIM2_SIO

R201

2

EINT_ACC 8 BSI-A_DAT2 5 BSI-A_DAT1 5 BSI-A_DAT0 5 BSI-A_EN 5 BSI-A_CK 5

AUD_DAT_MISO AUD_CLK_MOSI AUD_DAT_MOSI

G2 H4 J2

3 PMIC_SPI_MOSI 3 PMIC_SPI_MISO 3 PMIC_SPI_SCK 3 PMIC_SPI_CS

W_PA_B8_EN [6] GPIO_SPK_EN

J1 K5 K1

NC

D

VIO18_PMU

3

SIM1_SCLK

R202

NC

Normal : NC JTAG : 20K

Reserve R footprint for JTAG debugging VIO18_PMU

MT6572T

MT6572T

3

SIM2_SCLK

R210

NC

Normal : NC JTAG : 20K

U101E

E1

CLK26M

CLK32K_BB

H2

CLK32K_IN

3

RESETB

M2

SYSRSTB

G4

TESTMODE

AC24 3 3

12 12

U101G

R203 L25 K25 H22 J22

13 SUB_CMPDN2 13 SUB_CMRST2 10 GPIO_CMPDN 10 GPIO_CMRST 10 10 10 10 10 10

MIPI_RDN0 MIPI_RDP0 MIPI_RDN1 MIPI_RDP1 MIPI_RCN MIPI_RCP

R24 R23 R22 R21 R26 T26

RDN0 RDP0 RDN1 RDP1 RCN RCP

MIPI_CAM

9 9 differential 9 9

MIPI_TDN0 MIPI_TDP0 MIPI_TDN1 MIPI_TDP1

P19 P20 N25 N26 P23 P24 N20 N19

TDN0 TDP0 TDN1 TDP1 TDN2 TDP2 TCN TCP

MIPI_LCD

100-ohm differential

100-ohm

CMPDN2 CMRST2 CMPDN CMRST

9 9

B

MIPI_TCN MIPI_TCP

R205

1K5

MIPI_VRT

P26

External resistor for DSI Bias.close to BB

5.1K USB output for bias 10 current,close to BB 10

NC

MIPI_2nd_CAM Parallel 8-bit

CMMCLK

Y22

CMPCLK

Y23

RCN_A RCP_A RDN1_A RDP1_A RDN0_A RDP0_A

V25 W25 V24 V23 U22 U21

CMDAT3 CMDAT2 CMDAT1 CMDAT0

Y26 Y25 AA25 AB25

R204

CMMCLK

S_RCN S_RCP S_RDN1 S_RDP1 S_RDN0 S_RDP0

8,9 8,9

10

[13] [13] [13] [13] [13] [13]

12 12 2

VRT

CHD_DP CHD_DM

BC 1.1

USB_VRT

USB_DM USB_DP USB_VRT

USB 2.0

SCL_0 SDA_0 SCL_1 SDA_1

C25 C26 B24 B23

SCL_0 SDA_0 SCL_1 SDA_1

8 EINT_ALPXS

12 12 12 12 12 12

MC1CMD MC1CK MC1DAT0 MC1DAT1 MC1DAT2 MC1DAT3

CTP_ID CAM_ID CAM_ID1

C202 100pF/25V

SPI_MISO SPI_MOSI SPI_SCK SPI_CS

K23 L21 K22 M22 M25 L26

MC1_CMD T-flash MC1_CK MC1_DAT0 MC1_DAT1 MC1_DAT2 MC1_DAT3

VCAMD_IO_PMU

R206 R207

2K2 2K2 SCL_0 SDA_0

KP

UART

PWM_A PWM_B LPD17 LPD16 LPD15 LPD14 LPD13 LPD12 LPD11 LPD10 LPD9 LPD8 LPD7 LPD6 LPD5 LPD4 LPD3 LPD2 LPD1 LPD0

D12 E12

LPCE0B LPTE LRSTB LPRDB LPA0 LPWRB

AD25 AB26 AC26 AA22 AB23 AC25

KROW0 KROW1 KROW2 KCOL0 KCOL1 KCOL2

B25 A24 B26 C24 D24 A25

UTXD1 URXD1 UTXD2 URXD2

E25 D25 E26 1 F26 1

C

GPIO_FLASH_EN 10 EINT_CTP 9

N1 N2 N3 P2 N4 R2 N5 R1 P5 T1 R5 T2 T5 U2 T3 U5 T4 V2

(Reserve)EINT_SIM1 (Reserve)EINT_SIM2

BAT_ID

9

MT6572 support JTAG from below : 1. KP (recommand) 2. MC1 3. CAM for JTAG pin out from MC1/CAM, refer to HW design notice

LCD_ID 9 LPTE 9 GPIO_LRSTB 9 CAM_5MP_PWDN_VCM GPIO_CTP_RSTB 9

KCOL0 KCOL1

TP206

11 11

9

GPIO_TORCH_EN

1

TPΦ0.5

JTCK

1

TP202

1 1

TPΦ1.5 TP205

TPΦ1.5

10

TP201

JTMS

10

UTXD1 URXD1

B

TPΦ0.5 TP203

TPΦ1.5 TP204

TPΦ1.5

UTXD1

Power by CAM_IO

fi

A

SPI

AUX_IN0 ADC AUX_IN1 AUX_IN2_XP AUX_IN3_YP AUX_IN4_XM AUX_IN5_YM

MT6572T

10 10

i2C

F24 F25 F23 E23

B7 B6 C5 B5 C4 A5

MT6572T

C203 C201 100pF/25V 100pF/25V

LCD Parallel

J26 J25

6 GPIO_GPS_LNA_EN

PWM

FSOURCE

G26 G25 H25

CHD_DP CHD_DM

90-ohm differential

USB_DM USB_DP

SYSTEM

l

CLK1_BB

3

ti a

Based on your system level design , if better desense performance is needed on your system , please refer to desense performance enhance proposal

5

de n

C

A

VIO18_PMU

R208 R209

2K2 2K2

4

uc To K-

Power by CTP, MEMS sensor

3

h

5

SCL_1 SDA_1

Co n

8,9 8,9

Title

BB - peripheral 2

Size C

Document Number

Date:

Friday, June 13, 2014

Rev V1.0

MT6572 REF PHONE Sheet 1

2

of

15

5

4

3

2

1

Before you select BJT , please take power dissipation into consideration. Refer to MT6323 design notice

Charger

D

1. Close to Battery Connector. VBUS (Rsense (R328) U303's E, -> U303's C -> R328 -> VBAT) 3. Star connection from R328 to BAT Connector

D

R301

330K

VCDT

VCDT rating: 1.268V 39K

U301

40mils

VBAT

3.3K

CHR_LDO MICBIAS0

3

6 5 2 1

40mils

3

2

VDRV

Q303 2SK3541T2L

Q302

C303 7 100nF/10V 7

AU_VIN0_P AU_VIN0_N

E4 F4

7 7

AU_VIN1_P AU_VIN1_N

G3 G4

QST5TR

D2 D1

VA_PMU

40mils 40mils

ISENSE

4mil R303

Rsense

J2 D3 H2

C304 1uF/6.3V

Differential VBAT

4mil 40mils0.2 OHM

BATTERY CONNECTOR

VIO18_PMU

AUXADC_REF

R306 100K

AUXADC_REF 5

should be 16.9k

1%

40mils

5

GND 4 3 2 GND 1

40mils

4 3 2 1

BAT_ID VBAT BAT_ON

R308 VR302

J301

R309 30K

3.2.02.0203 VR303

VR301

should be 27k

1

1K

ACCDET CLK4_Audio

E2 E1

ISENSE BAT_ON VCDT VDRV

TP302

11 PWRKEY 2,4 WATCHDOG 2 RESETB

R310

1K

2

C326 330pF/50V

EINT_PMIC

K 0K 90 =9 53 = 35 33 R3 ,R K, 9K e 30 c i =9 41t o 3=n 34n R3g i ,3 Rs m,e hm d o khW 0o 1k 7H 43 s is2 i3 CC 6 TT NNT M yyo r r e t er tt t t a ae f bb e fi fR i

2 2 2

TP301

2,5 FCHR_ENB

1

VBAT

AUD_MOSI AUD_CLK AUD_MISO

E7 E8 B6

SRCLKENA FCHR_ENB

A2 M1

2 PMIC_SPI_SCK 2 PMIC_SPI_CS 2 PMIC_SPI_MOSI 2 PMIC_SPI_MISO

TPΦ0.5

4mil (VPA no use) 15mil

1

C309 22uF/6.3V

H13 P8 P6 P5 P2

20mil 20mil 20mil

R311 NC

20mil

J14 M14

VSYS_PMU 2

MM3Z5V1-5 DVDD18_DIG_PMIC

VF : 4.85V~5.36V

Between IC and IO port

A8 A5

VIO18_PMU

B

5 AUXADC_REF 5 AUXADC_TSX

AU_VIN0_P AUDIO AU_VIN0_N

Based on your system level design , if better EOS performance is needed on your system, please refer to EOS performance enhance proposal

AUXADC_REF

C327

C311 10uF/6.3V

AU_VIN1_P AU_VIN1_N

C312 must to be close100nF/10V to PMIC AUXADC_TSX pin

C314 1uF/6.3V C318 NC

K1 L1 H1 G1 H4 J4

AU_SPKP AU_SPKN

7 7

AU_HSP AU_HSN

7 7

AU_HPL AU_HPR

7 7

E9 C9 E10 C10

KPLED

AU_VIN2_P AU_VIN2_N

Please use inductor recommand by MTK Refer to MT6323 design notice

AVDD28_ABB AVDD28_AUXADC GND_ABB

ACCDET

BUCK OUTPUT VPROC VPROC VPROC

CLK26M

BATSNS ISENSE BATON VCDT VDRV

VPROC_FB GND_VPROC_FB VPA VPA VPA_FB

C14 D14 E14

L301 1

VPROC_SW

AUXADC_TSX

C2 B1 B2

PWRKEY SYSRSTB RESETB FSOURCE INT EXT_PMIC_EN

C319 1uF/6.3V

A14 B14

VPA_SW

L303 1

H14

VPA_PMU C

C305 2.2uF/6.3V C325 1nF/50V

VSYS_SW

L302 1

2

VSYS_PMU

VA_PMU ALDO OUTPUT

VA

VCN28 VTCXO VCAMA VCN33 AVDD33_RTC

AUD_MOSI AUD_CLK AUD_MISO

5

M3

VA_PMU

N3 L4

VCN_2V8_PMU VTCXO_PMU

P3 M6 C3

VCAMA_PMU VCN_3V3_PMU VRTC C308 1uF/6.3V

DLDO OUTPUT VM VRF18 VIO18 VIO28 VCN18 VCAMD VCAM_IO

SPI_CLK SPI_CSN SPI_MOSI SPI_MISO VBAT INPUT VBAT_VPROC VBAT_VPROC VBAT_VPROC VBAT_VPA

VEMC_3V3 VMC VMCH VUSB VSIM1 VSIM2 VGP1

VBAT_VSYS VBAT_LDOS3 VBAT_LDOS3 VBAT_LDOS2 VBAT_LDOS1

VIBR VGP2 VGP3 VCAM_AF

AVDD22_BUCK AVDD22_BUCK

J13 H11 L12 M4 J12 K14 L13

VM_PMU VRF18_PMU

VIO18_PMU VIO28_PMU

VCN_1V8_PMU VCAMD_PMU VCAMD_IO_PMU

P7 L6 P4 N6 P9 N9 L8

VEMC_3V3_PMU VMC_PMU VMCH_PMU VUSB_PMU VSIM1_PMU VSIM2_PMU

M7 N8 L14 N7

VIBR_PMU VCAM_AF_PMU

DVDD18_DIG DVDD18_IO B

AUXADC AUXADC_VREF18 AUXADC_AUXIN_GPS AVSS28_AUXADC

VREF

P14

VREF

dedicate VSS ball, must return to cap then to main GND: 1. GND_VREF(N14) => C320 C310

100nF/10V 2 2

BC 1.1 CHD_DM CHD_DP

A10 A11

2 2

SIM1_SCLK SIM1_SIO

B5 M11 E6

2 2

SIM2_SCLK SIM2_SIO

C5 K11 D6

CHG_DM CHG_DP

GND_VREF

SIM LVS

12 12 12

refer to system analog LDO performance improve proposal

1

2 2.2uH

D12

C312

Connect TSX/XTAL GND to AUXADC_GND first than connect to main GND

VPROC_PMU VPROC_PMU 1 C307 4.7uF/6.3V VPROC_PMU

0.68uH

PMU_TESTMODE

SRCLKEN FCHR_ENB

2

0.68uH

B12 C12

CHRLDO

C313 10uF/6.3V

C315 C323 C316 C317 10uF/6.3V 4.7uF/6.3V 10uF/6.3V1uF/6.3V

ISINK0 ISINK1 ISINK2 ISINK3

DRIVER

12 12 12

SCLK SIO SRST

M9 N11 M10

SCLK2 SIO2 SRST2

K9 L11 K10

SIM1_AP_SCLK SIMLS1_AP_SIO SIM1_AP_SRST SIM2_AP_SCLK SIMLS2_AP_SIO SIM2_AP_SRST SIMLS1_SCLK SIMLS1_SIO SIMLS1_SRST

RTC

RTC_32K1V8 RTC_32K2V8 XIN XOUT GND_ISINK GND_VSYS GND_VPA GND_VPROC GND_VPROC GND_VPROC GND_LDO GND_LDO

SIMLS2_SCLK SIMLS2_SIO SIMLS2_SRST GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO

Refer to MT6323 design notice for Zener selection

D9 B7 D8 B8 F13 F14 G13 A13

30mil

D301

M2 A1 K4 A9 A7 N12 N2

Close to PMIC

500mW

AU_HPL AU_HPR

CONTROL SIGNAL

Close to PMIC

Add Zenar Diode Place on the path 80mil from VBAT to IC (Battery connector or test point or IO connector)

AU_HSP AU_HSN

AU_MICBIAS0 AU_MICBIAS1

VSYS

C306 1uF/6.3V

VARISISTOR

P13 P12 K3 A12 M13

CHR_LDO N13

VARISISTOR VARISISTOR

Based on your system level design , if better ESD performance is needed on your system, please refer to ESD performance enhance proposal

GND_SPK

CHARGER

CHR_LDO

R334,R335 must to be close to PMIC AUXADC_REF pin

1%

7 5

VBAT ISENSE BAT_ON VCDT VDRV

SPK_P SPK_N

VBAT_SPK

ISENSE/BSTSNS 4mil differential to Rsense

R305 16.9K 1%

C

6

L2

F2 G2

MICBIAS1

4

1

R304

P1 C302 2.2uF/6.3V

l

R302 C301 1uF/50V

D5 C4 A3 A4

100nF/10V

CLK32K_BB

X1

1

MT6323GA

GND_BUCK

2

C331 18pF/25V

C330 18pF/25V

9H03200012

K6 K8 F5 F6 F7 F8 F9 G5 G6

RTC

2

B10 G11 E13 E11 F11 F10

J10 J9 J8 J7 J6 H10 H9 H8 H7 H6 H5 G9 G8 G7

Refer to MT6323 design notice for Buck GND layout rule

GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO GND_LDO

N14

ti a

cap rating depends on Phone OVP spec.

R312

NC

DCXO_32K

5

Vibra

VIBR_PMU J302 1

PAD_1.5X2.0

J303 1

VRTC

A

1

C322 1uF/6.3V

1

PAD_1.5X2.0

A

de n

R314 1K

Refer to GPS co-clock layout rule

C324 100nF/10V

4

3

K-

To

uc

h

Co n

fi

5

C320 22UF/6.3V

2

Title

PMIC

Size D

Document Number

Date:

Friday, June 13, 2014 1

Rev V1.0

MT6572 REF PHONE Sheet

3

of

15

5

4

VIO18_PMU

AF2 AC5 AE4 AD5 AF3 AF5 AE5 AB6 AB16 AE13 AE14 AC15 AF16 AE15 AE16 AF15 AC7 AE7 AC9 AF6 AB9 AF8 AE8 AE6 AE11 AE9 AF9 AC13 AF11 AF12 AE10 AD15 AB17 AC11

EVREF

BA[1:0] = EA[15:14] (LPDDR1)

C

EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 EA1 EA0

AE19 AE18 AE17 AC23 AF22 AE21 AD24 AC22 AE24 AE26 AE25 AD21 AD22 AB20 AE22 AF21 AE23 AF18 AE20 AF24

ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0

DRAM Data

DRAM Ctrl

ECS0_B ECS1_B EWR_B ERAS_B ECAS_B ECKE EDQM0 EDQM1 EDQM2 EDQM3 EDQS0 EDQS1 EDQS2 EDQS3

EDQS0_B EDQS1_B EDQS2_B EDQS3_B EDCLK0_B EDCLK0 EDCLK1_B EDCLK1 ND0 ND1 ND2 ND3 ND6 ND8 ND9 ND12 ND13 ND15 NCEB NWRB

VREF1 VREF0 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 EA1 EA0

DRAM Address

ERESET

U401

VDD1=1.8V VDD2=1.20V VDDCA=1.20V VDDQ= 1.20V

U101F

ED31 ED30 ED29 ED28 ED27 ED26 ED25 ED24 ED23 ED22 ED21 ED20 ED19 ED18 ED17 ED16 ED15 ED14 ED13 ED12 ED11 ED10 ED9 ED8 ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0

AF25 AD18

ECS0_B ECS1_B

AF19 AB18 AC18 AB19

ECKE

AD12 AE12 AB13 AD8

EDQM0 EDQM1 EDQM2 EDQM3

Y13 AA9 AA14 Y8

EDQS0 EDQS1 EDQS2 EDQS3

AA13 Y9 Y14 AA8

EDQS0_B EDQS1_B EDQS2_B EDQS3_B

Y18 AA18 AA19 Y19 Y4 AA2 V5 W1 Y3 Y2 W2 W4 W3 V1 W5 Y5

EDCLK_B EDCLK NLD0 NLD1 NLD2 NLD3 NLD6 NLD8 NLD9 NLD12 NLD13 NLD15 NCEB NWRB

EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9

U3 T3 R3 R2 R1 K2 J2 J3 H3 H2

ED0 ED1 ED2 ED3 ED4 ED5 ED6 ED7 ED8 ED9 ED10 ED11 ED12 ED13 ED14 ED15 ED16 ED17 ED18 ED19 ED20 ED21 ED22 ED23 ED24 ED25 ED26 ED27 ED28 ED29 ED30 ED31

T8 R8 R7 R9 R6 P7 P8 P9 K9 K8 K7 J6 J9 J7 J8 H8 W7 U6 W8 T5 U7 W9 V8 T6 H6 F8 E9 G7 H5 E8 G6 E7 ZQ0 ZQ1

G3 F3 F6 F9 G10 H10 J5 K10 M5 P10 R5 T10 U10 V6 V9

eMMC I/F MC0_RSTB MC0_DAT7 MC0_DAT6 MC0_DAT5 MC0_DAT4 MC0_DAT3 MC0_DAT2 MC0_DAT1 MC0_DAT0 MC0_CK MC0_CMD

AB1 AD3 AC3 AC2 AD2 AE2 AE1 AB3 AB2 AC1 AE3

1

eMMC MCP

VIO_EMI

0

D

2

162 Ball, 0.5mm pitch

R401

VM_PMU

3

NLD10 NALE NCLE NLD4 NLD5 NLD7 NLD14 NLD11

T1 M1 H1

eMMC_DAT0 NREB

NRNB

NAND_D3_eMMC_VSS

Please make sure the ball map is match to the MCP type you selected

B9 E1 F2 F5 G1 L2 M8 U1 V2 V5 C3 A1 A2 A9 A10 B1 B10 E10 W1 W10 Y1 Y2 Y9 Y10

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

Power

VDDCA VDDCA VDDCA VCC VCC VCCQ VDDI

eMMC

ZQ0 ZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

CLKm RST CMD DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 CS0# CS1# CKE0 CKE1 CLK CLK# DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3#

VSSCA VSSCA VSSCA VSSm VSSm VSS VSS VSS VSS VSS VSS VSS VSS VSSQm

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

DM0 DM1 DM2 DM3

LP-DDR2

VREFCA VREFDQ NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU

E6 F1 V1 W6

VIO_EMI

D

E5 G2 K1 M7 U2 W5 F7 F10 G5 H9 J10 L6 M6 N6 R10 T9 U5 V7 V10 J1 L1 T2 VIO18_PMU

NAND_VCC_eMMC_VCC

A8 B2 B8 A5

NAND_D15_eMMC_VCCQ NAND_VCC_eMMC_VDDI

B5 C1 C5

NREB NLD10

B4 A4 A6 B6 A7 B7 B3 A3

NALE NCLE NLD4 NLD5 NLD7 NLD14 NLD11

NRNB

NAND_WPB_eMMC_DAT0

P1 P2

ECS0_B ECS1_B

N1 N2

ECKE

M3 L3

EDCLK EDCLK_B

P6 P5 K6 K5 U8 U9 G8 G9

R416 47K

C401 100nF/10V

C

EDQS0 EDQS0_B EDQS1 EDQS1_B EDQS2 EDQS2_B EDQS3 EDQS3_B

N5 L5 T7 H7

EDQM0 EDQM1 EDQM2 EDQM3

K3 M9

EVREF

R420 C2 R421 C4 R422 C6 R423 D1 R424 D2 R425 D3 R426 D4 R427 D5 R428 D6 R429 E2 E3 M2 N3 P3 V3 W2 W3

NC NC NC NC NC NC NC NC NC NC

NLD1 NWRB NLD6 NLD8 NLD0 NLD2 NCEB NLD12 NLD13 NLD9

H9TP32A4GDBCPR-KGM

B

B

Power, Reference

l

Jumper for co-lay

VIO_EMI

VIO18_PMU C402 4.7uF/6.3V

ti a

Put C402 & C403 between BB & memory. C403 100nF/10V

VIO18_PMU

C404 100nF/10V

C405 C406 100nF/10V 4.7uF/6.3V

R403

NAND_VCC_eMMC_VCC

R404

C407 1uF/6.3V

0

NAND

NC

eMMC

C408 4.7uF/6.3V

VEMC_3V3_PMU

C409 4.7uF/6.3V

VIO_EMI

NAND_D15_eMMC_VCCQ NAND_VCC_eMMC_VDDI

R405

0

NAND

NAND R403 R405 R412 R414

NLD15

VIO18_PMU

R406 8.2K

R407

NC

eMMC

EVREF R408 R410

ZQ0 ZQ1

240 240

R409 R411 8.2K

0

NLD3

NAND

R412

NAND_D3_eMMC_VSS

NC

de n

eMMC R413

A

0

NAND_WPB_eMMC_DAT0

R414

R415

4

3

K-

To

uc

h

Co n

fi

5

C411 1uF/6.3V

NAND

C410 100nF/10V

eMMC R404 R407 R413 R415

0

NAND

WATCHDOG

NC

eMMC

eMMC_DAT0

2

A

2,3

Title Size D Date:

Memory Document Number

Rev V1.0

MT6572 REF PHONE

Friday, June 13, 2014 1

Sheet

4

of

15

5

4

3

2

1

U101C

D

CONN_XO_IN

C601

0

SYSCLK_WCN

5

Close to MT6572

GPS_RX_IN GPS_RX_IP

B16 A16

GPS_RXIN GPS_RXIP

GPS_RX_QN GPS_RX_QP

B14 B15

GPS_RXQN GPS_RXQP

WB_TXIN WB_TXIP

A19 B19

WB_TXIN WB_TXIP

WB_TXQN WB_TXQP

B18 A18

WB_TXQN WB_TXQP

WB_RXIN WB_RXIP

A21 A22

WB_RXIN WB_RXIP

B20 B21

WB_RXQN WB_RXQP

WB_RXQN WB_RXQP

AVDD18_WBG F18

AVDD18_WBG

GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG GND_WBG

A14 D18 B22 C16 C17 C18 C19 C20 C21 C15 D16 D17 D19 D20

CONN_WB_CTRL0 CONN_WB_CTRL1 CONN_WB_CTRL2 CONN_WB_CTRL3 CONN_WB_CTRL4 CONN_WB_CTRL5

E20 F20 D22 E22 C22 C23

WB_CTRL0 WB_CTRL1 WB_CTRL2 WB_CTRL3 WB_CTRL4 WB_CTRL5

CONN_RSTB CONN_SEN CONN_SDATA CONN_SCLK

C14 E15 E14 G12

CONN_RSTB CONN_SEN CONN_SDATA CONN_SCLK

R602

0

VCN_1V8_PMU

C602 100nF/10V

AVDD18_WB

VCN_1V8_PMU

AVDD18_GPS

VCN_1V8_PMU

D

C603

AVDD18_WBG

CONN_F2W_DAT CONN_F2W_CLK

E13 F12

CONN_XO_IN

F14

C604 1uF/6.3V 4.7nF/50V C605

C606

100nF/10V

100pF/25V

FM_DATA FM_CLK CONN_XO_IN AVDD28_FM

no need DC block cap

R605

C607

0

VCN_2V8_PMU

10nF/10V

MT6572T WB_CTRL3 R610 TP601

0 WB_CTRL2

TP603

WB_CTRL4 U604

K3.1.21.0065

K3.1.21.0065

WB_CTRL1

6

GND

WiFi

1

5

ANT

GND

2

C608

18pF/25V

Close to MT6627

WB_CTRL5 WB_CTRL0

R606

0

R609

NC

AVDD33_WB

AVDD33_WB

0

VCN_3V3_PMU C611

C610 2.2uF/6.3V

C621 0.22uF/10V

2.2uF/6.3V

C

21

22

24

25

26

23 HB0

HB1

WB_RX_IN

50 Ohm

50 Ohm

WB_RX_IP

WBG_ANT

WB_EXT_G

30

U601

WB_RXIN

HB2

LFD181G58DP8D754TEMP

R607

C609 100pF/25V

HB3

GPS_RF_LNA

28

18pF/25V

27

C612

3

GPS

HB4

GND

PTA

C

4

L605 NC

AVDD18_WBT

L604 NC

29 AVDD18_WB

WB_RXIP

WB_RX_QP

20 WB_RXQP

WB_RX_QN

19 WB_RXQN

31

WB_GPS_RF_IN

32

GPS_DPX_RFOUT

33

AVDD33_WBT

WB_TX_IP

34

NC

WB_TX_IN

17 WB_TXIN

35

NC

WB_TX_QP

16 WB_TXQP

36

AVDD28_FM

WB_TX_QN

15 WB_TXQN

37

FM_LANT_N

GPS_RX_IP

14 GPS_RX_IP

38

FM_LANT_P

GPS_RX_IN

13 GPS_RX_IN

18 WB_TXIP

R601 NC

AVDD28_FM

FM FM_LANT_N

7 FM_RX_N_6572

RFIN VCC GND SHDN GND RFOUT

4 5 6

C619

L907 2.2pF/25V C620

BGU7007115 SAFEB1G57KE0F00R14

CEXT

SCLK

F2W_CLK

F2W_DATA

GPS_RX_QP

12 GPS_RX_QP

GPS_RX_QN

11 GPS_RX_QN

B

XO_IN

10

2

6.2nH

9

GPIO_GPS_LNA_EN

33pF/25V

6

0

U603

3 2 1

5

L603 5.6nH

470pF/50V

de n

4

4

C622

OUT

G G G

IN

2 3 5

1

1

R612 U602 GPS_RF_LNA

DVSS

1uF/6.3V

3

41

R613 0 C616

AVDD28_FSOURCE

VCN_2V8_PMU

FM_DBG

AVDD18_GPS

HRST_B

AVDD18_GPS 40

GPS_RFIN

2

GPS_RFIN 50 Ohm 39

SEN

L602 NC

B

ti a

FM_LANT_P

8

82nH

SDATA

L606

FM_ANT

7

7

MT6627N

l

50 Ohm

MT6627 SMD QFN40

CONN_RSTB

C617

CONN_XO_IN

C618

FM_DATA

1uF/6.3V

100pF/25V

FM_CLK

CONN_SCLK A

A

CONN_SDATA

4

3

K-

To

uc

h

Co n

5

fi

CONN_SEN

北京天语朗通通讯设备股份有限公司 Title K-TOUCH TBT9720 Size A2 Date:

2

Document Number WIFI_BT_FM_GPS Friday, June 13, 2014

Rev

Sheet

1

6

of

15

5

3

AU_SPKP

close to IC

close to connector

C701 33pF/25V L712

SPK_P

R701

2000@1GHz

1

1

3

Earphone Audio

TP701 PAD_1.5X1.5

0

2

same power domain close to IC

close to connector

C702 3

AU_SPKN

100pF/25V L713

SPK_N

R703

D

2000@1GHz

1

1

C703 33pF/25V

0

Based on your system level design , if better desense performance is needed on your system , please refer to desense performance enhance proposal

VIO28_PMU

R702 470K

EINT_HP

R704 47K

TP702 PAD_1.5X1.5

VR701

1

Reserve bead+C footprint for FM performance tuning

2

D

VR702 C730 C704C705 HP_MIC

L705

2500@100M

L702 L704

2500@100M 2500@100M

3.2.11.0074

NC NC

C708 33pF/25V C710 33pF/25V

J703

600@100M

R707R708

2 RSB6.8CMGJT2N 2

AU_HSN

5 3 2

L R GND

470 470 1 2

C711

A K

100pF/25V 3

MIC MIC L

J701

VR711

C707 10uF/6.3V

6 1 4

1 1VR706

L707

L703 2500@100M

AU_HPR

EAR_DET HP_MP3L HP_MP3R VR705

close to connector

C709 33pF/25V AU_HSP

C706 10uF/6.3V R705 100 R706 100

3

3

L701 2500@100M

AU_HPL

VR704

close to IC

3

VR703

Receiver

1.2pF/25V

L711 2000@1GHz

美标

Speaker

4

L708

600@100M

RECEIVER C712 33pF/25V

FM_ANT

6

L706 VR707

VR708 100nH

C

Earphone MICPHONE Handset Microphone 1

Close to BB 3

MICBIAS0

AU_VIN1_N

R711 1K

R718 NC

AU_VIN1_N1

C720

Analog MIC

AU_VIN1_P

1 2

C714 4.7uF/6.3V 100nF/10V

3 2000@1GHz

HP_MIC

together then single via to main GND

R715

ACCDET 1K

SOM4013SL-G443-C1033-HS

C717 33pF/25V R712 1K5

C718 33pF/25V

VR709

VR710

VBAT

de n

R714 1K

C725 15nF/16V R719

C726 15nF/16V R720

3K

INN

C171 220pF/50V A1 INP A4

GPIO_SPK_EN

/SHDN

Co n

C2

AW8736FCR

3

K-

To

uc

h

4

GND

R717 100K

5

C2N C2N

CIN C2P

C1P

VDD VDD

A2

fi

2 A

3K

GND

AU_HPL

U1302

B3 A3

GND

3

C732 100nF/10V

B1 B2

D2

C1 D1

C733 2.2uF/6.3V C734 2.2uF/6.3V

C731 4.7uF/6.3V

together then single via to main GND

B

VOP

B4

R721

0

SPK_P

VON

D4

R722

0

SPK_N

PVDD

D3

C728 NC

C729 NC A

C727 4.7uF/10V

C4

if you use digital MIC, please change cap (C511,C512) to 1.0uF

+ -

C3

AU_VIN0_N

B

C715 100pF/25V L715

C723 33pF/25V

C724 100nF/10V

J702 100nF/10V

3

3

2000@1GHz

ti a

L714

l

C722 100pF/25V

R710 1K5

C716

Close to EarJack

R713 1K5

C721 33pF/25V

Close to MIC

C713

AU_VIN0_P

C

4.7uF/6.3V

R709 1K

3

FM_RX_N_6572 6

GND of C(4.7uF) and headset should tie together and single via to GND plane

100nF/10V

Close to BB

0

Single via to GND plane

MICBIAS1

Close to MIC

C719

R716

Title

Audio 2

Size C

Document Number

Date:

Friday, June 13, 2014

Rev V1.0

MT6572 REF PHONE Sheet 1

7

of

15

5

4

3

2

1

G-Sensor VIO18_PMU VIO18_PMU

VBAT U801

D

L801 2

600@100M R801

EINT_ACC 2,9 C801

NC

SDA_1

C802

D

3 4 7

VDDIO VDDD VDDA

5

INT

1 2

SDO SDX

10 11 12

CSB PS SCK

VIO18_PMU SCL_1

2,9

C804 2.2uF/6.3V

U803

6 8 9

CAPO GND GND

BMA220

2,9

100nF/10V100nF/10V

SCL_1

VIO28_PMU

4

LED+

LED-

5

3

GND

IRDR

6

2

SCL

INT

7

1

VDD

SDA

8

C805 100nF/10V

C

R804 100K

EINT_ALPXS SDA_1

2

2,9

TMD27723

预留接近传感器 C

ALS & PS Sensor

M-Sensor VIO18_PMU VA_PMU

1,7 1,7

6

SCL_1 SDA_1

3 4

SCL SDA

8

CAP

C812

VDA

12

VSA

11

VDD

TEST VPP NC NC NC NC

4.7uF/6.3V

1 5

VA_PMU

3,9,14

C807 100nF/10V

2 7 9 10

MMC3416XPJ

4

3

K-

To

uc

h

Co n

fi

5

de n

COMPASS A

B

ti a

U802 C806 100nF/10V

l

B

2

A

Title

MEMS Sensors Size B

Document Number

Date:

Friday, June 13, 2014

Rev V1.0

MT6572 REF PHONE Sheet 1

8

of

15

5

4

3

2

1

VIO18_PMU VIO28_PMU

C901 1uF/6.3V

C902 1uF/6.3V

J901 R901

LCD_ID

1K

32

LCM_ID

26 27 29 30

IOVCC IOVCC VCC VCC

BLIGHT_PWM

24 23 22

TE RESET PWM_OUT

2 2

MIPI_TCN MIPI_TCP

15 16

HSSI_CLK_N HSSI_CLK_P

2 2 2 2

MIPI_TDN0 MIPI_TDP0 MIPI_TDN1 MIPI_TDP1

12 13 18 19

HSSI_D0_N HSSI_D0_P HSSI_D1_N HSSI_D1_P

D

D

VR902

VR901

2 LPTE 2 GPIO_LRSTB

L901 R902

VBAT

KPLED

700@1GHz 0

LEDLED+ C911 1uF/6.3V

C

2 9

CTPLEDA CTPLEDK

3 8

LEDLED+

1 5 6 10 11 14 17 20 21 25 33 34 35

GND GND GND GND GND GND GND GND GND GND GND GND GND

4 7 28 31

NC NC NC NC

C

LED+

5

FB

3

CTP_ID

C1705，C1721用TY21000003 耐压50V LEDR912 15

RT8514GJ6

R909

1K

1 1VR908

EN GND

VOUT

1 1VR907

R911 10K

LX VIN

2 RSB6.8CMGJT2N 2

4 2

1 1VR909

0

2 RSB6.8CMGJT2N 2

PWM_BL_ctrl

1 6

NC

1 1VR906

2

R910

2,8 SDA_1 2,8 SCL_1 2 EINT_CTP 2 GPIO_CTP_RSTB

C907700@1GHz 15pF/50V

2 RSB6.8CMGJT2N 2

BLIGHT_PWMR908

C906 1uF/50V

1 1VR905

1

2 RSB6.8CMGJT2N 2

2

U902

J902

2 RSB6.8CMGJT2N 2

22uH

PMEG6010CEJ C908 4.7uF/6.3V

R906 R907 NC NC

de n

L903

L904

D901

LCD Backlight

1 2 3 4 5 6 7 8 9 10

1 2 3 4 5 6 7 8 9 10

12

12

11

11

1 1VR904

C904 33pF/25V

1uF/6.3V

2 RSB6.8CMGJT2N 2

1uF/6.3V

B

2 RSB6.8CMGJT2N 2

C903

C905 VBAT

B

VIO28_PMU

ti a

1 1VR903

VIO18_PMU

l

BL125-33RL-TAGF

BL509-10G31-TAH1

fi

CTP connector

4

3

K-

To

uc

h

5

Co n

A

A

Title

LCD, Touch 2

Size C

Document Number

Date:

Friday, June 13, 2014

Rev V1.0

MT6572 REF PHONE Sheet 1

9

of

15

5

4

3

2

1

Main CAM

D

D

2 GPIO_CMPDN 6 GPIO_CMRST

L1001

600@100M

2

C1024 1uF/6.3V

D1001

XI2323/KK3C-H5050M4P3B63Z6/2T(UN)

2 2

1

MIPI_RCN MIPI_RCP

CMMCLK

2 R1002 0

VCAM_AF_PMU SCL_0 2 SDA_0 2 CAM_5MP_PWDN_VCM 6

R1003 10

33 34

3

C1001 C1002 1uF/6.3V 22uF/6.3V

Camera Flash

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

2 GPIO_FLASH_EN

R1004 1K

Q1001 MMBT2222ATT1

1 R1005 100K

Q1002 MMBT2222ATT1

R1006 1K

1

2

VCAMA_PMU

ID SPI_CLK MDN1 VSYNC MDP1 DGND DGND MCN MDN0 MCP MDP0 DGND DGND SPI_D1 STROBE SPI_D0 PWDN DGND RESET XCLK DOVDD_1.8 DGND DGND AF_VCC_2.8 DGND SIOC AVDD_2.8 SIOD AGND AF_EN

3

VCAMD_IO_PMU

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

2

MIPI_RDN0 MIPI_RDP0

GND GND

CAM_ID MIPI_RDN1 MIPI_RDP1

2 2

AXT530124

GND GND

10 10 10

31 32

VBAT

J1001

GPIO_TORCH_EN 2

R1007 100K

预留闪光灯

C

S_RDN0 S_RDP0

[13] [13]

S_RCN S_RCP 2

2

CMMCLK

CAM_ID1

24 23 22 21 20 19 18 17 16 15 14 13

24 23 22 21 20 19 18 17 16 15 14 13

SCL_0 SDA_0

2 2 VCAMD_PMU VCAMA_PMU S_RDP1 [13] S_RDN1 [13] SUB_CMRST2 13 SUB_CMPDN2 13

l

[13] [13]

J1002 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12

C1020 C1021 100nF/10V 1uF/6.3V

BBR43-24KB533

ti a

VCAMD_IO_PMU

C

C1022 100nF/10V

B

fi

de n

B

4

3

K-

To

uc

h

5

Co n

A

A

Title

Camera 2

Size C

Document Number

Date:

Friday, June 13, 2014

Rev V1.0

MT6572 REF PHONE Sheet 1

10

of

13

5

4

TP1101

D

3

2

1

D

VBAT

TP1102

TP1103

1

1 TEST PAD 3

1

S1 2 4

PWRKEY

C

1 3 7 6 5

VR1101

C

1

TP1104

2

KCOL0

R1103

S2

1K DL_KEY

2 4

1 3 7 6 5

VR1103

1 3

A

4

3

K-

To

uc

h

Co n

fi

5

B

ti a

2 4 VR1102

de n

KCOL1

S3

1K

7 6 5

2

R1102

l

B

2

A

Title

KP Size B

Document Number

Date:

Friday, June 13, 2014

Rev V1.0

MT6572 REF PHONE Sheet 1

11

of

13

5

D

4

3

2

USB HS IF

VSIM1_PMU D

TP1201

TP1202 J1202

VR1206 C1204 1uF/50V

0

VR1212

1

VR1201

R1214

VR1207

UTXD1

10

1 2 3 4 5

TP1203

VSIM

GND

1

SRST

5

RST

VPP

2

3

SCLK

4

CLK

I/O

3

6 7

6 3

VBUS DD+ ID GND

SIO

3

SIMF006G5K24-00R C1203 1uF/6.3V

3.2.01.0131

8 9

USB_DM USB_DP

GND GND

J1201

GND GND

1

1

VBUS

2 2

1

SIM CARD2

C

C

VSIM2_PMU

Micro SD CARD

VMCH_PMU

J1203

R1205 NC

6

VSIM

GND

1

3

SRST2

5

RST

VPP

2

3

SCLK2

4

CLK

I/O

3

SIO2

3

SIMF006G5K24-00R C1206 1uF/6.3V

R1208 R1209 R1210

22 22 22

2

MC1CK

R1211

0

2 2

MC1DAT0 MC1DAT1

R1212 R1213

22 22

1 2 3 4 5 6 7 8

DAT2 CD/DAT3 CMD VDD CLK VSS DAT0 DAT1

VSS VSS VSS VSS

9 10 11 12

VAR出BOM全部NC

SIM CARD1

3.2.04.0049

T-Flash Card A

3

K-

To

uc

h

Co n

fi

4

de n

C1207 C1208 C1209 C1210 C1211 C1212 C1213 18pF/25V 18pF/25V 18pF/25V 18pF/25V 18pF/25V 18pF/25V 1uF/6.3V C1214 1uF/6.3V

5

B

ti a

MC1DAT2 MC1DAT3 MC1CMD

2 2 2

l

J1204 B

2

A

Title

USB Size B

Document Number

Date:

Friday, June 13, 2014

Rev V1.0

MT6572 REF PHONE Sheet 1

12

of

13

5

4

3

2

1

Project : MT6572 REF_SCH TOP LEVEL

Celullar ANT

FEM

BPI, APC

x32

EMI

EMI

TX

RX

Memory MCP NFI

D

RF IQ

D

NFI BSI ctrl

micro SD + hot-plug

MSDC1

MSDC 4-bit

RX balun

MT6166

26M_BB 26M_AUD

26M DCXO ctrl 26M_CN

ABB SPI

CMMB

MT6572

26M_CN

TCXO

Connectivity ANT

CONN IQ

EINT CONN ctrl

MT6627

C

C

2nd Camera Module

Camera IF

MT6323 I2C

LCD module

LCD IF

CTP controller

I2C

i2C_0

i2C_1

EINT

POWER

EINT SPI

EINT I2C

B

SIM2

Power Management

de n

I2C

Gyro sensor

Receiver

AU_VIN0

EINT

I2C

Magnetic sensor

Audio Speech

AUD I/F

I2C

ALS + PXS

Headset (HPL, HPR, AU_VIN1)

Class D/AB

LCD (MIPI / Parallel)

B

Motion Sensor

32K

RTC

32K_BB

CAM (MIPI / Parallel)

l

Camera IF

ti a

Camera Module

SIM2

SIM1

SIM1 VIB

BC1.1

EINT

Charger

Charger

Keypad

Battery

fi

BJT

JTAG

Debug port

UART

4

3

K-

To

uc

h

5

A

micro USB

USB 2.0

USB

Co n

A

Title

MT6572 Block diagram 2

Size C

Document Number

Date:

Friday, June 13, 2014

Rev V1.0

MT6572 REF PHONE Sheet 1

15

of

15