PCS-915SC - X - Technical Manual - EN - Overseas General - X - R1.01 [PDF]

Zitiervorschau

Copyright © 2019 NR. All rights reserved. NR, the NR logo are either registered trademarks or trademarks of NR Electric Co., Ltd. No NR trademarks may be used without written permission. NR products appearing in this document may be covered by P.R. China and foreign patents. NR Electric Co., Ltd. reserves all rights and benefits afforded under P.R. China and international copyright and patent laws in its products, including but not limited to software, firmware and documentation. NR Engineering Co., Ltd. is licensed to use this document as well as all intellectual property rights owned or held by NR Electric Co., Ltd, including but not limited to copyright, rights in inventions, patents, know-how, trade secrets, trademarks and trade names, service marks, design rights, database rights and rights in data, utility models, domain names and all similar rights. The information in this document is provided for informational use only and does not constitute a legal contract between NR and any person or entity unless otherwise specified. Information in this document is subject to change without prior notice. To the extent required the products described herein meet applicable IEC and IEEE standards, but no such assurance is given with respect to local codes and ordinances because they vary greatly. Although every reasonable effort is made to present current and accurate information, this document does not purport to cover all details or variations in equipment nor provide for every possible contingency to be met in connection with installation, operation, or maintenance. Should further information be desired or should particular problems arise which are not covered sufficiently for your purposes, please do not hesitate to contact us.

Preface

Preface About This Manual The technical manual describes the protection, automation, control, and supervision functions of PCS S series device for line differential protection, and contains operation principle descriptions, and lists function blocks, logic diagrams, input and output signals, setting parameters and technical data, sorted per function, as well as the hardware of the device. The manual can be used as a technical reference during the engineering phase and during normal service. In addition, the manual also includes a glossary that lists and defines technical terms used throughout the manual.

Safety Information This manual is not a complete index of all safety measures required for operation of the equipment (module or device). However, it comprises important information that must be followed for personal safety, as well as to avoid material damage. Information is highlighted and illustrated as follows according to the degree of danger: Indicates an imminently hazardous situation that, if not avoided, will result in death or serious injury. Indicates a potentially hazardous situation that, if not avoided, could result in death or serious injury. Indicates a potentially hazardous situation that, if not avoided, may result in minor or moderate injury or equipment damage. Indicates that property damage can result if the measures specified are not taken. Important information about the device, product handling or a certain section of the documentation which must be given particular attention.

Instructions and Warnings The following hazard statements apply to this device.

Disconnect or de-energize all external connections BEFORE opening this

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Preface

device. Contact with hazardous voltages and currents inside this device can cause electrical shock resulting in injury or death.

Contact with instrument terminals can cause electrical shock that can result in injury or death.

Use of this equipment in a manner other than specified in this manual can impair operator safety safeguards provided by this equipment.

Have ONLY qualified personnel service this equipment. If you are not qualified to service this equipment, you can injure yourself or others, or cause equipment damage.

This device is shipped with default passwords. Default passwords should be changed to private passwords at installation. Failure to change each default password to a private password may allow unauthorized access. NR shall not be responsible for any damage resulting from unauthorized access.

DO NOT look into the fiber (laser) ports/connectors.

DO NOT look into the end of an optical cable connected to an optical output.

DO NOT perform any procedures or adjustments that this instruction manual does not describe.

During installation, maintenance, or testing of the optical ports, ONLY use

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Preface

the test equipment qualified for Class 1 laser products!

Incorporated components, such as LEDs, transceivers, and laser emitters, are NOT user serviceable. Return units to NR for repair or replacement.

Equipment components are SENSITIVE to electrostatic discharge (ESD). Undetectable permanent damage can result if you do not use proper ESD procedures. Ground yourself, your work surface, and this equipment BEFORE removing any cover from this equipment. If your facility is not equipped to work with these components, contact NR about returning this device and related NR equipment for service.

Insufficiently rated insulation can deteriorate under abnormal operating conditions and cause equipment damage. For external circuits, use wiring of SUFFICIENTLY RATED insulation that will not break down under abnormal operating conditions.

SEVERE power and ground problems can occur on the communications ports of this equipment as a result of using non-standard cables. Please use the wiring method recommended in the manual for communication terminals.

DO NOT connect power to the relay until you have completed these procedures and receive instruction to apply power. Equipment damage can result otherwise.

Use of controls or adjustments, or performance of procedures other than those specified herein, may RESULT IN hazardous radiation exposure.

The firmware may be upgraded to add new features or enhance/modify

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Preface

existing features, please MAKE SURE that the version of this manual is compatible with the product in your hand.

Document Conventions 

The abbreviations and acronyms in this manual are explained in “Appendix A Glossary”. The Glossary also contains definitions of important terms.



Menu path is connected with the arrow "→" and bold. For example: the access path of protection settings is: MainMenu -> Settings -> Protection Settings



Settings not in the table should be placed in brackets. For example: the system setting [Opt_SysFreq]



Cross-references are presented in italics. For example: refer to Figure 1.1-1, refer to Table 1.1-1, reference to Section 1.1



Binary input signals, binary output signals, analogs, LED lights, buttons, and other fixed meanings, should be written in double quotes and bold. For example: press the button "ENT".

Symbols 

AND Gate

&



&

&

>=1

>=1

OR Gate

>=1



Comparator



Binary signal Input BI

IV

xxx

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

Signal input SIG



Setting input SET



xxx

Enable input EN



xxx

xxx

Timer Optional definite-time or inverse-time characteristic Timer t t



Timer Fixed delay pickup (10ms), fixed delay drop-off (2ms) 10ms



2ms

Timer Settable delay pickup, fixed delay drop-off [Tset1]



0ms

Timer Fixed delay pickup, settable delay drop-off 0ms



[Tset2]

Timer Settable delay pickup, settable delay drop-off [Tset1]



[Tset2]

Generator

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Preface

G 

Transformer



Reactor



Motor

M 

Capacitor

C 

Busbar



Circuit breaker

52



Current transformer 3CT

*



VI

Voltage transformer

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3VT



Disconnector



Earth

Three-phase Corresponding Relationship Basic A, B, C

L1, L2, L3

R, Y, B

AN, BN, CN

L1N, L2N, L3N

RN,YN, BN

ABC

L123

RYB

U (voltage)

V

U Example

Ia, Ib, Ic, I0

IL1, IL2, IL3, IN

IR, IY, IB, IN

Ua, Ub, Uc

VL1, VL2, VL3

UR, UY, UB

Uab, Ubc, Uca

VL12, VL23, VL31

URY, UYB, UBR

U0, U1, U2

VN, V1, V2

UN, U1, U2

Copyright Copyright © 2018 NR. All rights reserved. We have all the intellectual property rights of this manual and its content. Except with the express authorization, copy or distribution to third parties is prohibited. We verify regularly the content of this manual. In future versions, some amendments will be necessary. But inevitably, there will be errors. Thank you to propose your advice for improvement. We reserve the rights of technical improvement without prior notice.

Trademarks NR® is a registered trademark of NR Electric Co., Ltd. Any unauthorized use is illegal. The other brands or product names are trademarks or registered trademarks of their respective owners. All products of NR Electric referenced in this document are registered trademarks of NR Electric.

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Preface

Warranty This product is covered by the standard NR 10-year warranty. For warranty details, please consult the manufacturer or agent for warranty information.

Declaration This content does not form part of a contract or of business relations, and nor does it change these. All the obligations of NR are stipulated in the contractual agreements. NR reserves the rights to revise this manual from time to time. The product documents of NR can be sent and received separately from other goods. Therefore, this manual is provided to ensure that the information of the product are perfectly understood by the recipient. Before performing a job, user must be familiar with the contents of this manual and carefully read the chapters.

Document Structure This manual is a comprehensive work covering the theories of protection, control, supervision, measurement, etc. and the structure & technical data of relevant hardware. Read the sections that pertain to your application to gain valuable information about using the PCS-915SC. To concentrate on the target sections of this manual as your job needs and responsibilities dictate. An overview of each manual section and section topics follows.

1 Introduction Introduces PCS-915SC features, summarizes functions and applications of the device.

2 Technical Data Lists device specifications, type tests, and ratings.

3 Protection Functions Describes the function of various protection elements, gives detailed specifics on protection scheme logic, provides the relevant logic diagrams.

4 Measurement Provides information on viewing fundamental and rms metering quantities for voltages and currents.

5 Supervision Describes self-supervision technique to help diagnose potential difficulties should these occur.

6 System Function Describes how to perform fundamental operations such as clock synchronization, communicating with the device, switching active setting group, checking relay status, reading event reports and SER (Sequential Events Recorder) records.

7 Hardware

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Describes the hardware of the PCS series device family and provides general information on the product structure and the modules technical data.

8 Settings Provides a list of all PCS-915SC settings and their ranges, unit, steps, defaults. The organization of the settings is similar to the settings organization in the device and in the PCS-Studio configuration tool.

Appendix A Glossary Describes the abbreviations adopted in this manual.

Disclaimer This document has been subjected to rigorous technical review before being published, but the deviations cannot be totally excluded. It is revised at regular intervals, and any modifications and amendments are included in the subsequent issues. In the case where errors are detected, the reader is requested to inform the manufacturer. The content of this manual has been compiled for information purposes only. Although NR has done its best to ensure that the document remains the most precise and the most up-to-date as possible, NR shall not assume any liability for defects and damage which result through use of the information contained herein.

Document Revision History PN: ZL_PCS-915SC_X_Technical Manual_EN_Overseas General_X Current version: R1.00 Corresponding Version Date Document

Software

R1.00

R1.00

R1.01

R1.00

2019-01-29

Description of change



Form the original manual.



The current settings conversion description is added;



The setting range of the system setting [Active_Grp] is modified;

2019-03-11 

The binary input [87B.BI_ExtBlk] and the alarm signal [87B.Alm_BI_ExtBlk] are deleted;



The logics of 87B, 50DZ, 50SOTF are modified.

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Preface

X

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1 Introduction

1 Introduction

1

Table of Contents 1.1 Application ....................................................................................................... 1-1 1.2 Functions ......................................................................................................... 1-1 1.3 Features ............................................................................................................ 1-4

List of Figures Figure 1.2-1 Functional diagram of PCS-915SC....................................................................... 1-1

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1 Introduction

1

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1 Introduction

1.1 Application PCS-915SC centralized busbar relay integrates busbar differential protection, bus coupler/section protection (includes overcurrent protection, switch-onto-fault protection, dead zone fault protection and breaker failure protection) and feeder protection (includes overcurrent protection, dead zone fault protection and breaker failure protection). With its flexibility and the powerful PCS-Studio configuration tool, PCS-915SC offers future-oriented busbar solutions with high investment security and low operating costs.

1.2 Functions The function diagram of this relay is shown in Figure 1.2-1.

} 3 CTs

87B

50BF

50DZ

FR

50/51

3 CTs

3 CTs * 52

* 52

Bay 1

Bay 2

……

* 52

}

Bay n *

Busbar 1

50SOTF

3 CTs 52

Busbar 2

Bus coupler

Figure 1.2-1 Functional diagram of PCS-915SC

1

Protection Functions

The functions of this relay include protective functions and auxiliary testing functions, and the functions of this relay are listed in the following tables. No.

Function

Remark



Steady-state

percentage

ANSI restraint

busbar

differential protection 1

Busbar differential protection

87B



DPFC percentage restraint busbar differential protection

2



Breaker failure protection (50BF)

50BF



Dead zone fault protection (50DZ)

50DZ

Bus coupler/section protection

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1 Introduction

1 3

4

Feeder protection



Switch-onto-fault protection (50SOTF)

50SOTF



Overcurrent protection (50/51)

50/51



Breaker failure protection (50BF)

50BF



Dead zone fault protection (50DZ)

50DZ



Overcurrent protection (50/51)

50/51



Dynamic busbar replica



CT circuit supervision



VT circuit supervision



Disconnector position alarm

Auxiliary function

DPFC is the abbreviation of “deviation of power frequency component”. When a fault occurs in the power system, the fault current consists of three parts: the pre-fault power frequency components, the power frequency variables during the fault and the transient variables during the fault. DPFC is the power frequency variables during the fault. 2

Measurement functions



Phase angle measurement



Differential current calculation



Sequence component calculation



Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision events, 256 control logs and 1024 device logs.



Disturbance recorder including 32 disturbance records with waveforms (The file format of disturbance recorder is compatible with international COMTRADE file.)

3

Supervision functions



Self diagnostic



Frequency supervision



DC power supply supervision



CT circuit supervision



VT circuit supervision



Disconnector supervision

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1 Introduction

4

Communication



Up to four 10Base-T/100Base-TX copper Ethernet ports using IEC 61850, DNP3.0 or IEC 60870-5-103 over TCP/IP



Up to four 100Base-FX optical Ethernet ports using IEC 61850, DNP3.0 or IEC 60870-5-103 over TCP/IP



Two RS-485 serial ports using IEC 60870-5-103, DNP3 or Modbus



One RS-485 serial port for clock synchronization



Support GOOSE communication module using IEC 61850-8-1 GOOSE



Full compatibility between IEC 61850 Editions 1 and 2



Redundancy protocols PRP and HSR



One RS-485 serial port for clock synchronization

5

User Interface



Friendly HMI interface with LCD, easy-to-use keypad aids simple navigation and set-point adjustment



4 Programmable operator pushbuttons with user-configurable labels



Up to 18 programmable target LEDs with user-configurable labels



1 RS-232 or RS-485 rear ports for printer



Language switchover—English+ selected language



Configuration tool—PCS-Studio

6

Additional functions



User programmable logic



Fault phase selection



System phase sequences rotation function (ABC or ACB)



Clock synchronization 

IRIG-B: IRIG-B via RS-485 differential level, TTL level or optical fiber interface



PPS: Pulse per second (PPS) via RS-485 differential level or binary input



PPM: Pulse per minute (PPM) via RS-485 differential level or binary input



IEEE1588: Clock message based on IEEE1588 via optical fiber interface

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1

1 Introduction

1 



SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network



SNTP (BC): Broadcast SNTP mode via Ethernet network



Message (IEC103/Modbus/DNP3.0): Clock messages through IEC103 protocol, Modbus protocol and DNP3.0 protocol

Cyber security 

NERC CIP



IEC 62351



IEC 62443



IEEE 1686

1.3 Features 

Unified software and hardware platform, comprehensive power grid solutions of protection, control, measurement and monitoring, easy to use and maintain.



High reliability and redundancy design for drive systems of the sampling circuit and the output circuit ensure that overall reliability of the device is high. Real-time sampling based on dual AD can mutually check and detect the potential abnormality in the sampling circuit in time. The control power supply of the output relay is independent with the control circuit of trigger signals, which can prevent from undesired operation caused by the abnormality of drive circuit of output relays.



Various function modules can satisfy various situations according to the different requirements of users. Flexible and universal logic programming, user-defined configuration of BI/BOs, buttons and LEDs and powerful analog programming are supported.



Modularized hardware design makes the device be easily upgraded or repaired by a qualified service person. It can be mixed with different I/O modules, with online self-check and monitoring function, and the device can be restored from abnormal operation only need to replace a single abnormal module.



Support memory check and error correction function, ensure high reliability and safety.



Support the internet communication protocol of native PRP/HSR and RSTP.



Fully compatible with IEC 61850 edition 1 & edition 2, support MMS service, IEC 62351 communication service, GOOSE communication in station level & process level, SV

1-4

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1 Introduction

communication with multi-sampling rate. 

Full comply with cyber security standards, including IEC62443, IEC62351, IEEE1686, NERC-CIP, support role based access control (RBAC), security audit, security encryption communication and security tool, improve the cyber security capability of devices.



Powerful COMTRADE fault and disturbance recording function is supported. The whole recording time is automatically configurable by the fault duration, which is convenient to fault analysis and replay. The recording sample rate is up to 9.6kHz.



Settable secondary rated current (1A/5A) and settable voltage threshold of binary input



Support flush mounting, semi-flush mounting, surface mounting, wall mounting and other mounting methods.



Cross screw IO, CT/VT terminals can support AWG12 specification connector and 4mm2 lead



Protection class of front side is up to IP54



PCS-Studio configuration tool is the application software on the user’s PC for the interface with PCS S series devices providing all the related functionality. It ranges from device configuration to full substation design of bay integration.



Support IEEE1588, IRIG-B clock synchronization



Support actual system phase sequence, either ABC or ACB, incorrect connection of actual phase sequence can automatically be verified and relevant protection functions can be blocked.



Equipped with high-speed large capacity output relay, its operation speed is less than 1ms and its break capacity is up to 10A. The real-time supervision for output drive circuit can detect the abnormality in advance.



Support setup up to 40 users and allow each user to own different password and access authority.



Applicable for single busbar, single bus with bus section, double busbar, double busbar with bus section, etc. busbar arrangement, and the busbar differential protection can connect up to 4 busbars and 32 bays.



Comprehensive functionality including phase segregated current differential protection, breaker failure protection, overcurrent protection and dead zone protection, etc.



The phase segregated differential protection adopts both of deviation of power frequency

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1

1 Introduction

component (DPFC) and steady-state component, that can guarantees fast and reliable performance during CT saturation. It can ensure no mal-operation of external fault and fast

1

operation of internal fault in the case of the correct transfer time of CT is no less than 3ms. 

With patented adaptive-weight anti-saturation algorithm and harmonic restrain algorithm, the DPFC differential protection operates fast and not affected by load current, the typical operation time is within 15ms.



Voltage blocking is an option for the current differential protection and breaker failure protection, which will improve the reliability of current differential protection and breaker failure protection.



With CT circuit supervision function, once CT circuit failure is detected, the user can choose discrimination zone or check zone differential protection blocking.



Both of phase segregated and three phase breaker failure binary inputs can be connected for breaker failure protection, users can choose whether or not blocked by the current criterion. The overcurrent element of breaker failure protection have been especially treated, the drop-off time of it is no more than 12ms.



Selectable IEC, ANSI inverse-time characteristic curves, also the curve can be defined by users and the inverse-time drop-off curve selection is supported.



With the disconnector position status monitor and memory function, the device can check the rationality of the memorized disconnector position status and automatically correct the error.



Users can disable the discrimination zone differential element by the external binary input during the busbar maintenance. Also the bay can be disabled by the external binary input when it is in maintenance.



LCD can display real-time main wiring diagram, the number of each bay, the state of each breaker and disconnector, current and power flow, etc.

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2 Technical Data

2 Technical Data Table of Contents 2.1 Electrical Specifications ................................................................................. 2-1 2.1.1 AC Current Input ................................................................................................................... 2-1 2.1.2 AC Voltage Input ................................................................................................................... 2-1 2.1.3 Power Supply ....................................................................................................................... 2-2 2.1.4 Binary Input .......................................................................................................................... 2-2 2.1.5 Binary Output........................................................................................................................ 2-3

2.2 Mechanical Specifications .............................................................................. 2-4 2.3 Ambient Temperature and Humidity Range .................................................. 2-5 2.4 Communication Port ....................................................................................... 2-5 2.4.1 EIA-485 Port ......................................................................................................................... 2-5 2.4.2 Ethernet Port ........................................................................................................................ 2-5 2.4.3 Optical Fiber Port ................................................................................................................. 2-5 2.4.4 Print Port ............................................................................................................................... 2-6 2.4.5 Clock Synchronization Port .................................................................................................. 2-6

2.5 Type Tests ........................................................................................................ 2-6 2.5.1 Environmental Tests ............................................................................................................. 2-6 2.5.2 Mechanical Tests .................................................................................................................. 2-6 2.5.3 Electrical Tests ...................................................................................................................... 2-7 2.5.4 Electromagnetic Compatibility .............................................................................................. 2-7

2.6 Certifications .................................................................................................... 2-9 2.7 Terminals .......................................................................................................... 2-9 2.7.1 Ring Ferrule .......................................................................................................................... 2-9 2.7.2 Pin Ferrule ............................................................................................................................ 2-9

2.8 Measurement Scope and Accuracy ............................................................... 2-9 2.9 Management Function................................................................................... 2-10 2.9.1 Clock Performance ............................................................................................................. 2-10 PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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2

2 Technical Data

2.9.2 Fault and Disturbance Recording....................................................................................... 2-10 2.9.3 Binary Input Signal ............................................................................................................. 2-10

2.10 Protective Functions ................................................................................... 2-10 2.10.1 Busbar Differential Protection (87B)................................................................................. 2-10

2

2.10.2 Dead Zone Fault Protection (50DZ) ................................................................................. 2-10 2.10.3 Switch-onto-fault Protection (50SOTF) ............................................................................ 2-10 2.10.4 Breaker Failure Protection (50BF) ................................................................................... 2-10 2.10.5 Phase Overcurrent Protection (50/51P) ........................................................................... 2-11 2.10.6 Earth Fault Protection (50/51G) ....................................................................................... 2-11

2-b

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2 Technical Data

2.1 Electrical Specifications

“System phase sequence”, which can be set by PCS-Studio, this setting informs the device of the actual system phase sequence, either ABC or ACB. CT and VT inputs on the device, labeled as A, B and C, must be connected to system phase A, B and C for correct operation.

2.1.1 AC Current Input Phase rotation

ABC or ACB

Nominal frequency (fn)

50Hz, 60Hz

Rated current (In)

1A/5A (settable)

Linear to

0.05In~40In

Thermal withstand -continuously

4In

-for 10s

30In

-for 1s

100In

-for half a cycle

250In

Burden

=1 &

& &

3

SET

[87B.Opt_CTS_Blk]=3

BI

@BBx.87B.BI_ExtBlk DS Alarm Block 87B_BBx

SIG

87B.On

SI G

87B.Alm_X_Off

SIG

@BBx.87B.Alm_X_Off

SIG

DPFC DIF_X

SI G

DPFC DIF_X BB1

SIG

DPFC_X current FD element

SI G

DPFC_X voltage FD element

SI G

SP DIF_X (K=0.2)

SIG

SP DIF_X BB1 (K=0.2)

EN

[87B.En_DPFC]

SI G

HM REL_X BB1

& @BBx.87B.Alm_C_Off

>=1

CT saturation detector 1

SIG

>=1

>=1

&

&

& 87B.Op_Trp@BB1_DPFC

&

>=1 & 500ms 0

SI G

SP DIF_X BB1

SI G

HM REL_X

&

& 87B.Op_Trp@BB1_Biased

>=1

>=1

&

Diff_BB1

500ms 0 SI G

SP DIF_X

SI G

87B.Valid

SIG

VCE_BBP Rls BB1

SIG

VCE_BBP Rls BBx

SIG

VCE_BBP Rls BBx & BBx is in service

EN

[87B.En_Dly_Biased]

SIG

SP DIF_X BBx

SI G

Δsi>ΔSI Float+0.5In

SI G

Δu>ΔUFloat+0.05Un

SET

ID>[87B.I_Pkp]

& 87B.Op_Trp@BC1

&

&

>=1

240ms 0

87B.Op_Dly1

480ms 0

87B.Op_Dly2

& 87B.FD

Figure 3.3-6 Logic of busbar differential protection

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3 Protection Functions

Where: X=A, B or C, means phase-A, phase-B or phase-C. Fail_Device: The device fails. The signal is issued with other specific alarm signals that will block the device. DS Alarm Block 87B_BBx: Bay n disconnector position alarm signal which will block busbar differential protection of BBx, please refer to Section 3.12.3.5. DPFC_X current FD element: please refer to Section 3.3.1.1. DPFC_X voltage FD element: please refer to Section 3.3.1.1.

3

DPFC DIF_X: phase-X DPFC percentage restraint differential element for check zone. DPFC DIF_X BB1: phase-X DPFC percentage restraint differential element for bus zone No.1. SP DIF_X: phase-X steady-state percentage restraint differential element for check zone. SP DIF_X BB1: phase-X steady-state percentage restraint differential element for bus zone No.1. SP DIF_X BBx: Steady-state percentage restraint differential element for any bus zone. HM REL_X: phase-X harmonic release element for check zone. HM REL_X BB1: phase-X harmonic release element for bus zone No.1. VCE_BBP Rls BB1: Busbar differential protection is not controlled by VCE_BBP or voltage controlled element of BBP of BB1 operates, please refer to Section 3.3.1.3 for details. VCE_BBP Rls BBx: Busbar differential protection is not controlled by VCE_BBP or voltage controlled element of BBP of any busbar operates, please refer to Section 3.3.1.3. VCE_BBP Rls BBx & BBx is in service: Busbar differential protection is not controlled by VCE_BBP or voltage controlled element of BBP of any energized busbar operates, please refer to Section 3.3.1.3. Diff_BB1: Differential element of BB1 (not controlled by voltage controlled element) operates. Δu>ΔUFloat+0.05Un， Δsi>ΔSIFloat+0.5In， ID> [87B.I_Pkp]: Please refer to Section 3.3.1.1. 87B.FD: Any FD element for busbar differential protection picks up. Different from BC, busbar differential protection operating to trip BS is not controlled by the voltage control element.

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3 Protection Functions

3

SI G

BBx is in service

SIG

Ua[@BC1.50DZ.I_Set]

SIG

Ic_BC1>[@BC1.50DZ.I_Set]

SIG

BBP trip brea ker side BB

&

& >=1

[50DZ.t_Ack_TrpCB] 0

BC1 current is excluded from busbar differential current calculation

& @BC1.50DZ.Op

BBP trip CT side BB

Figure 3.4-1 Logic of BC/BS dead zone fault protection when BC/BS breaker is closed

DIF_CZ: Check zone percentage restraint differential element. BBP trip breaker side BB: busbar differential protection operates to trip the circuit breaker on the breaker side busbar, i.e. the signal “87B.Op_Trp@BBx_Biased” or “87B.Op_Trp@BBx_DPFC” (x=1 or 2, it is decided by the CT installation location). BBP trip CT side BB: busbar differential protection operates to trip the circuit breaker on the CT side busbar, i.e. the signal “87B.Op_Trp@BBx_Biased” or “87B.Op_Trp@BBx_DPFC” (x=1 or 2, it is decided by the CT installation location).

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3 Protection Functions SIG

@BC1.BI_Cls

SIG

Ia_BC1[@Bayn.50DZ.I_Set]

SIG

Bayn.50DZ.Valid

@Bayn.50DZ.Pkp

>=1

& [Fdr.50DZ.t_Op] 0

@Bayn.50DZ.Op @Bayn.Op_TT

Figure 3.5-1 Logic of feeder dead zone fault protection when feeder breaker is closed

Where: @Bayn.50DZ.Pkp: FD element for feeder bay n dead zone fault protection picks up. TBD of bay n is closed: transfer bus disconnector (TBD) of bay n is closed.

3.5.5 Settings 

Dead Zone Fault Protection Setting

Access path: MainMenu  Settings  Protection Settings  50DZ Settings Table 3.5-2 Settings of feeder dead zone fault protection No.

Name

Range

Default value

Unit

Step

1

Fdr.50DZ.t_Op

0.000~0.400s

0.020

s

0.001

2

50DZ.t_Ack_TrpCB

0.000~10.000s

0.100

s

0.001

3-38

Remark

Time delay for feeder dead zone fault protection, 20ms is recommended. The

breaker

open

position

confirmation time for feeder dead

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3 Protection Functions zone

fault

protection

condition that

feeder

under

the

breaker

is

closed, 100ms is recommended. Current setting for feeder dead zone 3

Bayn.50DZ.I_Set

0.05In ~20.00In

0.100

A

0.001

fault protection of bay n, 0.1In is recommended. Logic setting of feeder dead zone fault protection of bay n

4

Bayn.50DZ.En

Disabled Enabled

Disabled

1: Enabling feeder dead zone fault protection of bay n 0: Disabling feeder dead zone fault protection of bay n

All the current settings in above table are converted according to the CT ratio of each bay.

3.6 BC/BS Switch-onto-fault (SOTF) Protection (50SOTF)

The bay label of displayed alarm signals, tripping signals, binary input signals, settings and sampled values related with each bay will change with the corresponding label settings. In this section, “@Bayn” is used to refer to the label setting of corresponding bay. For a bus coupler bay, “@BCy” is also used to refer to the label setting of corresponding bus coupler. For a bus section bay, “@BSz” is also used to refer to the label setting of corresponding bus section.

3.6.1 Function Description When a busbar is first energized via a BC/BS after maintenance or newly installed, the BC/BS SOTF protection can make the device trip the BC/BS immediately when it is closed on to a fault. BC/BS SOTF protection is not controlled by voltage controlled element. SOTF protection is enabled if the following conditions are met. 1.

The BC/BS breaker is in open position

2.

BC/BS three phase currents are smaller than 0.04In.

3.

Any of the two connected busbars is out of service.

If any of the following conditions is met, SOTF protection will be blocked after 300ms

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3 Protection Functions

1.

The position status of BC/BS breaker changes from open to closed.

2.

BC current changes from being smaller than 0.04In to being larger than 0.04In.

3.

Both connected busbars are in service.

BC/BS SOTF protection will operate to trip BC/BS breaker without controlled by voltage controlled element.

3.6.2 Function Block Diagram 50SOTF

3

Ia_Bayn, Ib_Bayn, Ic_Bayn Ua_BBx, Ub_BBx, Uc_BBx @BCy.BI_52a

@BCy.50SOTF.Op_Trp @BCy.50SOTF.Alm_Pkp

@BCy.BI_52b

@BCy.50SOTF.Block @BCy.50SOTF.Enable

For a BS, Just use “BSz” to instead of “BCy” in the above function block diagram.

3.6.3 I/O Signal Table 3.6-1 Input/Output signals of BC/BS SOTF protection No.

Input Signal

Description

1

@BCy.50SOTF.Enable

Binary input of enabling SOTF of BCy

2

@BSz.50SOTF.Enable

Binary input of enabling SOTF of BSz

3

@BCy.50SOTF.Block

Binary input of disabling SOTF of BCy

4

@BSz.50SOTF.Block

Binary input of disabling SOTF of BSz

No.

Output Signal

Description

1

@BCy.50SOTF.Op_Trp

SOTF protection of BCy operates

2

@BSz.50SOTF.Op_Trp

SOTF protection of BSz operates

3

@BCy.50SOTF.Alm_Pkp

4

@BSz.50SOTF.Alm_Pkp

Alarm signal indicating that FD element for SOTF protection of BCy picks up for over 10s Alarm signal indicating that FD element for SOTF protection of BSz picks up for over 10s

3.6.4 Logic The logic of BC/BS SOTF protection is shown as follows (Takes BC1 in Figure 3.2-6 as an example). 3-40

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3 Protection Functions

&

EN

[@BC1.50SOTF.En]

SIG

@BC1.50SOTF.Enable

SIG

@BC1.50SOTF.Block

SIG

Fail_Device

@BC1.50SOTF.On

& @BC1.50SOTF.Blocked

≥1

& @BC1.50SOTF.Valid

SIG

Bre ake r of BC1 is o pen

SIG

BB1 is in service

SIG

BB2 is in service

SIG

Ia_BC1>0.04In

3 &

& 0 300ms

SIG

Ib_BC1>0.04In

SIG

Ic_BC1>0.04In

SIG

SET

&

& & @BC1.50SOTF.Op_Trp

>=1

@BC1.50SOTF.Vali d

Ia_BC1>[@BC1.50SOTF.I_Set]

SET

Ib_BC1>[@BC1.50SOTF.I_Set]

SET

Ic_BC1>[@BC1.50SOTF.I_Set]

& @BC1.50SOTF.Pkp

>=1

Figure 3.6-1 Logic of SOTF protection

Where: @BC1.50SOTF.Pkp: FD element for BC/BS SOTF protection picks up BBx is in service: Please refer to Figure 3.11-1.

3.6.5 Settings 

Switch-onto-fault Protection Setting

Access path: MainMenu  Settings  Protection Settings  SOTF Settings Table 3.6-2 Settings of switch-onto-fault protection No.

1

2

Name

Range

Bayn.50SOTF.I_Set

0.05In ~20.00In

Bayn.50SOTF.En

Disabled Enabled

Default value 1.000

Unit

Step

A

0.001

Remark

Current setting for BC/BS SOTF protection Logic setting of SOTF protection of

Disabled

bay n 1: Enabling SOTF protection of bay n

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3 Protection Functions (only for BC/BS bay) 0: Disabling SOTF protection of bay n (only for BC/BS bay)

All the current settings in above table are converted according to the CT ratio of each bay.

3

3.7 Breaker Failure Protection (50BF)

The bay label of displayed alarm signals, tripping signals, binary input signals, settings and sampled values related with each bay will change with the corresponding label settings. In this section, “@BBx” is used to refer to the label setting of corresponding busbar and “@Bayn” is used to refer to the label setting of corresponding bay. For a bus coupler bay, “@BCy” is also used to refer to the label setting of corresponding bus coupler. For a bus section bay, “@BSz” is also used to refer to the label setting of corresponding bus section. When the bay protection or the busbar protection operates to trip the breaker of a bay, but the breaker fails, the breaker failure protection of the bay needs to be initiated. When the breaker failure protection operates, it will re-trip the circuit breaker of the bay with the first time delay, then it will trip all the breakers on the busbar that connected to the bay with the second time delay, and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. Users can choose whether breaker failure protection is blocked by the current criterion or the voltage control element. Breaker failure protection of each bay can be enabled or disabled independently, the breaker failure current setting and the corresponding time delay of breaker failure protection of each bay can be set independently.

3.7.1 Function Description 3.7.1.1 Current Criterion of Breaker Failure Protection 1.

Phase current criterion

Phase current is greater than the setting [Bayn.50BF.I_Set] The phase current criterion is always enabled, but it can be blocked due to residual current if the logic setting [Bayn.50BF.En_3I0_1P] is set as “1”; or it will be blocked due to negative-sequence current if the logic setting [Bayn.50BF.En_I2_1P] is set as “1”. 2.

3-42

Residual current criterion

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3 Protection Functions

Residual current is greater than the setting [Bayn.50BF.3I0_Set] The logic setting [Bayn.50BF.En_3I0] is used to enable or disable the residual current criterion. 3.

Negative-sequence current criterion

Negative-sequence current is greater than the setting [Bayn.50BF.I2_Set] The logic setting [Bayn.50BF.En_I2] is used to enable or disable the negative-sequence current criterion.

When calculating all the current setting of each bay, the primary current should be converted to the secondary value according to the reference CT ratio instead of the actual CT ratio of each bay. 3.7.1.2 Voltage Control Element of Breaker Failure Protection (VCE_BFP) Voltage control element is used as an auxiliary condition. The criteria are: UP≤[50BF.VCE.U_Set]

Equation 3.7-1

3U0≥[50BF.VCE.3U0_Set]

Equation 3.7-2

U2≥[50BF.VCE.U2_Set]

Equation 3.7-3

If any of above equation is met, the voltage blocking of breaker failure protection will be released. Where: UP: Phase voltage 3U0: Residual voltage U2: Negative-sequence voltage [50BF.VCE.U_Set]: Phase voltage setting for releasing the voltage blocking of breaker failure protection [50BF.VCE.3U0_Set]: Residual voltage setting for releasing the voltage blocking of breaker failure protection [50BF.VCE.U2_Set]: Negative-sequence voltage setting for releasing the voltage blocking of breaker failure protection When the protective device is applied to an unearthed system, i.e. the system setting [Opt_UnearthedSys_Mode] is set as “1”, the criteria of voltage control element will change.

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3 Protection Functions

UPP ≤ 3 [50BF.VCE.U_Set]

Equation 3.7-4

U2 ≥[50BF.VCE.U2_Set]

Equation 3.7-5

Where: UPP: Phase-to-phase voltage U2: Negative-sequence voltage

3

[50BF.VCE.U_Set]: Phase-to-ground voltage setting for releasing the voltage blocking of breaker failure protection [50BF.VCE.U2_Set]: Negative voltage setting for releasing the voltage blocking of breaker failure protection VCE_BFP will be controlled by the logic setting [50BF.VCE.En], if it is set as “0”, VCE_BFP will be disabled and bay breaker failure protection will not controlled by VCE_BFP If voltage concerned function is disabled, VCE_BFP will quit and related settings will be hidden, bay breaker failure protection will not controlled by voltage element. Only if voltage concerned function is enabled and the logic setting [50BF.VCE.En] is set as “1”, VCE_BFP is enabled. A binary input for releasing voltage control element for breaker failure protection [50BF.BI_RlsVCE] is provided. If the logic setting [Bayn.50BF.En_BI_RlsVCE] is set as “1” and the releasing voltage control element binary input “50BF.BI_RlsVCE” is energized, the voltage blocking for breaker failure protection of bay n will be released. If VCE_BFP or VCE_BBP of BBx operates for over 3s (i.e. the voltage blocking of breaker failure protection or busbar differential protection is released for over 3s), an alarm signal “@BBx.Alm_VCE” will be issued. 3.7.1.3 Circuit Breaker Error Binary Input Circuit breaker error binary input is generally used to connect the breaker control circuit failure binary input, or tripping pressure low binary input etc. If breaker failure protection is initiated and the circuit breaker error binary input is “0”, breaker failure protection will operate to re-trip the circuit breaker of the bay with the time delay of [Bayn.50BF.t_ReTrp], then it will trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. If breaker failure protection is initiated and the circuit breaker error binary input is “1”, breaker failure protection will operate to trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB_CBErr], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. 3-44

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3 Protection Functions

3.7.1.4 Initiating Element of Breaker Failure Protection The initiating elements of breaker failure protection of each bay include the following: 



Other protection of the device operates to initiate breaker failure protection 1.

BBP operates to trip bay n (controlled by the logic setting [87B.En_Init50BF])

2.

Overcurrent protection [50/51.En_Init50BF])

3.

BC/BS switch-onto-fault protection operates to trip the BC/BS

of

bay

n

operates

(controlled

by the

logic

setting

3

External binary input initiate breaker failure protection 1.

Phase-segregated breaker failure initiating (BFI) binary input “@Bayn.BI_A_BFI”: The binary input for initiating BFP of phase A of bay n, it corresponds to the signal that external device operates to trip phase-A “@Bayn.BI_B_BFI”: The binary input for initiating BFP of phase B of bay n, it corresponds to the signal that external device operates to trip phase-B “@Bayn.BI_C_BFI”: The binary input for initiating BFP of phase C of bay n, it corresponds to the signal that external device operates to trip phase-C emote end of a line or inter-trip the breakers on other sides of a main-transformer.

2.

Three-phase breaker failure initiating (BFI) binary input “@Bayn.BI_BFI”: The binary input for three-phase tripping to initiate BFP, it is mainly used in the case where the bay breaker has no phase-segregated tripping contacts, such as a transformer bay.

3.

Three-phase breaker failure initiating (BFI) binary input that is not controlled by current criterion “@Bayn.BI_ExTrp_WOI_BFI”: The three-phase breaker failure initiating binary input that is not controlled by current criterion, it is mainly used for mechanical protection operates to initiate BFP. This binary input is not controlled by the current criterion, but it is controlled by the breaker position of the bay.

After breaker failure protection is initiated, it will be widened for 500ms. If the external breaker failure initiate binary input is energized for over 10s, the BFI binary input alarm signal “@Bayn.Alm_ExTrp_WOI_BFI” will be issued, and the external binary input initiating breaker failure protection function will be exited at the same time. 3.7.1.5 Operating Element of Breaker Failure Protection 

Other protection of the device operates to initiate breaker failure protection When other protection of the device operates to trip the bay, if the current criterion of breaker failure protection is met, and the voltage blocking for breaker failure protection is released,

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3 Protection Functions

the breaker failure protection will operates to re-trip the circuit breaker of the bay with the time delay of [Bayn.50BF.t_ReTrp], then it will trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. When breaker failure protection is initiated, if the circuit breaker error binary input is “1” at the same time, breaker failure protection will operate to trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB_CBErr], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer.

3



External binary input initiate breaker failure protection 1.

Phase-segregated breaker failure initiating (BFI) binary input When any phase-segregated BFI binary input is energized, if the current criterion of breaker failure protection is met, and the voltage blocking for breaker failure protection is released, the breaker failure protection will operates to re-trip the circuit breaker of the bay with the time delay of [Bayn.50BF.t_ReTrp], then it will trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. If the logic setting [Bayn.50BF.En_TrpBB_Ext] is set as “1”, when any phase-segregated BFI binary input is energized, and the voltage blocking for breaker failure protection is released, the breaker failure protection will operates to trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB_Ext], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. When breaker failure protection is initiated, if the circuit breaker error binary input is “1” at the same time, breaker failure protection will operate to trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB_CBErr], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer.

2.

Three-phase breaker failure initiating (BFI) binary input When three-phase BFI binary input is energized, if the current criterion of breaker failure protection is met, and the voltage blocking for breaker failure protection is released, the breaker failure protection will operates to re-trip the circuit breaker of the bay with the time delay of [Bayn.50BF.t_ReTrp], then it will trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. If the logic setting [Bayn.50BF.En_TrpBB_Ext] is set as “1”, when three-phase BFI binary input is energized, and the voltage blocking for breaker failure protection is released, the breaker failure protection will operates to trip all the breakers on the busbar that

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3 Protection Functions

connected to the bay with the time delay of [Bayn.50BF.t_TrpBB_Ext], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. When breaker failure protection is initiated, if the circuit breaker error binary input is “1” at the same time, breaker failure protection will operate to trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB_CBErr], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. 3.

Three-phase breaker failure initiating (BFI) binary input that is not controlled by current criterion When the three-phase BFI binary input that is not controlled by current criterion is energized, and the breaker of the bay is closed, the breaker failure protection will operates to re-trip the circuit breaker of the bay with the time delay of [Bayn.50BF.t_ReTrp], then it will trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer. When breaker failure protection is initiated, if the circuit breaker error binary input is “1” at the same time, breaker failure protection will operate to trip all the breakers on the busbar that connected to the bay with the time delay of [Bayn.50BF.t_TrpBB_CBErr], and transfer trip the breaker of the remote end of a line or inter-trip the breakers on other sides of a main-transformer.

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3 Protection Functions

3.7.2 Function Block Diagram Feeder 50BF Ia_Bayn, Ib_Bayn, Ic_Bayn

@Bayn.50BF.Op_ReTrp

Ua_BBx, Ub_BBx, Uc_BBx

@Bayn.50BF.Op_TrpBBx

@Bayn.BI_89b_@BBx

50BF.Op

@Bayn.50/51P.Op_Trp

3

50BF.Op_Trp@BBx

@Bayn.BI_89a_@BBx

@Bayn.50BF.Op_TrpBB

@Bayn.50/51G.Op_Trp

@Bayn.Op_TT

@BCy.50SOTF.Op_Trp

@Bayn.Alm_BI_BFI

87B.Op_Trp@BBx_Biased @Bayn.Alm_ExTrp_WOI_BFI 87B.Op_Trp@BBx_DPFC

50BF.Alm_BI_RlsVCE

@Bayn.BI_BFI

50BF.Alm_Pkp

@Bayn.BI_A_BFI

50BF.Alm_Off

@Bayn.BI_B_BFI @Bayn.BI_C_BFI @Bayn.BI_ExTrp_WOI_BFI

@Bayn.50BF.BI_CBErr 50BF.BI_RlsVCE @Bayn.BI_52a @Bayn.BI_52b @Bayn.50BF.Enable @Bayn.50BF.Block

3.7.3 I/O Signal Table 3.7-1 Input/Output signals of breaker failure protection No.

Input Signal

Description

1

@Bayn.50BF.Enable

Binary input of enabling breaker failure protection of bay n

2

@Bayn.50BF.Block

Binary input of disabling breaker failure protection of bay n

3

@Bayn.50/51P.Op_Trp

Phase overcurrent protection of bay n operates

4

@Bayn.50/51G.Op_Trp

Ground overcurrent protection of bay n operates

5

87B.Op_Trp@BBx_Biased

Steady-state busbar differential protection operates to trip BBx

6

87B.Op_Trp@BBx_DPFC

DPFC busbar differential protection operates to trip BBx

7

@BCy.50SOTF.Op_Trp

SOTF protection of BCy operates

8

@BSz.50SOTF.Op_Trp

SOTF protection of BSz operates

9

@Bayn.BI_BFI

Three-phase BFI binary input of bay n

10

@Bayn.BI_A_BFI

Phase-A BFI binary input of bay n

11

@Bayn.BI_B_BFI

Phase-B BFI binary input of bay n

12

@Bayn.BI_C_BFI

Phase-C BFI binary input of bay n

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Input Signal

13

@Bayn.BI_89a_@BBx

14

@Bayn.BI_89b_@BBx

15

@Bayn.BI_ExTrp_WOI_BFI

16

@Bayn.50BF.BI_CBErr

Description Normally open auxiliary contact of BBx disconnector of bay n Normally closed auxiliary contact of BBx disconnector of bay n, it is used if disconnector dual-position auxiliary contacts are adopted The external BFI binary input of bay n which is not controlled by the current criterion Circuit breaker error binary input of bay n, this binary input is generally used to connect the breaker control circuit failure binary input, or tripping pressure low binary input etc.

17

@Bayn.BI_52a

18

@Bayn.BI_52b

19

50BF.BI_RlsVCE

No.

Normally open auxiliary contact of the circuit breaker of bay n. The input signal is only configured if dual-position BI for circuit breaker is enabled. Normally closed auxiliary contact of the circuit breaker of bay n. Binary input of releasing voltage controlled element of breaker failure protection

Output Signal

Description

1

@Bayn.50BF.Op_ReTrp

BFP of bay n operates to re-trip the feeder breaker

2

50BF.Op_Trp@BBx

BFP operates to trip BBx

3

@Bayn.50BF.Op_Trp@BBx

BFP of bay n operates to trip BBx

4

@Bayn.50BF.Op_TrpBB

BFP of bay n operates to trip busbar zone

5

50BF.Op

BC/BS BFP or feeder BFP operates

6

@Bayn.Op_TT

DZP or BFP of bay n operates to initiate transfer trip to remote circuit breaker Binary input of initiating contact of BFP of bay n (@Bayn.BI_A_BFI,

7

@Bayn.Alm_BI_BFI

@Bayn.BI_B_BFI, @Bayn.BI_C_BFI or @Bayn.BI_BFI) is energized for over 10s.

8

@Bayn.Alm_ExTrp_WOI_BFI

9

50BF.Alm_BI_RlsVCE

10

50BF.Alm_Pkp

The external BFI binary input of bay n which is not controlled by the current criterion is energized for over 10s. Binary input of releasing voltage controlled element of breaker failure protection is energized for over 10s. Alarm signal indicating that FD element for BFP of any bay picks up for over 10s Alarm signal indicating feeder BFP is disabled. If the logic setting [50BF.En_Alm_Off] is set as “1”, once feeder BFP is disabled (feeder BFP

11

50BF.Alm_Off

can be disabled by the corresponding enabling binary input, function link or enabling logic setting), the alarm signal indicating feeder BFP is disabled will be issued

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3 Protection Functions

3.7.4 Logic EN

[Bayn.50BF.En]

BI

50BF.BI_Blk

BI

50BF.BI_En

& Bayn.50BF is enabled

& >=1

SIG

@Bayn.Alm_BI_BFI

SIG

@Bayn.Alm_ExTrp_WOI_BFI

SIG

Fail_Device

Bayn.50BF is blocked

& Bayn.50BF.Valid

3

EN

[87B.En_Init50BF]

SIG

BBP operates to trip bay n

EN

[50/51.En_Init50BF]

SIG

@Bayn.50/51.Op_Trp

SIG

@BCy.50SOTF.Op_Trp

SET

Ia_Bayn>[Bayn.50BF.I_Set]

SET

Ib_Bayn>[Bayn.50BF.I_Set]

SET

Ic_Bayn>[Bayn.50BF.I_Set]

EN

[Bayn.50BF.En_3I0]

SET

3I0_Bayn>[Bayn.50BF.3I0_Set]

&

&

>=1

>=1

& &

>=1

& @Bayn.50BF.Op_Trp@BBx

&

@Bayn.Op_TT

& [Bayn.50BF.t_TrpBB ] 0

EN

[Bayn.50BF.En_I2]

SET

I2_Bayn>[Bayn.50BF.I2_Set]

SIG

@Bayn.50BF is enabled

SIG

VCE_BFP Rls BBx

SIG

VCE_BFP is disabled

&

50BF.Op_Trp@BBx

&

BI

50BF.BI_RlsVCE

EN

Bayn.50BF.En_BI_RlsVCE

SIG

[Bayn.50BF.t_ReTrp] 0

@Bayn.50BF.BI_CBErr

EN

[50BF.En_ReTrp]

@Bayn.50BF.Op_ReTrp

& &

@Bayn.50BF.Op_Trp@BBx

@Bayn.Op_TT

&

Disconnector position of BBx

BI

3-50

>=1

[Bayn.50BF.t_TrpBB_CBErr]

0

50BF.Op_Trp@BBx

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

3 Protection Functions

BI

&

@Bayn.BI_BFI

>=1

SET

BI SET

BI SET

&

Ia_Bayn>[Bayn.50BF.I_Set]

@Bayn.BI_A_BFI

>=1

&

Ib_Bayn>[Bayn.50BF.I_Set]

@Bayn.BI_B_BFI

&

Ic_Bayn>[Bayn.50BF.I_Set]

BI

@Bayn.BI_C_BFI

EN

[Bayn.50BF.En_3I0_1P]

SET

3I0_Bayn>[Bayn.50BF.3I0_Set]

EN

[Bayn.50BF.En_I2_1P]

SET

I2_Bayn>[Bayn.50BF.I2_Set]

3

>=1 &

>=1 >=1

& >=1

BI

@Bayn.BI_BFI

BI

@Bayn.BI_A_BFI

BI

@Bayn.BI_B_BFI

BI

@Bayn.BI_C_BFI

EN

[Bayn.50BF.En_3I0]

& & @Bayn.50BF.Op_Trp@BBx

& >=1

@Bayn.Op_TT

&

&

[Bayn.50BF.t_TrpBB ] 0

&

50BF.Op_Trp@BBx

& >=1

@Bayn.50BF.Op_Trp@BBx

&

&

@Bayn.Op_TT

& [Bayn.50BF.t_TrpBB_Ext]

SET

3I0_Bayn>[Bayn.50BF.3I0_Set]

EN

[Bayn.50BF.En_I2]

SET

I2_Bayn>[Bayn.50BF.I2_Set]

EN

Bayn.50BF.En_TrpBB_Ext

SIG

@Bayn.Alm_BI_BFI

SIG

@Bayn.50BF is enabled

0

50BF.Op_Trp@BBx

&

& & [Bayn.50BF.t_ReTrp] 0

@Bayn.50BF.Op_Trp@BBx

>=1

@Bayn.Op_TT

& [Bayn.50BF.t_TrpBB_CBErr]

SIG

VCE_BFP Rls BBx

SIG

VCE_BFP is disabled

BI

50BF.BI_RlsVCE

EN

Bayn.50BF.En_BI_RlsVCE

SIG

Disconnect or position of BBx

EN

[50BF.En_ReTrp]

BI

@Bayn.50BF.BI_CBErr

BI

@Bayn.50BF.Op_ReTrp

>=1

0

50BF.Op_Trp@BBx

&

@Bayn.BI_ExTrp_WOI_BFI

&

& &

SIG

@Bayn.BI_52b=0

SIG

@Bayn.Alm_ExTrp_WOI_BFI

SIG

@Bayn.50BF is enabled

SIG

Disconnector position of BBx

@Bayn.50BF.Op_Trp@BBx

&

@Bayn.Op_TT

& [Bayn.50BF.t_TrpBB ] 0

50BF.Op_Trp@BBx @Bayn.50BF.Op_Trp@BBx @Bayn.Op_TT

& [Bayn.50BF.t_TrpBB_CBErr] BI

0

50BF.Op_Trp@BBx

@Bayn.50BF.BI_CBErr

& [Bayn.50BF.t_ReTrp] 0 EN

@Bayn.50BF.Op_ReTrp

[50BF.En_ReTrp]

Figure 3.7-1 Logic of breaker failure protection PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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3 Protection Functions

Where: @Bayn.50/51.Op_Trp: phase overcurrent protection or ground overcurrent protection of bay n operates. @Bayn.50BF is enabled: breaker failure protection is enabled (the corresponding enabling binary input “@Bayn.50BF.Enable” is energized, the corresponding disabling binary input “@Bayn.50BF.Block” is de-energized and the corresponding enabling logic setting [@Bayn.50BF.En] is set as “1”). VCE_BFP Rls BBx: Voltage controlled element for BFP of any connected BBx.

3

VCE_BFP is disabled: voltage concerned function is disabled or the logic setting [50BF.VCE.En] is set as “0”. Disconnector position of BBx: which busbar the bay is connected to (according to disconnector position of the bay). @Bayn.50BF.FD: FD element for feeder bay n BFP picks up. 3I0_Bayn: The residual current of bay n. I2_Bayn: The negative-sequence current of bay n. Ia_Bayn: The phase A current of bay n. Ib_Bayn: The phase B current of bay n. Ic_Bayn: The phase C current of bay n.

3.7.5 Settings 

Breaker Failure Protection Setting

Access path: MainMenu  Settings  Protection Settings  BFP Settings Table 3.7-2 Settings of breaker failure protection No.

1

Name

50BF.VCE.U_Set

Default

Range

value

Unit

Remark

Step Phase

0~100.000

40.000

V

V

0.001

voltage

50BF.VCE.3U0_Set

for

releasing the voltage blocking of breaker failure protection. Residual

2

setting

0~63.000V

6.000

V

0.001

voltage

setting

for

releasing the voltage blocking of breaker failure protection. Negative-sequence

3

50BF.VCE.U2_Set

0~63.000V

4.000

V

0.001

voltage

setting for releasing the voltage blocking

of

breaker

failure

protection. 4

3-52

Bayn.50BF.I_Set

0~20.00In

1.000

A

0.001

Phase current setting of breaker

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

3 Protection Functions No.

Name

Range

Default value

Unit

Remark

Step

failure protection of bay n.

5

6

Bayn.50BF.3I0_Set

Bayn.50BF.I2_Set

0.05In~20. 00In

0.05In~20. 00In

Residual 0.500

A

0.001

current

setting

of

breaker failure protection of bay n. Negative-sequence

0.500

A

0.001

setting

of

breaker

current failure

protection of bay n. Time delay for breaker failure

7

Bayn.50BF.t_ReTrp

0~10.000s

0.100

s

0.001

protection of bay n operates to re-trip breaker. Time delay for breaker failure protection of bay n operates to

8

Bayn.50BF.t_TrpBB

0~10.000s

0.250

s

0.001

trip all the breakers on the busbar that connected to the bay. Time delay for breaker failure protection of bay n operates to trip all the breakers on the busbar that connected to the bay

9

Bayn.50BF.t_TrpBB_Ext

0~10.000s

0.020

s

0.001

when the logic setting

[Bayn.50BF.En_TrpBB_Ext]

is

set as “1” and the breaker failure protection

is

initiated

phase-segregated three-phase

breaker

by or

failure

initiating binary input. Time delay for breaker failure protection of bay n operates to 10

Bayn.50BF.t_TrpBB_CBErr

0~10.000s

0.020

s

0.001

trip all the breakers on the busbar that connected to the bay in case of the bay breaker is abnormal. Logic setting for enable or

11

Bayn.50BF.En

Disabled Enabled

disable Enabled

breaker

failure

protection of bay n 1: Enable 0: Disable

12

50BF.En_ReTrp

Disabled Enabled

Logic setting for enable or Enabled

disable re-tripping function of breaker failure protection of bay

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3-53

3

3 Protection Functions No.

Name

Range

Default value

Unit

Remark

Step n 1: Enable 0: Disable

Logic setting for enable or disable residual current criterion 13

Bayn.50BF.En_3I0

Disabled Enabled

Disabled

of breaker failure protection of bay n 1: Enable

3

0: Disable Logic setting for enable or disable 14

Bayn.50BF.En_I2

Disabled Enabled

Disabled

negative-sequence

current

criterion

of

breaker

failure protection of bay n 1: Enable 0: Disable 1: The phase current criterion will be blocked by residual

15

Bayn.50BF.En_3I0_1P

Disabled Enabled

Disabled

current criterion 0: The phase current criterion will not be blocked by residual current criterion 1: The phase current criterion will

be

blocked

negative-sequence 16

Bayn.50BF.En_I2_1P

Disabled Enabled

Disabled

by current

criterion 0: The phase current criterion will

not

be

blocked

negative-sequence

by

current

criterion Logic setting for enable or disable initiating the breaker failure

protection

of

bay

n

externally. If it is set as “1”, and the breaker failure protection is 17

Bayn.50BF.En_TrpBB_Ext

Disabled Enabled

Disabled

initiated by phase-segregated or three-phase

breaker

failure

initiating binary input, breaker failure

protection

of

bay

n

operates to trip all the breakers on the busbar that connected to the bay with the time delay of 3-54

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

3 Protection Functions No.

Name

Range

Default value

Unit

Remark

Step

[Bayn.50BF.t_TrpBB_Ext]. 1: the binary input for releasing voltage controlled element of breaker failure protection of bay 18

Bayn.50BF.En_BI_RlsVCE

Disabled Enabled

Disabled

n is enabled 0: the binary input for releasing voltage controlled element of breaker failure protection of bay n is disabled 1: breaker failure protection is controlled by voltage control

19

Disabled

50BF.VCE.En

Enabled

Enabled

element 0: breaker failure protection is not controlled by voltage control element Logic

setting

of

enabling/disabling the external BFI

binary

input

[@Bayn.BI_ExTrp_WOI_BFI]. 0: the external BFI binary input 20

Disabled

50BF.En_CB_Ctrl

Enabled

[@Bayn.BI_ExTrp_WOI_BFI] is Disabled

disabled; 1: the external BFI binary input [@Bayn.BI_ExTrp_WOI_BFI] is enabled, and it will be blocked by the normally closed contact, but not controlled by the current criterion. 1: Enabling the alarm function when breaker failure initiating binary input is energized for

21

Disabled

50BF.En_Alm_Init

Enabled

Disabled

over 10s. 0: Disabling the alarm function when breaker failure initiating binary input is energized for over 10s.

All the current settings in above table are converted according to the CT ratio of each bay. PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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3

3 Protection Functions

3.8 Phase Overcurrent Protection

The bay label of displayed alarm signals, tripping signals, binary input signals, settings and sampled values related with each bay will change with the corresponding label settings. In this section, “@Bayn” is used to refer to the label setting of corresponding bay.

3

Phase overcurrent protection is the most widely used type of protection element in power systems. It can be used as the main protection of the feeder, and can also be used as the backup protection for power equipment such as transformers, reactors, and motors. When a fault occurs in the system, a fault current will be generated and the phase overcurrent protection can reflect the increase of the fault current.

3.8.1 Function Description The device can provide two stages of phase overcurrent protection with independent logic. Each stage can be independently set as definite-time characteristics or inverse-time characteristics. The dropout characteristics can be set as immediate dropout, definite-time dropout or inverse-time dropout. The phase overcurrent protection picks up when the current exceeds the current threshold value, and operates after a certain time delay, once the fault disappears, the phase overcurrent protection will dropout. Phase overcurrent protection can be enabled or disabled via the settings or binary input signals, for some specific applications, overcurrent protection needs to be blocked by the external signal, so the device provides a function block input signal to be used to block overcurrent protection. The enabling and blocking logic of phase overcurrent protection is shown in the figure below: EN

@Bayn.50/51Px.En

SIG

@Bayn.50/51Px.Enable

SIG

@Bayn.50/51Px.Block

SIG

Fail_Device

& @Bayn.50/51Px.On

& @Bayn.50/51Px.Blocked

≥1

& @Bayn.50/51Px.Valid

Figure 3.8-1 The enabling and blocking logic of phase overcurrent protection

The logic diagram of the fault detector element of phase overcurrent protection is as follows:

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3 Protection Functions

SET

Ia>0.95*[@Bayn.50/51Px.I_Set]

SET

Ib>0.95*[@Bayn.50/51Px.I_Set]

SET

Ic>0.95*[@Bayn.50/51Px.I_Set]

SIG

@Bayn.50/51Px.On

SIG

@Bayn.50/51Px.Valid

≥1

& 0

500ms

& @Bayn.50/51Px.Pkp

Figure 3.8-2 Logic diagram of the fault detector element of phase overcurrent protection

3.8.1.1 Operating Characteristic Phase overcurrent protection can operate without time delay or operate with a definite-time limit, it can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3 and ANSI C37.112 standards. Phase overcurrent protection can support definite-time limit, IEC & ANSI standard reverse time limit and user-defined inverse-time limit, users can select the wanted operating curve by the setting [Bayn.50/51Px.Opt_Curve] (x=1~2), the relationship between the value of the setting and the curve is shown in the table below. Bayn.50/51Px.Opt_Curve

Time Characteristic

k

α

c

tr

ANSIE

ANSI Extremely Inverse

28.2

2.0

0.1217

29.1

ANSIV

ANSI Very inverse

19.61

2.0

0.491

21.6

ANSIN

ANSI Normal Inverse

0.0086

0.02

0.0185

0.46

ANSIM

ANSI Moderately Inverse

0.0515

0.02

0.114

4.85

ANSIDefTime

ANSI Definite Time

-

-

-

-

ANSILTE

ANSI Long Time Extremely Inverse

64.07

2.0

0.25

30

ANSILTV

ANSI Long Time Very Inverse

28.55

2.0

0.712

13.46

ANSILT

ANSI Long Time Inverse

0.086

0.02

0.185

4.6

IECN

IEC Normal Inverse

0.14

0.02

0

-

IECV

IEC Very inverse

13.5

1.0

0

-

IEC

IEC Inverse

0.14

0.02

0

-

IECE

IEC Extremely inverse

80.0

2.0

0

-

IECST

IEC Short-time inverse

0.05

0.04

0

-

IECLT

IEC Long-time inverse

120.0

1.0

0

-

IECDefTime

IEC Definite Time

-

-

-

-

Resv

Reserved

-

-

-

-

UserDefine

Programmable

Only when the setting [Bayn.50/51Px.Opt_Curve] is set as “UserDefine”, i.e. the user-defined inverse-time characteristic is selected, the settings [Bayn.50/51Px.K], [Bayn.50/51Px.C] and [Bayn.50/51Px.Alpha] are useful, the inverse-time operating curve is determined by the three settings. 

Without time delay

When I > Ip , the protection operates immediately. 

Definite-time characteristic

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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3

3 Protection Functions

When I > Ip , the protection operates with a time delay of top (i.e. the value of the setting [Bayn.50/51Px.t_Op]), and the operating characteristic curve is as shown in the following figure:

t

3

t op

IP

I

Figure 3.8-3 Definite-time operating characteristic curve of phase overcurrent protection



Inverse-time characteristic

When I > Ip , the inverse-time accumulator begins to accumulate, and the operating time is affected by the applied current I . The larger current is, the smaller the operating time is, but not unlimited. When the current is large enough to a certain threshold ( Ip ), the inverse-time operating time will not continue to decrease, then the operating characteristic becomes the definite-time characteristic, and the operating time is tmin , i.e. the setting [Bayn.50/51Px.tmin] (x=1~2). The inverse-time operating characteristic equation is:   k t  c   TMS  ( I / I )  1 P  

Where:

Ip is the current setting [Bayn.50/51Px.I_Set]; TMS is the inverse-time time multiplier, i.e. the setting [Bayn.50/51Px.TMS];

k is the inverse-time coefficient K, i.e. the setting [Bayn.50/51Px.K];

c is the inverse-time coefficient C, i.e. the setting [Bayn.50/51Px.C];  is the inverse-time coefficient Alpha, i.e. the setting [Bayn.50/51Px.Alpha];

I is the measured current. The inverse-time operating characteristic curve is as shown below:

3-58

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

3 Protection Functions

t

3

t min

IP

ID

I

Figure 3.8-4 Inverse-time operating characteristic curve of phase overcurrent protection

When the applied current is not a fixed value, but changes with time, the operating behavior of the protection is shown in the following equation: T0

1

 t ( I )dt

1

0

Where: T0 is the operating time of the protection element; t(I) is the theoretical operating time when the current is I. 3.8.1.2 Dropout Characteristic The supported dropout characteristics of the phase overcurrent protection include immediate dropout, definite-time dropout and ANSI inverse-time dropout. When the operating curve is selected as definite-time, IEC inverse-time or user-defined inverse-time characteristic, the dropout characteristic can only be selected as immediate dropout or definite-time dropout, if inverse-time dropout is selected, the alarm signal “Fail_Settings” will be issued and the device will be blocked. When the operating curve is selected as ANSI inverse-time characteristic, the dropout characteristic can be selected as immediate dropout, definite-time dropout and ANSI inverse-time dropout. 

Immediate dropout

When I Ip , the inverse-time operating accumulator begins to accumulate, the accumulated value after tp (Assuming tp is less than the theoretical operating time) is calculated according to the following equation: tp

1 dt t(I ) 0

I tp  

At this time, if I [@Bayn.50/51Px.I_Set]

SIG

@Bayn.50/51Px.Pkp

SIG

@Bayn.50/51Px.St_A

SIG

@Bayn.50/51Px.St_B

SIG

@Bayn.50/51Px.St_C

SIG

@Bayn.50/51Px.Op_A

SIG

@Bayn.50/51Px.Op_B

SIG

@Bayn.50/51Px.Op_C

Timer t

&

@Bayn.50/51Px.Op_A

t

>=1 @Bayn.50/51Px.St

>=1 @Bayn.50/51Px.Op

Figure 3.8-8 Logic diagram of phase overcurrent protection

3.8.5 Settings 

Phase Overcurrent Protection Setting

Access path: MainMenu  Settings  Protection Settings  OC Settings Table 3.8-2 Settings of phase overcurrent protection No.

Settings

Range

Default value

Unit

Step

Description The current setting of stage x

1

Bayn.50/51Px.I_Set

(0.05 ~40)In

15.000

A

0.001

of

phase

overcurrent

protection of bay n The operating time setting of 2

Bayn.50/51Px.t_Op

0 ~100.000

0.100

s

0.001

stage x of phase overcurrent protection of bay n

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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3 Protection Functions No.

Settings

Default

Range

value

Unit

Step

Description The dropout time setting of

3

Bayn.50/51Px.t_DropOut

0 ~100.000

0

s

0.001

stage x of phase overcurrent protection of bay n The

logic

setting

for

enabling/disabling the stage 4

Bayn.50/51Px.En

Disabled Enabled

Enabled

x

-

of

phase

overcurrent

protection of bay n 0: disabling

3

1: enabling ANSIE; ANSIV; ANSIN; ANSIM; ANSIDefTime;

5

Bayn.50/51Px.Opt_Curve

ANSILTE;

The setting for selecting the

ANSILTV;

inverse-time

ANSILT;

characteristic curve of stage

IECN;

IECDefTime

-

x

of

phase

operating overcurrent

IECV;

protection of bay n. please

IEC;

refer to Section 3.8.1.1 for

IECE;

details.

IECST; IECLT; IECDefTime; Resv; UserDefine The setting for selecting the inverse-time

dropout

characteristic curve of stage 6

Bayn.50/51Px.Opt_Curve _DropOut

Inst; DefTime;

x Inst

-

of

phase

overcurrent

protection of bay n.

IDMT

Inst: instantaneous dropout DefTime:

definite-time

dropout IDMT: inverse-time dropout The time multiplier setting of 7

Bayn.50/51Px.TMS

0.040~20.000

1.000

0.001

stage x of phase overcurrent protection of bay n The minimum operating time

8

Bayn.50/51Px.tmin

0 ~10.000

0.020

s

0.001

setting of stage x of phase overcurrent protection of bay n

3-64

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3 Protection Functions No.

Settings

Default

Range

value

Unit

Step

Description The

9

customized

0.0010~

Bayn.50/51Px.K

constant

0.1400

120.0000

0.0001

operating

“k”

of

the

inverse-time characteristic

of

stage x of phase overcurrent protection of bay n The constant “α” customized

10

Bayn.50/51Px.Alpha

0.0100~3.0000

0.0200

0.0001

operating

of

the

inverse-time characteristic

of

stage x of phase overcurrent protection of bay n The constant “C” of the customized 11

0 ~1.0000

Bayn.50/51Px.C

0

0.0001

operating

inverse-time characteristic

of

stage x of phase overcurrent protection of bay n

All the current settings in above table are converted according to the CT ratio of each bay.

3.9 Earth Fault Overcurrent Protection

The bay label of displayed alarm signals, tripping signals, binary input signals, settings and sampled values related with each bay will change with the corresponding label settings. In this section, “@Bayn” is used to refer to the label setting of corresponding bay. The normal operating power system is three-phase symmetrical, its zero-sequence current and voltage are theoretically zero. Most of the faults are three-phase asymmetrical, according to the asymmetry of the fault, various protections reflect sequence component principle can be constituted. Earth fault overcurrent protection has been widely used in power systems, it can be used for the fault conditions that zero-sequence fault current flows into the earth, including single-phase earth fault and phase-to-phase short-circuit earth fault etc..

3.9.1 Function Description The device can provide two stages of earth fault overcurrent protection with independent logic. Each stage can be independently set as definite-time characteristics or inverse-time characteristics. The dropout characteristics can be set as immediate dropout, definite-time PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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3

3 Protection Functions

dropout or inverse-time dropout. Earth fault overcurrent protection can be enabled or blocked by the external binary input. Earth fault overcurrent protection can be enabled or disabled via the settings or binary input signals, for some specific applications, the protection needs to be blocked by the external signal, so the device provides a function block input signal to be used to block earth fault overcurrent protection. The enabling and blocking logic of earth fault overcurrent protection is shown in the figure below:

&

EN

@Bayn.50/51Gx.En

SIG

@Bayn.50/51Gx.Enable

SIG

@Bayn.50/51Gx.Block

SIG

Fail_Device

@Bayn.50/51Gx.On

3

& @Bayn.50/51Gx.Blocked

≥1

& @Bayn.50/51Gx.Valid

Figure 3.9-1 The enabling and blocking logic of earth fault overcurrent protection

The logic diagram of the fault detector element of earth fault overcurrent protection is as follows: SET

&

3I0>0.95*[@Bayn.50/51Gx.3I0_Set]

0

SIG

@Bayn.50/51Gx.On

SIG

@Bayn.50/51Gx.Valid

500ms

& @Bayn.50/51Gx.Pkp

Figure 3.9-2 Logic diagram of the fault detector element of earth fault overcurrent protection

3.9.1.1 Operating Characteristic Earth fault overcurrent protection can operate without time delay or operate with a definite-time limit, it can also operate with an inverse-time limit, the characteristic curve meets the IEC60255-3 and ANSI C37.112 standards. Earth fault overcurrent protection can support definite-time limit, IEC & ANSI standard reverse time limit and user-defined inverse-time limit, users can select the wanted operating curve by the setting [Bayn.50/51Gx.Opt_Curve], the relationship between the value of the setting and the curve is shown in the table below. Bayn.50/51Gx.Opt_Curve

k

Time Characteristic

α

c

tr

ANSIE

ANSI Extremely Inverse

28.2

2.0

0.1217

29.1

ANSIV

ANSI Very inverse

19.61

2.0

0.491

21.6

ANSIN

ANSI Normal Inverse

0.0086

0.02

0.0185

0.46

ANSIM

ANSI Moderately Inverse

0.0515

0.02

0.114

4.85

ANSIDefTime

ANSI Definite Time

-

-

-

-

3-66

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3 Protection Functions Bayn.50/51Gx.Opt_Curve

k

Time Characteristic

α

c

tr

ANSILTE

ANSI Long Time Extremely Inverse

64.07

2.0

0.25

30

ANSILTV

ANSI Long Time Very Inverse

28.55

2.0

0.712

13.46

ANSILT

ANSI Long Time Inverse

0.086

0.02

0.185

4.6

IECN

IEC Normal Inverse

0.14

0.02

0

-

IECV

IEC Very inverse

13.5

1.0

0

-

IEC

IEC Inverse

0.14

0.02

0

-

IECE

IEC Extremely inverse

80.0

2.0

0

-

IECST

IEC Short-time inverse

0.05

0.04

0

-

IECLT

IEC Long-time inverse

120.0

1.0

0

-

IECDefTime

IEC Definite Time

-

-

-

-

Resv

Reserved

-

-

-

-

UserDefine

Programmable

3

Only when the setting [Bayn.50/51Gx.Opt_Curve] is set as “UserDefine”, i.e. the user-defined inverse-time characteristic is selected, the settings [Bayn.50/51Gx.K], [Bayn.50/51Gx.C] and [Bayn.50/51Gx.Alpha] are useful, the inverse-time operating curve is determined by the three settings. 

Without time delay

When I 0 > I 0 p , the protection operates immediately. 

Definite-time characteristic

When I 0 > I 0 p , the protection operates with a time delay of top (i.e. the value of the setting [Bayn.50/51Gx.t_Op]), and the operating characteristic curve is as shown in the following figure:

t

t op

I0p

I

Figure 3.9-3 Definite-time operating characteristic curve of earth fault overcurrent protection



Inverse-time characteristic

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3 Protection Functions

When I 0 > I 0 p , the inverse-time accumulator begins to accumulate, and the operating time is affected by the applied current I 0 . The larger current is, the smaller the operating time is, but not unlimited. When the current is large enough to a certain threshold ( I 0 p ), the inverse-time operating time will not continue to decrease, then the operating characteristic becomes the definite-time characteristic, and the operating time is tmin , i.e. the setting [Bayn.50/51Gx.tmin]. The inverse-time operating characteristic equation is: 

k

t  

 (I 0 / I 0P )  1

3

  c   TMS 

Where:

I 0 p is the current setting [Bayn.50/51Gx.3I0_Set]; TMS is the inverse-time time multiplier, i.e. the setting [Bayn.50/51Gx.TMS];

k is the inverse-time coefficient K, i.e. the setting [Bayn.50/51Gx.K]; c is the inverse-time coefficient C, i.e. the setting [Bayn.50/51Gx.C];

 is the inverse-time coefficient Alpha, i.e. the setting [Bayn.50/51Gx.Alpha];

I is the measured zero-sequence current.

The inverse-time operating characteristic curve is as shown below:

t

t min

ID

I0P

I

Figure 3.9-4 Inverse-time operating characteristic curve of earth fault overcurrent protection

When the applied zero-sequence current I 0 is not a fixed value, but changes with time, the operating behavior of the protection is shown in the following equation: T0

1

 t ( I )dt 0

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1

0

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

3 Protection Functions

Where: T0 is the operating time of the protection element; t(I0) is the theoretical operating time when the current is I 0 . 3.9.1.2 Dropout Characteristic The supported dropout characteristics of the earth fault overcurrent protection include immediate dropout, definite-time dropout and ANSI inverse-time dropout. When the operating curve is selected as definite-time, IEC inverse-time or user-defined inverse-time characteristic, the dropout characteristic can only be selected as immediate dropout or definite-time dropout, if inverse-time dropout is selected, the alarm signal “Fail_Settings” will be issued and the device will be blocked. When the operating curve is selected as ANSI inverse-time characteristic, the dropout characteristic can be selected as immediate dropout, definite-time dropout and ANSI inverse-time dropout. 

Immediate dropout

When I 0 I 0 p , the inverse-time operating accumulator begins to accumulate, the accumulated value after tp (Assuming tp is less than the theoretical operating time) is calculated according to the following equation: tp

Itp 

1

 t(I 0

dt

0

)

At this time, if I 0 [@Bayn.50/51GX.3I0_Set]

3

@Bayn.50/51Gx.Op

t

@Bayn.50/51Gx.Pkp

Figure 3.9-8 Logic diagram of earth fault overcurrent protection

3.9.5 Settings Earth Fault Overcurrent Protection Setting



Access path: MainMenu  Settings  Protection Settings  ROC Settings Table 3.9-2 Settings of earth fault overcurrent protection No.

Settings

Default

Range

value

Unit

Step

Description The current setting of stage

1

Bayn.50/51Gx.3I0_Set

(0.05 ~40)In

15.000

A

0.001

x of earth fault overcurrent protection of bay n The operating time setting

2

Bayn.50/51Gx.t_Op

0 ~100.000

0.100

s

0.001

of stage x of earth fault overcurrent

protection

of

bay n The dropout time setting of 3

Bayn.50/51Gx.t_DropOut

0 ~100.000

0

s

0.001

stage

x

of

overcurrent

earth

fault

protection

of

setting

for

bay n The

logic

enabling/disabling the stage 4

Bayn.50/51Gx.En

Disabled Enabled

Enabled

-

x of earth fault overcurrent protection of bay n 0: disabling 1: enabling

ANSIE; 5

Bayn.50/51Gx.Opt_Curve

ANSIV; ANSIN;

The setting for selecting the IECDefTime

ANSIM;

-

inverse-time

operating

characteristic curve of stage x of earth fault overcurrent

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3 Protection Functions No.

Settings

Default

Range

value

Unit

Step

Description

ANSIDefTime;

protection of bay n, please

ANSILTE;

refer to Section 3.9.1.1 for

ANSILTV;

details.

ANSILT; IECN; IECV; IEC; IECE;

3

IECST; IECLT; IECDefTime; Resv; UserDefine The setting for selecting the inverse-time

dropout

characteristic curve of stage 6

Bayn.50/51Gx.Opt_Curve _DropOut

Inst;

x of earth fault overcurrent

DefTime;

Inst

-

protection of bay n,

IDMT

Inst: instantaneous dropout DefTime:

definite-time

dropout IDMT: inverse-time dropout The time multiplier setting of 7

Bayn.50/51Gx.TMS

0.040~20.000

1.000

0.001

stage

x

of

overcurrent

earth protection

fault of

bay n The 8

Bayn.50/51Gx.tmin

0 ~10.000

0.02

s

0.001

minimum

operating

time setting of stage x of earth

fault

overcurrent

protection of bay n The constant “k” of the customized 9

Bayn.50/51Gx.K

0.0010~ 120.0000

0.1400

0.0001

inverse-time

operating characteristic of stage

x

of

overcurrent

earth protection

fault of

bay n The constant “α” of the customized 10

Bayn.50/51Gx.Alpha

0.0100~ 3.0000

0.0200

0.0001

inverse-time

operating characteristic of stage

x

overcurrent

of

earth protection

fault of

bay n

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3 Protection Functions No.

Settings

Default

Range

value

Unit

Step

Description The constant “C” of the customized

11

0 ~1.0000

Bayn.50/51Gx.C

0

0.0001

inverse-time

operating characteristic of stage

x

overcurrent

of

earth protection

fault of

bay n

All the current settings in above table are converted according to the CT ratio of each bay.

3.10 CT Circuit Supervision

The bay label of displayed alarm signals, tripping signals, binary input signals, settings and sampled values related with each bay will change with the corresponding label settings. In this section, “@BBx” is used to refer to the label setting of corresponding busbar and “@Bayn” is used to refer to the label setting of corresponding bay. For a bus coupler bay, “@BCy” is also used to refer to the label setting of corresponding bus coupler. For a bus section bay, “@BSz” is also used to refer to the label setting of corresponding bus section.

3.10.1 Function Description CT circuit abnormality will affect the calculation result of the busbar differential current, and then affect the operation behavior of busbar differential protection. In order to prevent the protection from mal-operation due to CT circuit abnormality, CT circuit supervision function is provided by the device. 3.10.1.1 CT Circuit Failure 1. If the check zone differential current of one phase is larger than the setting [I_AlmH_CTS], CT circuit failure alarm of corresponding phase “AlmH_CTS_X” (X=A, B or C) will be issued. CT circuit failure alarm will affect the operation behavior of busbar differential protection, users can select the busbar differential protection blocking mode under CT circuit failure condition via the logic setting [87B.Opt_CTS_Blk], please refer to Section 3.3.1.9 for details. 2. For the BC/BS that only one CT is available, if the check zone differential current of one phase is smaller than the setting [I_AlmH_CTS] and both discriminating zone differential currents of the phase of the two connected busbars are larger than [I_AlmH_CTS], BC/BS CT circuit failure alarm signal of corresponding phase “@BCy.AlmH_CTS_X”/“@BSz.AlmH_CTS_X” PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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3 Protection Functions

will be issued with a time delay of 5s. BC/BS CT circuit failure alarm will affect the operation behavior of busbar differential protection, users can select the inter-linked mode under BC/BS CT circuit failure condition via the logic setting [87B.Opt_BC_CTS_IntLink], please refer to Section 3.3.1.5 for details. If [87B.Opt_BC_CTS_IntLink] is set as “None”, the busbar differential protection will be blocked according to the blocking mode that set via the logic setting [87B.Opt_CTS_Blk], please refer to Section 3.3.1.9 for details.

3

3. For the BC/BS that double CTs are available, if the check zone differential current of one phase is smaller than the setting [I_AlmH_CTS] and discriminating zone differential current of the phase of any connected busbar is larger than [I_AlmH_CTS], if the discriminating zone differential current equals to the difference of current between the two CTs, BC/BS CT circuit failure alarm signal of corresponding phase “@BCy.AlmH_CTS_X”/“@BSz.AlmH_CTS_X” will be issued with a time delay of 5s. BC/BS CT circuit failure alarm will affect the operation behavior of busbar differential protection, users can select the inter-linked mode under BC/BS CT circuit failure condition via the logic setting [87B.Opt_BC_CTS_IntLink], please refer to Section 3.3.1.5 for details. If [87B.Opt_BC_CTS_IntLink] is set as “None”, the busbar differential protection will be blocked according to the blocking mode that set via the logic setting [87B.Opt_CTS_Blk], please refer to Section 3.3.1.9 for details.

If the logic setting [En_AutoRecov_AlmH_CTS] is set as “1”, the CT circuit failure alarm can be reset automatically after the CT circuit returns to normal condition. If the logic setting [En_AutoRecov_AlmH_CTS] is set as “0”, the alarm should be reset manually after the CT circuit returns to normal condition, it can be reset by energizing the resetting binary input “BI_RstTarg” or pressing “ESC” first then “ENT” simultaneously (“ESC” and “ENT” are two keypads on the front of the device) after the CT circuit returns to normal condition. When voltage concerned function is enabled and VT circuit failure is not detected, CT circuit supervision will be blocked if voltage blocking element of any busbar is released. If VT circuit failure is detected, CT circuit supervision will not be blocked. If voltage concerned function is disabled, or the logic setting [87B.VCE.En] is set as “0”, CT circuit supervision logic will not be affected by voltage. If [87B.Opt_BC_CTS_IntLink] is set as “None”, and [87B.Opt_CTS_Blk] is set as “None”, “PhSeg_Blk87B” or “3-phase_Blk87B”, for BC/BS CT circuit failure will not affect the check zone differential element, so after BC/BS CT circuit failure occurs, the alarm signal will be issued, but the busbar differential protection will not be affected. 3.10.1.2 CT Circuit Abnormality 1.

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If the check zone differential current of one phase is larger than the setting i.e. [I_AlmL_CTS],

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3 Protection Functions

CT circuit abnormality alarm of corresponding phase [AlmL_CTS_X] (X=A, B or C) will be issued with a time delay of 5s. 2.

For the BC/BS that only one CT is available, if the check zone differential current of one phase is smaller than the setting [I_AlmL_CTS] and both discriminating zone currents of the phase of the two connected busbars are larger than [I_AlmL_CTS], BC/BS CT circuit abnormality alarm of corresponding phase [@BCy.AlmL_CTS_X]/[@BSz.AlmL_CTS_X] will be issued with a time delay of 5s.

3.

For the BC/BS that double CTs are available, if the check zone differential current of one phase is smaller than the setting [I_AlmL_CTS] and discriminating zone differential current of the phase of any connected busbar is larger than [I_AlmL_CTS], if the discriminating zone differential current equals to the difference of current between the two CTs, BC/BS CT circuit abnormality alarm of corresponding phase [@BCy.AlmL_CTS_X]/[@BSz.AlmL_CTS_X] will be issued with a time delay of 5s.

If the logic setting [En_AutoRecov_AlmL_CTS] is set as “1”, the CT circuit abnormality alarm can be reset automatically after the CT circuit returns to normal condition. If the logic setting [En_AutoRecov_AlmL_CTS] is set as “0”, the alarm should be reset manually after the CT circuit returns to normal condition, it can be reset by energizing the resetting binary input [BI_RstTarg] or pressing “ESC” first then “ENT” simultaneously (“ESC” and “ENT” are two keypads on the front of the device) after the CT circuit returns to normal condition. Busbar differential protection will not be blocked when CT circuit abnormality occurs. 3.10.1.3 Discriminating Zone Differential Current High/Low Value Alarm 1.

If discriminating zone differential current of BBx is larger than [I_AlmL_CTS], BBx differential current low value alarm signal [@BBx.AlmL_Diff] will be issued with a time delay of 5s.

2.

If discriminating zone differential current of BBx is larger than [I_AlmH_CTS], BBx differential current high value alarm signal [@BBx.AlmH_Diff] will be issued with a time delay of 5s. BBx differential current high value alarm will affect the operation behavior of busbar differential protection, users can select the busbar differential protection blocking mode via the logic setting [87B.Opt_CTS_Blk], please refer to Section 3.3.1.9 for details.

If the logic setting [En_AutoRecov_AlmL_CTS] is set as “1”, the BBx differential current low value alarm can be reset automatically after the CT circuit returns to normal condition. If the logic setting [En_AutoRecov_AlmH_CTS] is set as “1”, the BBx differential current high

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value alarm can be reset automatically after the CT circuit returns to normal condition. Otherwise, the two alarm signals should be reset manually after the CT circuit returns to normal condition, it can be reset by energizing the resetting binary input [BI_RstTarg] or pressing “ESC” first then “ENT” simultaneously (“ESC” and “ENT” are two keypads on the front of the device) after the CT circuit returns to normal condition.

3.10.2 Function Block Diagram CTS

3

AlmH_CTS_X

Ia_Bayn, Ib_Bayn, Ic_Bayn

@BCy.AlmH_CTS_X

AlmL_CTS_X @BCy.AlmL_CTS_X @BBx.AlmH_Diff @BBx.AlmL_Diff

@BSz.AlmH_CTS_X @BSz.AlmL_CTS_X

X=A, B or C

3.10.3 I/O Signal Table 3.10-1 Output signal of CT circuit supervision No.

Output signal

Description

1

AlmH_CTS

CT circuit failure

2

AlmH_CTS_A

Phase-A CT circuit failure

3

AlmH_CTS_B

Phase-B CT circuit failure

4

AlmH_CTS_C

Phase-C CT circuit failure

5

@BCy.AlmH_CTS

BCy CT circuit failure

6

@BCy.AlmH_CTS_A

BCy phase-A CT circuit failure

7

@BCy.AlmH_CTS_B

BCy phase-B CT circuit failure

8

@BCy.AlmH_CTS_C

BCy phase-C CT circuit failure

9

@BSz.AlmH_CTS

BSz CT circuit failure

10

@BSz.AlmH_CTS_A

BSz phase-A CT circuit failure

11

@BSz.AlmH_CTS_B

BSz phase-B CT circuit failure

12

@BSz.AlmH_CTS_C

BSz phase-C CT circuit failure

13

AlmL_CTS

CT circuit abnormality

14

AlmL_CTS_A

Phase-A CT circuit abnormality

15

AlmL_CTS_B

Phase-B CT circuit abnormality

16

AlmL_CTS_C

Phase-C CT circuit abnormality

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3 Protection Functions 17

@BCy.AlmL_CTS

BCy CT circuit abnormality

18

@BCy.AlmL_CTS_A

BCy phase-A CT circuit abnormality

19

@BCy.AlmL_CTS_B

BCy phase-B CT circuit abnormality

20

@BCy.AlmL_CTS_C

BCy phase-C CT circuit abnormality

21

@BSz.AlmL_CTS

BSz CT circuit abnormality

22

@BSz.AlmL_CTS_A

BSz phase-A CT circuit abnormality

23

@BSz.AlmL_CTS_B

BSz phase-B CT circuit abnormality

24

@BSz.AlmL_CTS_C

BSz phase-C CT circuit abnormality

25

@BBx.AlmH_Diff

BBx differential current high value alarm

26

@BBx.AlmL_Diff

BBx differential current low value alarm

3

3.10.4 Logic 3.10.4.1 CT Circuit Failure

SET

Ida_CZ>[I_AlmH_CTS]

5s

0

AlmH_CTS_A

SET

Idb_CZ>[I_AlmH_CTS]

5s

0

AlmH_CTS_B

SET

Idc_CZ>[I_AlmH_CTS]

5s

0

AlmH_CTS_C

Figure 3.10-1 Logic of CT circuit failure

Where: Ida_CZ: Phase-A check zone differential current Idb_CZ: Phase-B check zone differential current Idc_CZ: Phase-C check zone differential current I_AlmH_CTS: Current setting of CT circuit failure AlmH_CTS_A: Phase-A CT circuit failure alarm signal AlmH_CTS_B: Phase-B CT circuit failure alarm signal AlmH_CTS_C: Phase-C CT circuit failure alarm signal The logic of BC/BS CT circuit failure (for the BC/BS that only one CT is available) is shown as follows (Takes BC1 in Figure 3.2-6 as an example).

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3 Protection Functions

SET

Ida_CZ[I_AlmH_CTS]

SET

Ida_BB2>[I_AlmH_CTS]

SET

Idb_CZ[I_AlmH_CTS]

SET

Idb_BB2>[I_AlmH_CTS]

SET

Idc_CZ[I_AlmH_CTS]

SET

Idc_BB2>[I_AlmH_CTS]

&

Figure 3.10-2 Logic of BC/BS CT circuit failure (for the BC/BS that only one CT is available)

Where: Ida_BB1: Phase-A discriminative differential current of BB1 Idb_BB1: Phase-B discriminative differential current of BB1 Idc_BB1: Phase-C discriminative differential current of BB1 Ida_BB2: Phase-A discriminative differential current of BB2 Idb_BB2: Phase-B discriminative differential current of BB2 Idc_BB2: Phase-C discriminative differential current of BB2 @BC1.AlmH_CTS_A: BC1 phase-A CT circuit failure @BC1.AlmH_CTS_B: BC1 phase-B CT circuit failure @BC1.AlmH_CTS_C: BC1 phase-C CT circuit failure The logic of BC/BS CT circuit failure (for the BC/BS that double CTs are available) is shown as follows (Takes BC1 in Figure 3.2-9 as an example).

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3 Protection Functions

SET

Idx_CZ[I_AlmH_CTS]

SIG

Idx_BB1=∣Ix_BC1_CT1-Ix_BC1_CT2∣

SET

Idx_CZ[I_AlmH_CTS]

SIG

Idx_BB2=∣Ix_BC1_CT1-Ix_BC1_CT2∣

& &

5s

0

@BC1.CT1.AlmH_CTS_X

5s

0

@BC1.CT2.AlmH_CTS_X

& &

3

Figure 3.10-3 Logic of BC/BS CT circuit failure (for the BC/BS that double CTs are available)

Where: Ix_BC1_CT1: Phase-X (A, B or C) current of CT1 of BC1 IX_BC1_CT2: Phase-X (A, B or C) current of CT2 of BC1 3.10.4.2 CT Circuit Abnormality

SET

Ida_CZ>[I_AlmL_CTS]

5s

0

AlmL_CTS_A

SET

Idb_CZ>[I_AlmL_CTS]

5s

0

AlmL_CTS_B

SET

Idc_CZ>[I_AlmL_CTS]

5s

0

AlmL_CTS_C

Figure 3.10-4 Logic of CT circuit abnormality

Where: Ida_CZ: Phase-A check zone differential current Idb_CZ: Phase-B check zone differential current Idc_CZ: Phase-C check zone differential current I_AlmL_CTS: Current setting of CT circuit abnormality AlmL_CTS_A: Phase-A CT circuit abnormality AlmL_CTS_B: Phase-B CT circuit abnormality AlmL_CTS_C: Phase-C CT circuit abnormality The logic of BC/BS CT circuit abnormality (for the BC/BS that only one CT is available) is shown PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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as follows (Takes BC1 in Figure 3.2-6 as an example).

SET

Ida_CZ[I_AlmL_CTS]

SET

Ida_BB2>[I_AlmL_CTS]

SET

Idb_CZ[I_AlmL_CTS]

SET

Idb_BB2>[I_AlmL_CTS]

SET

Idc_CZ[I_AlmL_CTS]

SET

Idc_BB2>[I_AlmL_CTS]

& 5s

&

0

@BC1.AlmL_CTS_A

&

3

&

5s

0

@BC1.AlmL_CTS_B

5s

0

@BC1.AlmL_CTS_C

& &

Figure 3.10-5 Logic of BC/BS CT circuit abnormality (for the BC/BS that only one CT is available)

Where: Ida_BB1: Phase-A discriminative differential current of BB1 Idb_BB1: Phase-B discriminative differential current of BB1 Idc_BB1: Phase-C discriminative differential current of BB1 Ida_BB2: Phase-A discriminative differential current of BB2 Idb_BB2: Phase-B discriminative differential current of BB2 Idc_BB2: Phase-C discriminative differential current of BB2 @BC1.AlmL_CTS_A: BC1 phase-A CT circuit abnormality @BC1.AlmL_CTS_B: BC1 phase-B CT circuit abnormality @BC1.AlmL_CTS_C: BC1 phase-C CT circuit abnormality The logic of BC/BS CT circuit abnormality (for the BC/BS that double CTs are available) is shown as follows (Takes BC1 in Figure 3.2-9 as an example).

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Idx_CZ[I_AlmL_CTS]

SIG

Idx_BB1=∣Ix_BC1_CT1-Ix_BC1_CT2∣

SET

Idx_CZ[I_AlmL_CTS]

SIG

Idx_BB2=∣Ix_BC1_CT1-Ix_BC1_CT2∣

& &

5s

0

@BC1.CT1.AlmL_CTS_X

5s

0

@BC1.CT2.AlmL_CTS_X

& &

3

Figure 3.10-6 Logic of BC/BS CT circuit abnormality (for the BC/BS that double CTs are available)

Where: Ix_BC1_CT1: Phase-X (A, B or C) current of CT1 of BC1 IX_BC1_CT2: Phase-X (A, B or C) current of CT2 of BC1 3.10.4.3 Discriminating Zone Differential Current High/Low Value Alarm

SET

Ida_BBx>[I_AlmH_CTS]

SET

Idb_BBx>[I_AlmH_CTS]

SET

Idc_BBx>[I_AlmH_CTS]

>=1 5s

0

@BBx.AlmH_Diff

Figure 3.10-7 Logic of BBx differential current high value alarm

Where: Ida_BBx: Phase-A discriminative differential current of BBx Idb_BBx: Phase-B discriminative differential current of BBx Idc_BBx: Phase-C discriminative differential current of BBx @BBx.AlmH_Diff: BBx differential current high value alarm signal

SET

Ida_BBx>[I_AlmL_CTS]

SET

Idb_BBx>[I_AlmL_CTS]

SET

Idc_BBx>[I_AlmL_CTS]

>=1 5s

0

@BBx.AlmL_Diff

Figure 3.10-8 Logic of BBx differential current low value alarm

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Where: @BBx.AlmL_Diff: BBx differential current low value alarm signal

3.10.5 Settings Access path: MainMenuSettingsProt SettingsBBP Settings Table 3.10-2 CT circuit supervision function related settings 1

No.

Name

Default

Range

value

3

Unit

Step

Remark Logic setting for selecting the

differential

protection

blocking mode, please refer to Section 3.3.1.9 for details. None: Unblocking PhSeg_Blk87B: None

Phase-segregated blocking

PhSeg_Blk87B 1

87B.Opt_CTS_Blk

3-phase_Blk87B PhSeg_BlkDZ

PhSeg_B lkDZ

3-phase_BlkDZ

3-phase_Blk87B: Three-phase blocking PhSeg_BlkDZ: Phase-segregated blocking according to respective busbar zone 3-phase_BlkDZ: Three-phase according

blocking to

respective

busbar zone Logic setting for selecting the BC/BS CT circuit failure inter-linked

87B.Opt_BC_CTS_IntLink

PhSeg

please

refer to Section 3.3.1.5 for

None 2

mode,

PhSeg

3-phase

details. None: no inter-link PhSeg:

phase-segregated

inter-link; 3-phase:

three-phase

inter-link 1:

busbar

differential

protection is controlled by 3

87B.VCE.En

Disabled Enabled

Enabled

voltage control element 0:

busbar

differential

protection is not controlled by voltage control element

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

Access path:

MainMenu  Settings  Global Settings  Superv Settings Table 3.10-3 CT circuit supervision function related settings 2 No.

Settings

Range

Default value

Unit

Step

1

I_AlmH_CTS

0.05In ~1.00In

0.100

A

0.001

2

I_AlmL_CTS

0.05In ~1.00In

0.080

A

0.001

Remark Current setting of CT circuit failure Current setting of CT circuit abnormality 1: the CT circuit failure alarm signal

can

be

reset

automatically after the CT circuit 3

En_AutoRecov_AlmH_CTS

Disabled Enabled

Enabled

returns

to

normal

condition 0: the CT circuit failure alarm signal

cannot

be

reset

automatically after the CT circuit

returns

to

normal

condition 1: the CT circuit abnormality alarm signal can be reset automatically after the CT circuit 4

En_AutoRecov_AlmL_CTS

Disabled Enabled

Enabled

returns

to

normal

condition 0: the CT circuit abnormality alarm signal cannot be reset automatically since the CT circuit

returns

to

normal

condition

All the current settings in above table are converted according to the referenced CT ratio.

3.11 VT Circuit Supervision 3.11.1 Function Description 1.

If BBx is in service and positive-sequence voltage (U1) of BBx is smaller than [VTS.U1_Set] and fault detector element does not pick up, the alarm signal “@BBx.Alm_VTS” will be issued with a time delay of [VTS.t_DPU].

2.

If BBx is in service and residual voltage (3U0) of BBx is larger than [VTS.3U0_Set] and fault

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3

3 Protection Functions

detector element does not pick up, the alarm signal “@BBx.Alm_VTS” will be issued with a time delay of [VTS.t_DPU]. If VT circuit failure is detected, DPFC voltage FD element will be disabled. When the three phase-voltage returns to normal condition, the alarm “@BBx.Alm_VTS” will be reset automatically with a time delay of [VTS.t_DDO]. If the fault detector element picks up due to a disturbance in the system (DPFC current is detected), the VT circuit supervision will be disabled for 3s.

3.11.2 Function Block Diagram

3

VTS Ia_Bayn, Ib_Bayn, Ic_Bayn

@BBx.Alm_VTS

Ua_BBx, Ub_BBx, Uc_BBx

3.11.3 I/O Signal Table 3.11-1 Output signal of VT circuit supervision No. 1

Signal @BBx.Alm_VTS

Description BBx VT circuit failure

3.11.4 Logic SIG

Ua>0.7Un

SIG

Ub>0.7Un

SIG

Uc>0.7Un

SIG

IΨ_Bayn>0.04In

SET

3U0>[VTS.3U0_Set]

SET

U1=1 SIG

Bay n is conn ected to B B1

SIG

Bay n is conn ected to B B2

SIG

&

Bayn.Alm_DS

IΨ_Bayn>0.04In

3

Figure 3.12-2 Logic of disconnector position alarm

Where: Bayn DS position changes: Disconnector position of bay n changes (from open change to closed or from closed change to open). En_AutoRecov_DS: 1: Logic setting of busbar differential protection. When it is set as “1”, if any disconnector position alarm is issued, once the abnormality of disconnector position disappears, the alarm will be reset automatically. When it is set as “0”, if any disconnector position alarm is issued, the alarm cannot be reset unless energizing the disconnector position confirm binary input [BI_ConfirmDS]. Bay n is connected to BB1, Bay n is connected to BB2: Please refer to the inter-connection mode alarm logic. IΨ_Bayn: Any phase current of feeder bay n @Bayn.Alm_DS: Disconnector position of bay n is abnormal. 3.12.3.3 Disconnector Position Automatic Correction Logic Takes BB1 as an example

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3 Protection Functions

SIG

3

Bay n is conn ected to B B1

SIG

Ida_CZ0.08In

SIG

Ida_BB2=1 BI

@Bayn.BI_89b_@BB1

BI

@Bayn.BI_89a_@BB1

BI

@Bayn.BI_89b_@BB1

SIG

Dual-position CB

BI

@Bayn.BI_52a

BI

@Bayn.BI_52b

BI

@Bayn.BI_52a

BI

@Bayn.BI_52b

BI

BI_Maintenan ce

0

@Bayn.Alm_89a/89b_@BB1

&

& >=1

3

& 5s

0

@Bayn.Alm_52a/52b

&

Figure 3.12-4 Logic of dual-position alarm

Where: Dual-position DS: Dual-position for disconnector status, it can be configured via PCS-Studio configuration tool. @Bayn.BI_89a_@BB1: Normally open auxiliary contact of BB1 disconnector of bay n @Bayn.BI_89b_@BB1: Normally closed auxiliary contact of BB1 disconnector of bay n Dual-position CB: Dual-position for circuit breaker status, it can be configured via PCS-Studio configuration tool. @Bayn.Alm_89a/89b_@BBx: Dual-position alarm for BB1 disconnector of bay n @Bayn.BI_52a: Normally open auxiliary contact of the circuit breaker of bay n @Bayn.BI_52b: Normally closed auxiliary contact of the circuit breaker of bay n BI_Maintenance: Binary input to indicate circuit breaker is in maintenance @Bayn.Alm_52a/52b: Dual-position alarm for circuit breaker of bay n

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3.12.3.5 Disconnector Position Alarm Blocking Busbar Differential Protection Logic

3

SIG

Bay n is connected to BB1

SIG

Bay n is connected to BB2

SIG

IΨ_Bayn>0.04In

SET

[En_Blk87B_DS_Open_WithCurr]

SET

[Opt_DS_DPS_BAD] = 2

SIG

Bayn.BI_89a_@BBx = 1

SIG

Bayn.BI_89b_@BBx = 1

SET

[Opt_DS_DPS_INT] = 2

SIG

Bayn.BI_89a_@BBx = 0

SIG

Bayn.BI_89b_@BBx = 0

SIG

Disconnector position of BBx

& &

&

>=1 &

DS Alarm Block 87B_BBx &

Figure 3.12-5 Logic of disconnector position alarm blocking busbar differential protection

Where: Bay n is connected to BB1, Bay n is connected to BB2: Please refer to the inter-connection mode alarm logic. IΨ_Bayn: Any phase current of feeder bay n. DS Alarm Block 87B_BBx: Bay n disconnector position alarm signal which will block busbar differential protection of BBx.

3.12.4 Settings Access path: MainMenuSettingsProt SettingsBBP Settings Table 3.12-4 Disconnector position related settings 1

No.

Settings

Range

Default value

Unit

Step

Remark 1: if current is detected for a bay, but the

corresponding

disconnector

position is missing, the last valid disconnector 1

En_Mem_DS_Open

Disabled

_WithCurr

Enabled

Enabled

position

will

be

memorized 0: if current is detected for a bay, but the

corresponding

disconnector

position is missing, the last valid disconnector position will not be memorized 2

3-94

En_Blk87B_DS_Open

Disabled

_WithCurr

Enabled

Disabled

1: busbar differential protection is blocked when current is detected for

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3 Protection Functions a

bay

but

the

corresponding

disconnector position is missing 0: busbar differential protection is not blocked when current is detected for a

bay

but

the

corresponding

disconnector position is missing “0” is recommended for this logic setting. The treatment method when both of the normally open auxiliary contact and normally closed auxiliary contact of a disconnector are energized at the same time.

ForceCls 3

Opt_DS_DPS_BAD

Memorize

0: the disconnector position status is

Memorize

considered as closed;

BlkBBP

1: take the last valid memorized position; 2: take the last valid memorized position and block the corresponding busbar differential protection. The treatment method when both of the normally open auxiliary contact and normally closed auxiliary contact of a disconnector are de-energized at the same time.

ForceCls 4

Opt_DS_DPS_INT

Memorize

0: the disconnector position status is

Memorize

considered as closed;

BlkBBP

1: take the last valid memorized position; 2: take the last valid memorized position and block the corresponding busbar differential protection.



Access path:

MainMenu  Settings  Global Settings  Superv Settings Table 3.12-5 Disconnector position related settings 2 No.

Settings

Range

Default value

Unit

Step

Remark Time

1

t_Alm_89a/89b

0~1000000.000

10.000

s

0.001

Date: 2019-03-11

for

disconnector

dual-position alarm (i.e. the normally closed and normally open auxiliary contact

PCS-915SC Centralized Busbar Relay

delay

of

a

disconnector

are

3-95

3

3 Protection Functions No.

Settings

Range

Default value

Unit

Step

Remark energized at the same time. Time delay for the alarm when the

2

t_Alm_Two_DS_Closed

0~1000000

10.000

s

0.001

disconnectors of two busbars of a bay are closed at the same time. 1: If any disconnector position alarm is issued, once the abnormality of disconnector position disappears,

3

3

En_AutoRecov_DS

Disabled Enabled

the alarm will be reset automatically. Enabled

0: If any disconnector position alarm is issued, the alarm cannot be reset unless energizing the disconnector position

confirm

binary

input

“BI_ConfirmDS”

3.13 Busbar Protection Operation Mode Identification Drawing the busbar arrangement on the page “Single Line Graph” via the auxiliary configuration tool PCS-Studio, and completing the type definition of each bay of the busbar arrangement, then PCS-915SC can be adapted to different busbar arrangement. The currently supported bay type including single-CT bus coupler (Tie), double-CTs bus coupler (Tie2CT), feeder (Feeder) and disconnector (SwitchTie). The currently supported busbar arrangement including single-busbar arrangement, single-busbar with bus section arrangement, double-busbars arrangement, double-busbars with one bus section arrangement, double-busbars with two bus sections arrangement, single-busbar with transfer bus arrangement, single-busbar with bus section and transfer bus arrangement, double-busbars with transfer bus arrangement etc..

3.13.1 Bay Type Description Following table lists the currently supported bay types of the device. The switch, TA, etc. in each bay symbol are not allowed to be deleted. The disconnector can be added according to the actual needs on site. It should be noted that the increased disconnector symbol must be guaranteed within the box of the bay symbol. If the disconnector symbol is outside the box of the bay symbol, the device does not consider that the added disconnector belongs to the bay. At present, the device only supports adding disconnector symbol in the bay symbol, and does not support adding other symbols such as switch and TA. For details, please refer to Section 3.13.2.

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Bay type

Bay symbol

Description Single-CT bus coupler, it is used as the tie breaker for the busbar, the busbar can be connected to both the breaker side and the TA side. When only one busbar is connected to a certain side, the BC current will be counted into the discriminating zone differential

Tie

current of the connected busbar. When the number of the connected busbars on one side is greater than or equal to 2, the BC current will be counted into the discriminating zone differential current of the busbar of which the disconnector is closed. In addition, whether the BS current is counted into the discriminating zone differential current also needs to consider the dead zone fault protection function. Double-CTs bus coupler, it is used as the tie breaker for the busbar, the busbar can be connected to both the TA1 side and the TA2 side. Double-click the symbol, the cross attribute (Across, Non Across) can be selected. Across: TA1 and TA2 are cross-counted into the discriminating zone differential current of the connected busbars. Non Across: TA1 and TA2 are not cross-counted into the discriminating zone differential current of the connected busbars, if BC dead zone fault happens, the busbar differential protection will not operate. Currently BC dead zone fault busbar differential

Tie2CT

protection function is not available, so “Across” mode is recommended. When only one busbar is connected to a certain side, the BC current will be counted into the discriminating zone differential current of the connected busbar. When the number of the connected busbars on one side is greater than or equal to 2, the BC current will be counted into the discriminating zone differential current of the busbar of which the disconnector is closed. In addition, whether the BS current is counted into the discriminating zone differential current also needs to consider the dead zone fault protection function.

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The feeder TA is on the outside of the circuit breaker. The busbar can be connected to the QA1 side and the transfer bus can be connected to both sides of the TA1. The feeder current is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the feeder disconnector position and the circuit breaker position (feeder dead zone fault protection is enabled). Feeder The feeder TA is on the inside of the circuit breaker. The busbar

3

can be connected to the TA1 side and the transfer bus can be connected to both sides of the QA1. The feeder current is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the feeder disconnector position and the circuit breaker position (feeder dead zone fault protection is enabled).

It is used as the tie disconnector for the busbar, when it is closed, SwitchTie

the connected busbars of the tie disconnector will be considered as under the inter-linked operation mode automatically.

3.13.2 Typical Busbar Arrangement Description 1.

Single-busbar arrangement

The differential circuits include one check zone differential circuit and one discriminating zone differential circuit (Bus1), The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). 2.

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Single-busbar with transfer bus arrangement (the feeder TA is on the outside of the bypass disconnector)

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3 Protection Functions

3 The differential circuits include one check zone differential circuit and two discriminating zone differential circuits (Bus1 and Bus2), where Bus2 is the transfer bus. The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). The BC current will be counted into the discriminating zone differential current of Bus1 and Bus2, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. 3.

Single-busbar with transfer bus arrangement (the feeder TA is on the inside of the bypass disconnector)

The differential circuits include one check zone differential circuit and one discriminating zone differential circuit (Bus1), Bus2 is not within the protected zone of busbar differential protection. The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). In the case of non-bypass operation, the BC current is 0. In the case of the bypass operation, the BC current is counted into the check zone differential current and discriminating zone differential current of Bus1, and it is decided whether to be excluded from discriminating zone differential PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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3 Protection Functions

current calculation according to BC dead zone fault protection function. 4.

Single-busbar with bus section arrangement

3 The differential circuits include one check zone differential circuit and two discriminating zone differential circuits (Bus1 and Bus2). The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). The BS current will be counted into the discriminating zone differential current of Bus1 and Bus2, and it is decided whether to be excluded from discriminating zone differential current calculation according to BS dead zone fault protection function. 5.

Single-busbar with bus section arrangement (the feeder TA is on the outside of the bypass disconnector)

The differential circuits include one check zone differential circuit and three discriminating zone differential circuits (Bus1, Bus2 and Bus3), where Bus3 is the transfer bus. The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). The BS current will be counted into the discriminating zone differential current of the busbar of which the disconnector is closed, and it is decided whether to be excluded from discriminating zone differential current calculation according to BS dead zone fault protection function. 6.

Single-busbar with bus section arrangement (the feeder TA is on the inside of the bypass disconnector)

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The differential circuits include one check zone differential circuit and two discriminating zone differential circuits (Bus1 and Bus2), Bus3 is not within the protected zone of busbar differential protection. The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). In the case of non-bypass operation, the BC current is 0. In the case of the bypass operation, the BC current is counted into the check zone differential current and discriminating zone differential current of Bus1, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. 7.

Double-busbars arrangement

The differential circuits include one check zone differential circuit and two discriminating zone differential circuits (Bus1 and Bus2). The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). The BC current will be counted into the discriminating zone differential current of Bus1 and Bus2, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. 8.

Double-busbars arrangement (the feeder TA is on the outside of the bypass

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3

3 Protection Functions

disconnector)

3 The differential circuits include one check zone differential circuit and three discriminating zone differential circuits (Bus1, Bus2 and Bus3), where Bus3 is the transfer bus. The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). The current of the BC (Tie1) is counted into the discriminating zone differential current, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. The current of the BC (Tie2) is counted into the discriminating zone differential current of which the disconnector is closed, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. 9.

Double-busbars arrangement (the feeder TA is on the inside of the bypass disconnector)

The differential circuits include one check zone differential circuit and two discriminating zone differential circuits (Bus1 and Bus2), the transfer bus Bus3 is not within the protected zone of busbar differential protection. 3-102

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3 Protection Functions

The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). The current of the BC (Tie1) is counted into the discriminating zone differential current, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. In the case of non-bypass operation, the current of the BC (Tie2) is 0. In the case of the bypass operation, the current of the BC (Tie2) is counted into the check zone differential current and discriminating zone differential current of Bus1, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. 10. Double-busbars with one bus section arrangement

The differential circuits include one check zone differential circuit and three discriminating zone differential circuits (Bus1, Bus2 and Bus3). The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). The current of the BC (Tie1) is counted into the discriminating zone differential current of Bus1 and Bus2, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. The current of the BC (Tie2) is counted into the discriminating zone differential current of Bus2 and Bus3, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. The current of the BC (Tie3) is counted into the discriminating zone differential current of Bus1 and Bus3, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. 11. Double-busbars with two bus sections arrangement PCS-915SC Centralized Busbar Relay Date: 2019-03-11

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3 Protection Functions

3

The differential circuits include one check zone differential circuit and four discriminating zone differential circuits (Bus1, Bus2, Bus3 and Bus4). The current of each feeder is fixedly counted into the check zone differential current, and it will be counted into the discriminating zone differential current according to the disconnector position and the circuit breaker position of each bay (feeder dead zone fault protection is enabled). The current of the BC (Tie1) is counted into the discriminating zone differential current of Bus1 and Bus2, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. The current of the BC (Tie2) is counted into the discriminating zone differential current of Bus3 and Bus4, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. The current of the BC (Tie3) is counted into the discriminating zone differential current of Bus1 and Bus3, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function. The current of the BC (Tie4) is counted into the discriminating zone differential current of Bus2 and Bus4, and it is decided whether to be excluded from discriminating zone differential current calculation according to BC dead zone fault protection function.

3.14 Device Configuration Description The differential circuits of PCS-915SC include one check zone differential circuit and up to six discriminating zone differential circuits, it can protect up to six busbars. If busbar voltage is not connected, the device can connect up to 36 bays (108 AC current inputs). If busbar voltage is connected, the device can connect up to 32 bays (96 AC current inputs) and the voltage of up to 4 busbars (12 AC voltage inputs). The busbar relay PCS-915SC includes one central unit (CU, 6U chassis) and up to two extended units (EU, 6U chassis). If busbar voltage is not connected, the central unit can connect up to 12 bays (36 AC current inputs). If busbar voltage is connected, the central unit can connect up to 8 bays (24 AC current inputs) and the voltage of up to 4 busbars (12 AC voltage inputs). Each extended unit can connect up to 12 bays (36 AC current inputs). Please refer to following table for details. 3-104

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3 Protection Functions PCS-915SC

Analog input Busbar voltage is not connected

CU

36 AC current inputs

1CU+1EU

72 AC current inputs

1CU+2EU

108 AC current inputs

Busbar voltage is connected 24 AC current inputs +12 AC voltage inputs 60 AC current inputs +12 AC voltage inputs 96 AC current inputs +12 AC voltage inputs

Binary

Binary

input

output

265

141

434

197

503

253

The extended unit is connected to the central unit via the optical fiber (ST type connector), the communication between the CU and the EU adopts CRC check, which has high reliability. The fiber connection rules are as follows: The fiber port TX1 of the DSP module located in slot No.1 of EU1 → The fiber port RX1 of the DSP module located in slot No.2 of the CU The fiber port RX1 of the DSP module located in slot No.1 of EU1 → The fiber port TX1 of the DSP module located in slot No.2 of the CU The fiber port TX1 of the DSP module located in slot No.1 of EU2 → The fiber port RX2 of the DSP module located in slot No.2 of the CU The fiber port RX1 of the DSP module located in slot No.1 of EU2 → The fiber port TX2 of the DSP module located in slot No.2 of the CU All the protection logic is completed in the CU, and the EU is responsible for bay current and binary quantity acquisition, and the EU also realizes the tripping of the connected bays. It should be noted that the analog quantity and the binary quantity configuration of the EU are all completed during the DEVS project configuration of the CU. The following parameters need to be set in the EU. 1.

System frequency The system frequency of the EU needs to be consistent with that of the CU. Otherwise, the analog sampling of the CU and the analog sampling of the EU are not synchronized, it will cause a differential current.

2.

Logic setting for enabling/disabling the communication between the EU and the CU (BU_RX.En) If the logic setting is set as “0”, the EU will no longer receive the information sent by the CU.

3.

Binary input module related parameters Binary input power supply voltage, operating voltage percentage, drop-off percentage, monitoring window of binary input jitter processing, blocking window of binary input status change due to jitter, time threshold to block binary input status change due to jitter, time threshold to initiate immediately another blocking window of binary input status change due to continuous jitter, logic setting to enable the jitter processing function in case of binary input

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voltage variation, and power supply mode of binary input module. 4.

Clock synchronization related parameters Set the clock synchronization related parameters if necessary. These parameters only affect the display time of the device and will not affect the sampling synchronization between the EU and the CU.

3

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4 Measurement

4 Measurement Table of Contents 4.1 Overview ........................................................................................................... 4-1 4.2 Primary Values ................................................................................................. 4-1 4.2.1 General Values ..................................................................................................................... 4-1 4.2.2 Angle Values ......................................................................................................................... 4-1 4.2.3 Sequence Components Values ............................................................................................ 4-2

4.3 Secondary Values ............................................................................................ 4-3 4.3.1 General Values ..................................................................................................................... 4-3 4.3.2 Angle Values ......................................................................................................................... 4-3 4.3.3 Sequence Components Values ............................................................................................ 4-4

4.4 Function Values ............................................................................................... 4-4

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

4-a

4

4 Measurement

4

4-b

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4 Measurement

4.1 Overview This device performs continuous measurement of the analogue input quantities. The current full scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS value in each interval and updated the LCD display in every 0.5 second. The measurement data can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool. Navigate the menu to view the sampling value through LCD screen.

4.2 Primary Values 4.2.1 General Values Access path: MainMenu  “Measurements”  “Primary Values”  “General Values” No.

Symbol

Definition

Unit

1

Frequency

The system frequency

Hz

2

@BBx.Ua_Pri

Phase-A voltages of BBx

V

3

@BBx.Ub_Pri

Phase-B voltages of BBx

V

4

@BBx.Uc_Pri

Phase-C voltages of BBx

V

5

@Bayn.Ia_Pri

Phase-A currents of bay n

A

6

@Bayn.Ib_Pri

Phase-B currents of bay n

A

7

@Bayn.Ic_Pri

Phase-C currents of bay n

A

8

@Bayn.CT1.Ia_Pri

Phase-A currents of CT1 of bay n (for double-CT BC/BS)

A

9

@Bayn.CT1.Ib_Pri

Phase-B currents of CT1 of bay n (for double-CT BC/BS)

A

10

@Bayn.CT1.Ic_Pri

Phase-C currents of CT1 of bay n (for double-CT BC/BS)

A

11

@Bayn.CT2.Ia_Pri

Phase-A currents of CT2 of bay n (for double-CT BC/BS)

A

12

@Bayn.CT2.Ib_Pri

Phase-B currents of CT2 of bay n (for double-CT BC/BS)

A

13

@Bayn.CT2.Ic_Pri

Phase-C currents of CT2 of bay n (for double-CT BC/BS)

A

4.2.2 Angle Values Access path: MainMenu  “Measurements”  “Primary Values”  “Angle Values” When voltage is sampled by the device and phase A voltage of BB1 is larger than a certain value, the phase A voltage of BB1 will be taken as a reference; if the phase A voltage of BB1 is smaller than the certain value and the phase A voltage of BB2 is larger than the certain value, the phase A voltage of BB2 will be taken as a reference; and so forth. When voltage is not sampled by the device, if the currents of some feeder are larger than a certain value, the phase A current of the feeder (takes the feeder whose number is minimal) will be taken as a reference.

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4-1

4

4 Measurement No.

Symbol

Definition

Unit

If the phase A voltage of BBx is taken as a reference, the displayed value of “AngRef” is “x”, If phase A voltage of all busbars are all smaller than a 1

certain value, the displayed value of “AngRef” is “0”.

AngRef

If the phase A current of feeder m is taken as a reference, the displayed

°

value of “AngRef” is “m” (m=01, 02, 03, ……), if all the currents are smaller than a certain value, the displayed value of “AngRef” is “0”.

4

2

@BBx.Ang(Ua)

Phase-A angle of voltage of BBx

°

3

@BBx.Ang(Ub)

Phase-B angle of voltage of BBx

°

4

@BBx.Ang(Uc)

Phase-C angle of voltage of BBx

°

5

@Bayn.Ang(Ia)

Phase-A angle of current of bay n

°

6

@Bayn.Ang(Ib)

Phase-B angle of current of bay n

°

7

@Bayn.Ang(Ic)

Phase-C angle of current of bay n

°

8

@Bayn.CT1.Ang(Ia)

Phase-A angle of current of CT1 of bay n (for double-CT BC/BS)

°

9

@Bayn.CT1.Ang(Ib)

Phase-B angle of current of CT1 of bay n (for double-CT BC/BS)

°

10

@Bayn.CT1.Ang(Ic)

Phase-C angle of current of CT1 of bay n (for double-CT BC/BS)

°

11

@Bayn.CT2.Ang(Ia)

Phase-A phase angle of current of CT2 of bay n (for double-CT BC/BS)

°

12

@Bayn.CT2.Ang(Ib)

Phase-B phase angle of current of CT2 of bay n (for double-CT BC/BS)

°

13

@Bayn.CT2.Ang(Ic)

Phase-C phase angle of current of CT2 of bay n (for double-CT BC/BS)

°

4.2.3 Sequence Components Values Access path: MainMenu  “Measurements”  “Primary Values” “SeqComponent Values” No.

Symbol

Definition

Unit

1

@BBx.Uab_Pri

Phase-to-phase voltage (Uab) of BBx

kV

2

@BBx.Ubc_Pri

Phase-to-phase voltage (Ubc) of BBx

kV

3

@BBx.Uca_Pri

Phase-to-phase voltage (Uca) of BBx

kV

4

@BBx.U2_Pri

Negative-sequence voltage of BBx

kV

5

@BBx.3U0_Cal_Pri

The calculated residual voltage of BBx

kV

6

@Bayn.I2_Pri

Negative-sequence current of bay n

A

7

@Bayn.CT1.I2_Pri

Negative-sequence current of CT1 of bay n (for double-CT BC/BS)

A

8

@Bayn.CT2.I2_Pri

Negative-sequence current of CT2 of bay n (for double-CT BC/BS)

A

9

@Bayn.3I0_Cal_Pri

The calculated residual current of bay n

A

10

@Bayn.CT1.3I0_Cal_Pri

The calculated residual current of CT1 of bay n (for double-CT BC/BS)

A

11

@Bayn.CT2.3I0_Cal_Pri

The calculated residual current of CT2 of bay n (for double-CT BC/BS)

A

4-2

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4 Measurement

4.3 Secondary Values 4.3.1 General Values Access path: MainMenu  “Measurements”  “Secondary Values”  “General Values” No.

Symbol

Definition

Unit

1

Frequency

The system frequency

Hz

2

@BBx.Ua_Sec

Phase-A voltages of BBx

V

3

@BBx.Ub_Sec

Phase-B voltages of BBx

V

4

@BBx.Uc_Sec

Phase-C voltages of BBx

V

5

@Bayn.Ia_Sec

Phase-A currents of bay n

A

6

@Bayn.Ib_Sec

Phase-B currents of bay n

A

7

@Bayn.Ic_Sec

Phase-C currents of bay n

A

8

@Bayn.CT1.Ia_Sec

Phase-A currents of CT1 of bay n (for double-CT BC/BS)

A

9

@Bayn.CT1.Ib_Sec

Phase-B currents of CT1 of bay n (for double-CT BC/BS)

A

10

@Bayn.CT1.Ic_Sec

Phase-C currents of CT1 of bay n (for double-CT BC/BS)

A

11

@Bayn.CT2.Ia_Sec

Phase-A currents of CT2 of bay n (for double-CT BC/BS)

A

12

@Bayn.CT2.Ib_Sec

Phase-B currents of CT2 of bay n (for double-CT BC/BS)

A

13

@Bayn.CT2.Ic_Sec

Phase-C currents of CT2 of bay n (for double-CT BC/BS)

A

4.3.2 Angle Values Access path: MainMenu  “Measurements”  “Secondary Values”  “Angle Values” No.

Symbol

Definition

Unit

If the phase A voltage of BBx is taken as a reference, the displayed value of “AngRef” is “x”, If phase A voltage of all busbars are all smaller than a 1

AngRef

certain value, the displayed value of “AngRef” is “0”. If the phase A current of feeder m is taken as a reference, the displayed

°

value of “AngRef” is “m” (m=01, 02, 03, ……), if all the currents are smaller than a certain value, the displayed value of “AngRef” is “0”. 2

@BBx.Ang(Ua)

Phase-A angle of voltage of BBx

°

3

@BBx.Ang(Ub)

Phase-B angle of voltage of BBx

°

4

@BBx.Ang(Uc)

Phase-C angle of voltage of BBx

°

5

@Bayn.Ang(Ia)

Phase-A angle of current of bay n

°

6

@Bayn.Ang(Ib)

Phase-B angle of current of bay n

°

7

@Bayn.Ang(Ic)

Phase-C angle of current of bay n

°

8

@Bayn.CT1.Ang(Ia)

Phase-A angle of current of CT1 of bay n (for double-CT BC/BS)

°

9

@Bayn.CT1.Ang(Ib)

Phase-B angle of current of CT1 of bay n (for double-CT BC/BS)

°

10

@Bayn.CT1.Ang(Ic)

Phase-C angle of current of CT1 of bay n (for double-CT BC/BS)

°

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4-3

4

4 Measurement No.

Symbol

Definition

Unit

11

@Bayn.CT2.Ang(Ia)

Phase-A phase angle of current of CT2 of bay n (for double-CT BC/BS)

°

12

@Bayn.CT2.Ang(Ib)

Phase-B phase angle of current of CT2 of bay n (for double-CT BC/BS)

°

13

@Bayn.CT2.Ang(Ic)

Phase-C phase angle of current of CT2 of bay n (for double-CT BC/BS)

°

4.3.3 Sequence Components Values Access path: MainMenu  “Measurements”  “Secondary Values”  “SeqComponent Values” No.

4

Symbol

Definition

Unit

1

@BBx.Uab

Phase-to-phase voltage (Uab) of BBx

V

2

@BBx.Ubc

Phase-to-phase voltage (Ubc) of BBx

V

3

@BBx.Uca

Phase-to-phase voltage (Uca) of BBx

V

4

@BBx.U2

Negative-sequence voltage of BBx

V

5

@BBx.3U0_Cal

The calculated residual voltage of BBx

V

6

@Bayn.I2

Negative-sequence current of bay n

A

7

@Bayn.CT1.I2

Negative-sequence current of CT1 of bay n (for double-CT BC/BS)

A

8

@Bayn.CT2.I2

Negative-sequence current of CT2 of bay n (for double-CT BC/BS)

A

9

@Bayn.3I0_Cal

The calculated residual current of bay n

A

10

@Bayn.CT1.3I0_Cal

The calculated residual current of CT1 of bay n (for double-CT BC/BS)

A

11

@Bayn.CT2.3I0_Cal

The calculated residual current of CT2 of bay n (for double-CT BC/BS)

A

4.4 Function Values Access path: MainMenu  “Measurements”  “Function Values”  “DiffCurr Values” No.

Sign

Description

Unit

1

Ida_CZ

Phase-A check zone differential current

A

2

Idb_CZ

Phase-B check zone differential current

A

3

Idc_CZ

Phase-C check zone differential current

A

4

@BBx.Ida

Phase-A discriminating zone differential current of BBx

A

5

@BBx.Idb

Phase-B discriminating zone differential current of BBx

A

6

@BBx.Idc

Phase-C discriminating zone differential current of BBx

A

7

@BBx.Ira

Phase-A discriminating zone restraint current of BBx

A

8

@BBx.Irb

Phase-B discriminating zone restraint current of BBx

A

9

@BBx.Irc

Phase-C discriminating zone restraint current of BBx

A

10

@Bayn.Ia_Conv

Phase-A currents of bay n

the current

11

@Bayn.Ib_Conv

Phase-B currents of bay n

12

@Bayn.Ic_Conv

Phase-C currents of bay n

4-4

have

A

been

converted

A

according

to

A

that

the

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

4 Measurement No.

Sign

13

@Bayn.CT1.Ia_Conv

14

@Bayn.CT1.Ib_Conv

15

@Bayn.CT1.Ic_Conv

16

@Bayn.CT2.Ia_Conv

17

@Bayn.CT2.Ib_Conv

18

@Bayn.CT2.Ic_Conv

Description Phase-A currents of CT1 of bay n (for double-CT BC/BS) Phase-B currents of CT1 of bay n (for double-CT BC/BS) Phase-C currents of CT1 of bay n (for double-CT BC/BS) Phase-A currents of CT2 of bay n (for double-CT BC/BS) Phase-B currents of CT2 of bay n (for double-CT BC/BS) Phase-C currents of CT2 of bay n (for double-CT BC/BS)

PCS-915SC Centralized Busbar Relay Date: 2019-03-11

Unit referenced CT ratio

A

A

A

A

A

A

4

4-5

4 Measurement

4

4-6

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5 Supervision

5 Supervision Table of Contents 5.1 Overview ........................................................................................................... 5-1 5.2 Device Hardware Supervision ........................................................................ 5-1 5.2.1 Hardware Resource Consumption Supervision ................................................................... 5-1 5.2.2 Hardware Status Supervision ............................................................................................... 5-2 5.2.3 Hardware Configuration Supervision ................................................................................... 5-3 5.2.4 Device Firmware Supervision .............................................................................................. 5-3 5.2.5 CPU Process and Module Supervision ................................................................................ 5-3

5.3 Analog Input Supervision ............................................................................... 5-3 5.4 Secondary Circuit Supervision....................................................................... 5-4 5.5 Binary Input Supervision ................................................................................ 5-4 5.5.1 Debounce Time .................................................................................................................... 5-4 5.5.2 Jitter Processing ................................................................................................................... 5-6

5.6 Circuit Breaker Supervision ........................................................................... 5-8 5.7 Supervision Alarms and Handling Suggestion ............................................. 5-9

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5-a

5

5 Supervision

5

5-b

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5 Supervision

5.1 Overview Protection system is in quiescent state under normal conditions, and it is required to respond promptly for faults occurred on power system. When the device is in energizing process before the LED “HEALTHY” is on, the device need to be checked to ensure no abnormality. Therefore, the automatic supervision function, which checks the health of the protection system when startup and during normal operation, plays an important role. The numerical relay based on the microprocessor operations is suitable for implementing this automatic supervision function of the protection system. In case a defect is detected during initialization when DC power supply is provided to the device, the device will be blocked with indication and alarm of relay out of service. It is suggested a trial recovery of the device by re-energization. Please contact supplier if the device is still failure. When a failure is detected by the automatic supervision, it is followed by a LCD message, LED indication and alarm contact outputs. The failure alarm is also recorded in event recording report and can be printed if required.

5

5.2 Device Hardware Supervision All hardware has real-time monitoring functions, such as CPU module monitoring, communication interface status monitoring, power supply status monitoring. The monitoring function of CPU module also includes processor self-check, memory self-check and so on. The processor self-check is checked by designing execution instructions and data operations. Check whether the processor can execute all instructions correctly, and whether it can correctly calculate complex data operations to determine whether it works normally. For peripherals, it can monitor the status of the interface module, check the input and output data, send the communication interface and receive self-loop detection. Memory self-check is used to detect unexpected memory errors in the running process. It can effectively prevent program logic abnormality caused by memory errors. The status monitoring of communication interface also includes Ethernet communication interface monitoring and differential channel communication interface monitoring. By accessing the status register of the communication interface, the state of the corresponding interface is obtained, such as the state of connection, the number of sending frames, the number of frames received, and the number of wrong frames. According to the statistics of the acquired interface state, it is judged whether the interface work is abnormal. The hardware supervision also includes the power supply status monitoring. The voltage monitoring chip is used by all the power supplies. The reset voltage threshold is preset to the reset monitoring circuit. When the power supply is abnormal, the voltage monitoring chip will output the reset signal to control CPU to be in the reset state and avoid the wrong operation.

5.2.1 Hardware Resource Consumption Supervision 1.

Logic component total execution time monitoring

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5 Supervision

In the process of operation, the safety allowance should always be kept and no overload phenomenon is allowed. When the user configures logic components with PCS-Studio, the PCS-Studio automatically calculates the time required for the theoretical execution of the configured components. When the security limit is exceeded, the PCS-Studio will indicate that the configuration error is not allowed to download the current configuration to the device. 2.

Module data exchange monitoring

During the operation of the device, there is a lot of data exchange between modules. The number of data exchanges is related to the number of logical components configured by the user. When the configuration is too large to cause the number of data exchange to exceed the upper limit supported by the device, the PCS-Studio prompts the configuration error. 3.

Configuration file size monitoring

The initialization of the device depends on the configuration files of each module. The user configured logical components will eventually be embodied in the configuration file, limited to the hardware memory space. When the configuration file size is more than the upper limit, the PCS-Studio prompts the configuration error.

5

5.2.2 Hardware Status Supervision 1.

Memory ECC and parity functions.

The DDR3 memory chip has the function of ECC (Error Checking and Correcting) to eliminate unexpected changes in memory caused by electromagnetic interference. The chip memory has parity function. When an error occurs, the system can detect anomalies immediately, and eliminate the logic abnormity caused by memory errors. 2.

Memory error monitoring in code area and constant data area

In addition to the above hardware memory reliability measures, the device software is also constantly checking the memory during operation, including code, constant data, and so on. Once the error detection, the system will automatically restart the restore operation. If they detect the error immediately after the restart, it may be the result of a permanent fault locking device hardware, only at the moment and not restart. 3.

Binary output relay drive monitoring

The reliability of the device is largely determined by the reliability of the export drive. By reading the driving state of the binary output relay, the alarm signal will be generated and the device is immediately blocked to prevent the relay from mal-operation when the device is not given a tripping order and the binary output relay driver is detected in the effective state. 4.

CPU temperature monitoring

The CPU chip needs to be able to ensure long-term stability under the permissible working temperature of the specification. Therefore, it is necessary to monitor the working temperature monitored by CPU.

5-2

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5 Supervision

5.2.3 Hardware Configuration Supervision The device is blocked when the actual hardware configuration is not consistent with the hardware configuration file. Compared with pre configured modules, this device will be blocked if more modules are inserted, fewer modules are inserted, and wrong modules are inserted.

5.2.4 Device Firmware Supervision 1.

Each hardware module configuration check code needs to be consistent with CPU module.

The device CPU module stores the configuration check codes of other modules. In initialization procedure, it checks whether the configuration check code of each module is consistent with the stored code in CPU module, and if it is not consistent, this device is blocked. The hardware modules and process interface versions need to be consistent with the CPU module. 2.

If the system is incompatible with the upgrade, it will upgrade the internal interface version. At this moment, each hardware module and process will be upgraded synchronously, otherwise the version of the interface will be inconsistent. 3.

Configuration text is correct.

The configuration text formed by the device calibration visualization project includes checking whether the check code is wrong or not. 4.

Whether any setting is over the range, whether it needs to confirm the settings.

If the setting exceeds the configuration range, the device is blocked; if some settings are added, it is necessary to confirm the new values through the LCD.

5.2.5 CPU Process and Module Supervision 1.

Monitor the heartbeat of the module.

In the operation procedure, the CPU module sends a time synchronization command to other module, each module repeats heartbeat message to the CPU module, if it does not respond or the heartbeat is abnormal, then this device is blocked. 2.

Check whether the settings of other modules are consistent with the CPU module.

The actual values of all the settings in the CPU module are initialized to send to the corresponding slave modules. In the process of operation, the setting values stored in the CPU module and the setting values of other modules will be checked one by one. If they are not consistent, this device will issue the alarm signal [Fail_Settings].

5.3 Analog Input Supervision The sampling circuit of this device is designed as dual-design scheme. Each analog sampling channel is sampled by two groups of ADC. The sampling data is self checking and inter checking in real time. If any sampling circuit is abnormal, the device reports the alarm signal [Fail_Sample], PCS-915SC Centralized Busbar Relay Date: 2019-03-11

5-3

5

5 Supervision

and the protection function related to the sampling channel is disabled at the same time. When the sampling circuit returns to normal state, the related protection is not blocked after 10s.

5.4 Secondary Circuit Supervision The secondary circuit supervision function includes current transformer supervision (CTS), voltage transformer supervision (VTS), and binary inputs power supply supervision. 

CTS function

The purpose of the CTS function is to detect whether the current transformer circuit is failed. In some cases, if the CT is failed (broken-conductor, short-circuit), related protective element should be blocked for preventing this device from mal-operation. Please refer to Chapter 3 about the details about the CTS function. 

5

VTS function

The purpose of the VTS function is to detect whether the VT analog input is normal. Some voltage related function will be influenced by voltage input failure. The VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault, poor contact of VT circuit, VT maintenance and so on. The device can detect the failure, and then issue an alarm signal and block relevant function. Please refer to Chapter 3 about the details about the VTS function.

5.5 Binary Input Supervision 5.5.1 Debounce Time The well-designed debounce technique is adopted in this device, and the state change of binary input within “Debounce time” will be ignored. As shown in Figure 5.5-1. All binary inputs should setup necessary debounce time to prevent the device from undesired operation due to transient interference or mixed connection of AC system and DC system. When the duration of binary input is less than the debounce time, the state of the binary input will be ignored. When the duration of binary input is greater than the debounce time, the state of the binary input will be validated and wrote into SOE.

5-4

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5 Supervision

Binary input state SOE report timestamps

SOE report timestamps Validated binary input state changes

1

Validated binary input state changes

0

Debounce time of delayed pickup

Debounce time of delayed dropout

Time

Figure 5.5-1 Sequence chart of debounce technique

All binary inputs should setup necessary debounce time to prevent the device from undesired operation due to transient interference or mixed connection of AC system and DC system. When the duration of binary input is less than the debounce time, the state of the binary input will be ignored. When the duration of binary input is greater than the debounce time, the state of the binary input will be validated and wrote into SOE. In order to meet flexible configurable requirement for different project field, all binary inputs provided by the device are configurable. Through the configuration tool, this device provides two parameters to setup debounce time of delayed pickup and dropout based on specific binary signal.

Figure 5.5-2 Debounce time configuration page

The configurable binary signals can be classified as follows: 1.

Type 1 This type of binary inputs includes enable/disable of protection functions, AR mode selection, “BI_RstTarg”, “BI_Maintenance”, disconnector position, settings group switch, open and close command of circuit breaker and disconnector, enable/disable of auxiliary functions (for example, manually trigger recording). They are on the premise of reliability, and the

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5

5 Supervision

debounce time of delayed pickup and delayed dropout is recommended to set as 100ms at least. 2.

Type 2 This type of binary inputs include breaker failure initiating binary input and so on. Debounce time BI

t1

Input Signal.X1

t2

& Time delay

Output

SIG Operation condition



Time delay is equal to 0 The debounce time of delayed pickup and delayed dropout is recommended to set as 15ms, in order to prevent binary signals from mal-operation due to mixed connection of AC system and DC system.



5

Time delay is not equal to 0 The debounce time of delayed pickup and delayed dropout is recommended to set as (-t1+ t2+Time delay)≥15ms, in order to prevent binary signals from mal-operation due to mixed connection of AC system and DC system. Where, “t1” is the debounce time of delayed pickup, and “t2” is the debounce time of delayed dropout.

3.

Type 3 This type of binary inputs is usually used as auxiliary input condition, and the debounce time of delayed pickup and delayed dropout is recommended to set as 5ms.

When users have their own reasonable setting principles, they can set the debounce time related settings according to their own setting principles.

5.5.2 Jitter Processing This device can handle repetitive signal or so-called jitter via binary input module with the following settings: [Mon_Window_Jitter]

T, monitoring window of binary input jitter processing

[Num_Blk_Jitter]

N, times threshold to block binary input status change due to jitter

[Blk_Window_Jitter]

T', blocking window of binary input status change due to jitter

[Num_Reblk_Jitter]

N', times threshold to initiate immediately another blocking window of binary input status change due to continuous jitter

For a binary input voltage variation, if the jitter processing function is enabled, its handling 5-6

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5 Supervision

principle is: 1.

2.

During the T, 

If the actual jitter times < N, the block will not be initiated and the status change of this binary input will be considered.



If the actual jitter times ≥ N, the T' is initiated, and the status change of binary input will be ignored during the T'.

During the T', 

If the actual jitter times < N', the block window will expire. The final status of this binary input will be compared to the original one before T', so as to determine whether there is a change or not.



If the actual jitter times ≥ N', the T' will be initiated again immediately (i.e. restart the timer), and the status change of binary input will be ignored during the next T'.

An example of jitter processing is shown in the following sequence chart: Input voltage level

Debounce time (falling edge)

5

Debounce time (rising edge)

Jitter blocking flag n=N initiate jitter block

Signal after debounce & jitter processing

n=N Prolong blocking window

n=5