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Laptop Chip Level Repair Guide

Contents: Chapter 1: The Introduction of Laptop Repair 1.1 The Level of Laptop Computer Maintenance/Repair ……………………..12 1.2 The Basic Knowledge You Must Know Before Starting to Repair Laptop.14

Chapter 2: Original & OEM Laptop Mainboard Part Numbers 2.1 Quanta …………………………………………………………………….17 2.2 Compal ……………………………………………………………………18 2.3 Wistron ……………………………………………………………………19 2.4 Inventec …………………………………………………………………...19 2.5 Pegatron …………………………………………………………………...20 2.6 Samsung …………………………………………………………………...21 2.7 Apple ………………………………………………………………………22 2.8 Other Manufacturers ……………………………………………………....22

Chapter 3: The Architecture of The Laptop Mainboard 3.1 The Architecture of Intel Double Bridges (GM/PM45 and below) .... .......25 3.2 The Architecture of Intel Single Bridge (above HM55)..............................26 3.3 The Architecture of AMD Double Bridges (RS780)...................................29 3.4 The Architecture of AMD Single Bridge (A70).......................................... 29 3.5 The Architecture of nVIDIA Double Bridges (C51M)................................30 3.6 The Architecture of nVIDIA Single Bridge (MCP67)................................ 30

Chapter 4: The Explanation of Nouns and Common Concepts of Laptop Maintenance 4.1 Power Supply and Signal............................................................................. 35 4.2 High Level and Low Level...........................................................................37 4.3 Jump and Pulse.......................................................................................... ..37 4.4 The Clock Signal..........................................................................................38

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Laptop Chip Level Repair Guide 4.5 Reset Signal................................................................................................. 39 4.6 Power Good Signal.................................................................................... ..39 4.7 Open Signal (Start-up Signal) ……..............................................................40 4.8 Chip Select Signal.........................................................................................41 4.9 The Explanation of The Signal Name/Symbol for Laptop Mainboard Manufactures………..………………………………………………………... 41

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4.9.1 Wistron........................................................................................... 41 4.9.2 Quanta..............................................................................................43 • 4.9.3 Asus.................................................................................................45 • 4.9.4 Compal............................................................................................48 • 4.9.5 DELL...............................................................................................49 • 4.9.6 Apple...............................................................................................51 • 4.9.7 Inventec...........................................................................................52 • 4.9.8 ThinkPad (IBM)..............................................................................53

Chapter 5: The Basic Application Circuit of Electronic Components 5.1 The Basic Application Circuit of Capacitor.................................................57 5.2 The Basic Application Circuit of The Resistance .......................................59 5.3 The Basic Application Circuit of The Diode................................................62 5.4 The Basic Application Circuit of Transistor.................................................66 5.5 The Basic Application Circuit of The Field-Effect Tube (MOSFET)......... 68 5.6 The Basic Application Circuit of The Gate Circuit......................................69 5.7 The Basic Application Circuit of The Comparator.......................................71 5.8 The Basic Application Circuit of The Converter..........................................72 5.9 The Basic Application Circuit of The Voltage Regulator............................73

Chapter 6: The Use of the Circuit Diagram and the Point Bitmap (BoardView) 6.1 The Use of The Circuit Diagram..................................................................75 6.2 The Use of The Common Point Bitmap (BoardView Software) .................80

Chapter 7: Introduction of EC and BIOS…89 7.1 The Working Conditions and Functions of EC............................................91 7.2 The Functions and Working Conditions of BIOS........................................94

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Laptop Chip Level Repair Guide Chapter 8: The Basic Working Process of Laptop Computer 8.1 The general process of Laptop computer................................................... 101 8.1.1 Hard Starting Process and Intel Chipset Standard Timing......................102 8.1.2 The Soft Start Process..............................................................................107 8.2 About ACPI Specification..........................................................................111 8.2.1 ACPI Summarize.....................................................................................111 8.2.2 G (Global) State of ACPI.........................................................................112 8.2.3 D (Device) State of ACPI........................................................................112 8.2.4 S (Sleeping) State of ACPI......................................................................113 8.2.5 C State of ACPI.......................................................................................114 8.2.6 The Power and The Control Signal of ACPI...........................................115 8.3 Clock, PWRGD and The Reset Circuit......................................................116 8.3.1 The Clock Circuit.....................................................................................116 8.3.2 PWRGD and The Reset Circuit...............................................................122

Chapter 9: The Explanation of PWM Circuit 9.1 The Introduction of PWM Circuit..............................................................126 9.1.1 Introduction to PWM Working Principle ……………….......................126 9.1.2 The Meaning of Common English Abbreviation in PWM Circuit. ........130 9.1.3 The Boot-Strap Circuit ............................................................................130 9.1.4 Output Voltage Regulation Circuit .........................................................132 9.1.5 The Voltage Detection Circuit.................................................................132 9.1.6 The Current Detection Circuit.................................................................134 9.1.7 The Working Mode..................................................................................135 9.2 Analysis of The Standby Power Chip.........................................................137 9.2.1 Analysis of MAX8734A..........................................................................137 9.2.2 Analysis of TPS51125.............................................................................148 9.2.3 Analysis of RT8206A/RT8206B.............................................................155 9.3 Analysis of The Memory Power Supply Chip............................................162 9.3.1 Analysis of ISL88550A...........................................................................162 9.3.2 Analysis of RT8207.................................................................................168 9.4 Analysis of the Bridge/BUS Power Supply Chip.......................................172 9.4.1 Analysis of The Single PWM Controller RT8209...................................172 9.4.2 Analysis of The Dual PWM Controller TPS51124.................................175 9.5 Analysis of CPU Core Power Supply.........................................................178 9.51 The Features of CPU VCORE Power Supply..........................................178 9.5.2 Analysis of MAX8770.............................................................................180 9.5.3 Analysis of ISL6260................................................................................192 9.5.4 Analysis of Commonly Used Chip ISL95831 by HM65 Mainboard .....200 9.5.5 Analysis of Commonly Used Chip ISL6265 by AMD Platform ............215

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Laptop Chip Level Repair Guide

Chapter 10: Analysis of Quanta OEM Laptop Mainboard Circuit 10.1 Analysis of Quanta CT6 RTC Circuit.......................................................225 10.2 Analysis of Quanta CT6 Protective Isolation Circuit...............................227 10.3 Analysis of Quanta CT6 Power-On Sequence Circuit.............................232 10.4 Analysis of Quanta ZQ5 (Acer as4733z) Protective Isolation Circuit….250 10.5 Analysis of Quanta AX1 Protective Isolation Circuit..............................255

Chapter 11: Analysis of Wistron OEM Laptop Mainboard Circuit 11.1 Analysis of Wistron HBU16-1.2 Protective Isolation Circuit..................261 11.2 Analysis of Wistron HBU16-1.2 Standby Circuit....................................267

Chapter 12: Analysis of Compal OEM Laptop Mainboard Circuit 12.1 Analysis of Compal LA-5891P Protective Isolation and The Standby Circuit...............................................................................................................274 12.2 Analysis of Compal LA-6631P Protective Isolation Circuit....................290 12.3 Analysis of Compal LA-6751P Protective Isolation Circuit....................295

Chapter 13: Analysis of Inventec OEM Laptop Mainboard Circuit 13.1 Analysis of Inventec DosXX Dunkel 1.0 Protective Isolation Circuit.....300 13.2 Analysis of Inventec DosXX Dunkel 1.0 Standby Circuit.......................305 13.3 Analysis of Inventec Feature Circuit........................................................309 13.3.1 Analysis of OCP Circuit .......................................................................309 13.3.2 Analysis of Big OR GATE Circuit........................................................316

Chapter 14: Analysis of INTEL PCH Power on Sequence (i3/i5/i7) 14.1 About Intel ME and Intel AMT................................................................319 14.2 Analysis of Intel HM55 Series Chipset Timing Sequence.......................325 14.3 Analysis of The Chipset Timing Sequence Above Intel HM65 Series ……………………….…………………………………………….......328

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Laptop Chip Level Repair Guide Chapter 15: Analysis of ASUS K42JR (HM5x) Timing Sequence 15.1 The Standby State ....................................................................................333 15.2 Trigger......................................................................................................346 15.3 The Boot State..........................................................................................347 15.4 Clock, PG and Reset ................................................................................359

Chapter 16: Analysis of Apple A1286 (HM5x) Timing Sequence 16.1 G3 State....................................................................................................362 16.2 RTC Circuit.............................................................................................. 370 16.3 S5 State.....................................................................................................371 16.4 Trigger......................................................................................................378 16.5 S3 and S0 State........................................................................................ 379 16.6 The Clock, PG and The Reset.................................................................. 393

Chapter 17: Analysis of DELL N4110 (HM6x) Timing Sequence 17.1 G3 State.................................................................................................... 398 17.2 Trigger..................................................................................................... 408 17.3 The Standby and The Memory Power Supply of The Bridge..................408 17.4 S0 state......................................................................................................411 17.5 PG and The Clock.....................................................................................416 17.6 CPU Core Power Supply..........................................................................419 17.7 Reset..........................................................................................................424 17.8 The Graphic Card Power Supply..............................................................425

Chapter 18: Analysis of ThinkPad (IBM) T410 Timing Sequence 18.1 G3 State.....................................................................................................427 18.2 S5 State.....................................................................................................442 18.3 AMT..........................................................................................................451 18.4 Trigger......................................................................................................455 18.5 S3 and S0 State........................................................................................ 456 18.6 The Clock, PG and Reset......................................................................... 463 18.7 The Battery Charge Circuit.......................................................................468

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Laptop Chip Level Repair Guide Chapter 19: Analysis of AMD Platform Timing Sequence 19.1 The Standard Timing Sequence of nVIDIA.............................................478 19.2 The Explanation of nVIDIA Chipset Timing Sequence (MSI MS16352)……………………………………………………………………….. 481 19.3 The Standard Timing Sequence of AMD Chipset....................................501 19.4 The Timing Sequence of AMD Chipset (ACER 4235, Quanta ZQE)......503 19.5 The Explanation of AMD A70M (Lenovo G485, Compal LA-8681P)...506 19.5.1 RTC Circuit............................................................................................506 19.5.2 Protective Isolation Circuit....................................................................508 19.5.3 The Standby Power Supply................................................................... 512 19.5.4 The Trigger Switch............................................................................... 519 19.5.5 Produce Power Supply...........................................................................521 19.5.6 APU Power Supply................................................................................528 19.5.7 Clock, PG and Reset..............................................................................529 19.5.8 The Independent Graphics Working Timing Sequence.........................534

Chapter 20: Analysis of the Laptop Battery Charging Circuit 20.1 Analysis of Charging Chip MAX1772 Used Usually Under Intel 1965GM Platform ……………………………………………………………………...542 20.1.1 The Name and The Definition of The Pin............................................ 543 20.1.2 Application Circuit............................................................................... 546 20.2 Analysis of The Charging Chip ISL88731 Used Usually by The Intel GM45…………………………………………………...…………………… 549 20.2.1 The Name and The Pin Definition of ISL88731................................... 550 20.2.2 The Typical Application Diagram.........................................................553

Chapter 21: Maintenance of Common Failures 21.1 Short Trouble (Short Circuit Problem) ...................................................556 21.2 Do Not Trigger Fault................................................................................560 21.3 Power Down Fault................................................................................... 564 21.4 Not Running Fault (NO Error Code) ...................................................... 567 21.5 The Maintenance of Common Code........................................................ 574 21.6 The Screen Shows Fault...........................................................................581 21.7 The Sound Card Fault.............................................................................. 587 21.8 USB Fault................................................................................................ 591 21.9 The Network Card Fault...........................................................................592 21.10 SATA Interface Fault............................................................................. 595 21.11 The Fan Interface Fault...........................................................................597 21.12 Crash Fault..............................................................................................599 http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide Chapter 22: Example of Maintenance (Laptop Repair Cases) 22.1 The example of maintenance about don't boot fault Example 1 IBM T61 cannot boot.................................................................... 600 Example 2 Lenovo G480 inflow water, which cause cannot boot.................. 602 Example 3 lightning strike cause the Lenovo Z360 does not boot.................. 605 Example 4 IBM R60 no standby.................................. ................................... 610 Example 5 ASUS A42J with multiple fault..................................................... 615 Example 6 ASUS K42JR no standby...............................................................619 Example 7 Acer Aspire 4738G powered off....................................................620 Example 8 ASUS K42JR Powered off.............................................................622 Example 9 SONY NS90HS cannot boot after lightning strike........................ 624 Example 10 Lenovo Xuri 410M power off......................................................626 Example 11 DELL N4030 I3 not trigger......................................................... 628 Example 12 Toshiba L500 cannot boot........................................................... 631 Example 13 Samsung R23 cannot boot........................................................... 638 22.2 The example of the breakdown maintenance about not bright Example 14 Lenovo G460 do not run code..................................................... 641 Example 15 DELL V130 no display after powering on.................................. 644 Example 16 Samsung R428 no display after powering on.............................. 645 Example 17 Inventec HP511 no display and powered down...........................648 Example 18 eMachines D725 inflow water, which cause no light...................651 Example 19 Lenovo G470 no CPU voltage..................................................... 654 Example 20 Lenovo Y430 no clock and no display ....................................... 656 Example 21 Acer 5750G starting up but not display....................................... 657 22.3 The fault maintenance examples of power down Example 22 used the oscilloscope to repair the fault of power down of Lenovo G450 ……………………………………………………………………..…..659 Example 23 Lenovo G550 the standby is abnormal and power down............ 661 Example 24 HP 4411S power down when enter into the system.................... 664 Example 25 Acer Aspire 4310 power down.................................................... 667 Example 26 Lenovo Zhao yang E43G power down after triggering............... 671 Example 27 HP 510 power down repeatedly and restart after starting up.......672 Example 28 Lenovo V450 power down when stating up................................ 674 Example 29 HP 4411 Power down repeatedly after starting up...................... 676 22.4 The maintenance examples of other faults Example 30 ASUS A8E large short circuit when install battery..................... 678 Example 31 Lenovo s10.2 dark screen ........................................................... 682 http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide

BONUSES: 1) How to Clear ME Region (Intel Management Engine Fix Tutorial). 2) Bypass Discrete Graphic Chip and change to UMA Graphic type. System will more stable and save battery. 3) Laptop Mainboard BoardView Software and their Schematic Diagrams. Note: The above Bonuses information was inside the Bonus Page not inside this ebook. So you can download all these valuable information from Bonus Page there.

You CANNOT give this E-book away for free. You do not have the rights to redistribute this Ebook in internet or no matter where it is.

Copyright @ All Rights Reserved Warning! No part of this E-book/guide may be reproduced or transmitted in any form whatsoever, electronic, or mechanical, including photocopying, printing, recording, or transmitting by any informational storage or retrieval system without expressed written, dated and signed permission from the author. You cannot alter, change, or repackage this document in any manner.

Disclaimer And/ Or Legal Notices The reader is expressly warned to consider and adopt all safety precaution that might be indicated by the activities herein and to avoid all potential hazards. http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide This E-Book is for INFORMATIONAL PURPOSES only and the author do not accept any responsibilities or liabilities resulting from the use of this information. While every attempt has been made to verify the information provided here, the author cannot assume any responsibility for any loss, injury, errors, inaccuracies, omissions or inconvenience sustained by anyone resulting from this information. Most of the repair tips and solution given should only be carried out by suitable qualified electronics engineers/technicians. Please be careful as all electrical equipment is potentially dangerous when dismantled. Any perceived slights of policy, specific people or organizations are unintentional.

Limit of Liability/ Disclaimer of Warranty: The author and publisher of this E-book and the accompanying materials have used their best efforts in preparing this program. The authors and publisher make no representation or warranties with respect to the accuracy, applicability, fitness, or completeness of the contents of this program. They disclaim any warranties (expressed or implied), merchantability, or fitness for any particular purpose. The reader is expressly warned to consider and adapt all safety precautions that might be indicated by the activities here in and to avoid all potential hazards. By following the instructions contained herein, the reader willingly assumes all risks in connection with such instructions. The authors and publisher shall in no event be held liable for any loss or other damages, including but not limited to special, incidental, consequential, or other damages. As always, the advice of a competent legal, tax, accounting or other professional should be sought. No this parts of this E-book/Guide/Manual shall be reproduced or transmitted by any means, electronic, mechanical, photocopying, printing and recording or otherwise . Any unauthorized use of this material is prohibited. All product illustration, product names and logo are trademark of their respective manufacturers. If you have any information regarding the illegal reselling or duplication of the E-book, please report it to [email protected] for your reward.

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Laptop Chip Level Repair Guide

If you want to learn more about Electronic Repair from the expert, please visit to the page here: http://www.XiuFix.com

Thank You for Contribution Thank you very much to Mr. Kent Liew. Where he gave me this opportunity to write this ebook and appreciate where he has helped me a lot in this project.

Author of this ebook

Mr. Eric Huang (China)

Note: Some words meaning in this ebook Tube = MOSFET or Transistor Partial pressure = Divider Triode= Transistor Resistance= Resistor (some time is mean the resistance, too) Motherboard = Mainboard Plate number = Model number Top tube = High-side of MOSFET Low or down tube= Low-side of MOSFET Light= Power on (some time also means screen got display) Universal meter = Multimeter

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Laptop Chip Level Repair Guide

Chapter 1 The Introduction of Laptop Repair The laptop computer also called as: Laptop, Notebook Computer, Portable, NB and etc. Nowadays, the laptop computer repair business still maintain in the market now. But the desktop computer repair market percentage is huge drop when compare to laptop computer.

1.1: The Level of Laptop Computer Maintenance/Repair 1) Application Level Laptop Maintenance This level of laptop repair is more on the software and system OS installed. For example:  Install Operation System (OS)  Install sound card, network card, Bluetooth, graphic card and etc hardware drivers.  Upgrade BIOS  And etc.

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Laptop Chip Level Repair Guide 2) Board Level Laptop Maintenance This level of laptop repair is more on the swap board. For example:        

Replace CPU (Processor), including the CPU heat sink & fan. Replace Hard disk Replace Battery Upgrade/Replace RAM Replace Keyboard Replace Screen Replace WIFI card And etc.

In this level of laptop repair, the repairer must have the basic knowledge on electronic. For example on how to use the multimeter to testing/measure voltage & ohm values.

3) Components Level Laptop Maintenance In this level of laptop repair, the repairer must know how to use the multimeter, Oscilloscope, DC Regulated Power Supply, Soldering Workstation, BGA machine and etc. The repairer can repair laptop mainboard with replace the electronic components to solve the laptop mainboard problem. For example electronic components:     

Resistor, Capacitor, Transistor/MOSFET Inductor IC chip South & North Bridge Discrete Graphic BGA chip & etc.

4) Signal Level Laptop Mainboard Maintenance Signals level laptop repair is an advance level of component level laptop repair. This is a top level or laptop repair. You need to know the knowledge on the above 1), 2) & and 3). For example, know how to read the schematic diagram, http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide for signal level laptop level repair, you must know how to measure and analysis the signals of the mainboard. So the perfect laptop repair solution is: Components Level + Signal Level repair!

1.2: The Basic Knowledge You Must Know Before Starting to Repair Laptop 1) The basic electronic repair knowledge you must know: a) The analogue and digital circuits. b) What are the opened circuit, short circuit, leakage circuit and etc. c) For the laptop repairer, you must know what's the "signal" and "timing sequence". I.

Signal = When a laptop mainboard working, it will sends and receives different data and commands to control the circuits. So the signal is very important for a laptop mainboard to working properly.

II.

Timing Sequence = The meaning of Timing Sequence is as the name of "Timing" and the "Sequence". When a laptop mainboard supply an AC to it, press power button until it start-up/opening successfully to working. At the same time mainboard each circuit will sends and receives the signals in between their correct timing and sequence, to successfully start-up/open the mainboard and ready to use by the user. The timing sequence is important, and must need to follow. If one of the step missing or incorrect timing, it will cause the mainboard not working. Even the markets have many brands laptop, but all or most of them are just using the Intel or AMD platform chipset only. So the same chipset is using the same timing sequence to work. And then we can just learn these two main chipset timing sequence, we can handle and repair the laptop easily.

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Laptop Chip Level Repair Guide 2) Know how to testing electronic components As a laptop repairer, you must know what type of electronic component it is and know how to testing an electronic component with using the proper tools & equipment.

3) Know the structure of laptop Need to know the structure of laptop before repair it. For example, how to proper dismantle the laptop and the correct maintenance steps.

4) Know how to operation the testing equipment properly Need to know the proper way on how to use the multimeter, soldering iron (soldering workstation), diagnostic card, DC regulated power supply, oscilloscope, BGA and etc. Also need to know how to avoid the electro-static damage the laptop mainboard. So it will help the laptop repairer to increase their successful rate in laptop repair.

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Laptop Chip Level Repair Guide

Chapter 2 Original & OEM Laptop Mainboard Part Numbers All branded laptop computer like Acer, Dell, HP, Lenovo and etc, they are not manufacture their laptop mainboard/motherboard. All of them are using the third party company design laptop mainboard to build their own brand laptop computer. This is because the branded computer company they want to earn more money and cut the cost to build a laptop computer. The entire third party laptop computer mainboard manufacturer called it as an OEM company/manufacturer. What is the difference to OEM (Original Equipment Manufacturer) and ODM (Original Design Manufacturer) company? The OEM company is responsible to manufacture the product, but not include the product design and research. But the ODM company is do all these thing, so the branded computer company just put their brand name and model into this laptop as their new model of laptop computer. For example the ODM product manufacture by ECS G550 is using in different brands and models of laptop computer like TCL610, ChangCheng E2000, FangZheng T5800D and etc. We can say most of the laptop computer company is using the OEM and ODM product to build their laptop computer now. All these OEM & ODM laptop production company are from Taiwan and their manufacturer base is in China. The popular OEM & ODM company like: Compal, QUANTA, Wistron, Inventec and Pegatron. These OEM company have a huge market percentage on production of laptop mainboard. The second line OEM manufacturer like: MITAC, Clevo, FIC, MSI, ECS, Flextronics, Foxconn, Topstar and etc.

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Laptop Chip Level Repair Guide In the laptop maintenance, we can see different brands and models of laptop computer send to repair. After dismantle the laptop and found it different brands and models of laptop, but they also use the same laptop mainboard. So their mainboard circuits, timing sequence and repairing steps also the same. We need to know how to identify the laptop mainboard part number and their OEM manufacturer by which company.

2.1: Quanta QUANTA is one the top OEM laptop mainboard manufacturer. Their OEM laptop mainboard is using by big laptop computer company like: Dell, HP, Lenovo, Apple and etc. The Quanta OEM laptop mainboard part number is starting from DA or DAO. Their part number is DA or DAO and in between MB with 3 digits or 4 digits. The Quanta mainboard p/n model CH3 is shown in figure 2-1. In this model of laptop mainboard schematic diagram, you can find the "PROJECT: CH3" on bottom right there, as shown in figure 2-2.

Figure 2-1: Quanta CH3 mainboard part number

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Laptop Chip Level Repair Guide

Figure 2-2: Quanta CH3 mainboard schematic marking label

2.2: COMPAL Compal is the second top of the OEM laptop mainboard manufacturer. Their OEM laptop mainboard is using by big laptop computer company like: Dell, HP, Lenovo, Toshiba and etc. The Compal OEM laptop mainboard part number is starting from LA, for example LA-4112, LA-3301P and etc. The part number starting from LS is a small transfer board. The Compal LA-3301P laptop mainboard part number is shown in figure 2-3. In the figure 2-3 mainboard schematic diagram, you can find "LA-3301P" at the bottom right corner there, as shown in figure 2-4.

Figure 2-3: Compal LA-3301P mainboard part number

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Laptop Chip Level Repair Guide

Figure 2-4: Compal LA-3301P schematic marking label

2.3: Wistron Wistron is the predecessor of Acer DMS (Design, Manufacture & Service) department. After 2001, it is independent from Acer company and become Acer top 3 company. Their OEM laptop mainboard is using by big laptop computer company like: Acer, Dell, HP, Lenovo and etc. As shown in figure 2-5, the Wistron OEM laptop mainboard PCB part number is starting from 05234, SHIBA is project name, 48.4F701.031 is project code. The Wistron laptop mainboard need to match the above 3 things then it is call a correct laptop mainboard.

Figure 2-5: Wistron SHIBA laptop mainboard

2.4: Inventec Inventec was founded in year 1975. Their OEM laptop mainboard is using by big laptop computer company like: Acer, Benq, HP, TCL, Toshiba and etc. The Wistron OEM laptop mainboard PCB part number is starting from 6050A. The Wistron laptop mainboard part number and schematic diagram model

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Laptop Chip Level Repair Guide number usually is not match. Need to use the manufacturer root file name to find the correct part number and model number. Figure 2-6 is Inventec 6050A2030501 laptop mainboard and brand model is HP NX6325.

Figure 2-6: Inventec 6050A2030501Laptop Mainboard

2.5: Pegatron Pegatron is the subsidiary company from ASUS since 2008. Their OEM laptop mainboard is using by laptop computer company like: ASUS. Their laptop mainboard have PCB logo as ASUS and PEGATRON. As shown in figure 2-7 (a) is the PEGATRON H24Z laptop mainboard and figure 2-7 (b) is the ASUS K43SV laptop mainboard.

Figure 2-7 (a)

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Laptop Chip Level Repair Guide

Figure 2-7 (b): Pegatron & ASUS laptop mainboard models

2.6: Samsung Samsung laptop mainboard is manufacture, design and research by Samsung. The Samsung laptop mainboard PCB part number is starting from "BA41-". For example, the Samsung BA41-00478A laptop mainboard is shown in figure 2-8.

Figure 2-8: Samsung BA41-00478A laptop mainboard

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Laptop Chip Level Repair Guide

2.7: Apple Apple laptop computer mainboard their model number marking code is quite small and hard to find it. The figure 2-9 is an Apple 820-2523-B laptop mainboard model number.

Figure 2-9: Apple 820-2523-B laptop mainboard

2.8: Other Manufacturers Introduce other OEM laptop mainboard manufacturers:

1) Micro-Star The Micro-Star laptop mainboard PCB part number is starting from MS- xxxxx. For example, the Micro-Star MS-6001 laptop mainboard is shown in figure 2-10.

Figure 2-10: Micro-Star MS-6001 laptop mainboard

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Laptop Chip Level Repair Guide

2) Foxconn The Foxconn laptop mainboard usually is using by big laptop computer company like: Apple, SONY and etc. Their laptop mainboard PCB model/part number is starting from MS. The figure 2-11 is MSS1 model laptop mainboard, version 1.1. But this model laptop mainboard is OEM for SONY, so their PCB can find the Sony model number: MBX-155.

Figure 2-11: Foxconn model MSS1 laptop mainboard

3) ECS The figure 2-12 is the ECS G510 model laptop mainboard.

Figure 2-12: ECS model G510 laptop mainboard

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Laptop Chip Level Repair Guide

4) MITAC The MITAC laptop mainboard usually is using by big laptop computer company like: Benq and etc. Their laptop mainboard PCB model/part number is starting from 4-digits number is shown in figure 2-13.

Figure 2-13: Mitac 8640 and 8599 model laptop mainboard

5) CLEVO The Clevo laptop mainboard usually is using by big laptop computer company like: BuyNow and etc. Their laptop mainboard PCB model/part number is starting from 1 character and follows by 3 numbers and last by 1 character. For example: D400S, D410E, D900K, M720T, M540J and etc. The figure 2-14 is a Clevo M55V0 model laptop mainboard.

Figure 2-14: Clevo M55V0 laptop mainboard

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Laptop Chip Level Repair Guide

Chapter 3 The Architecture of the Laptop Mainboard Now the chipset used by the mainstream laptop on the market is only two manufacturers. The Intel and AMD Intel is the absolute dominance. Once the most popular nVlDlA has quit the chipset industry in 2010, on the market, the notebook computer products with nVIDlA chipset are few.

3.1: The Architecture of Intel Double Bridges (GM/PM45 and below) The Intel Double Bridge architecture includes the 855-GM/PM45 chipset. In the Intel Double Bridge architecture, their CPU & North Bridge both are connected through the FSB (Front Side Bus) and the North Bridge also control the memory, PCI-E 16X discrete graphics card and display output interface. The North Bridge and South Bridge bus connected is called as HUBLINK before. But it is renamed to DMI (Direct Media Interface) now and their transmission speed increased much faster. The South Bridge is control peripheral extension interface, mainly in the following: USB: Devices on the USB line are USB interface, camera, Bluetooth and etc. Audio card: MODEM and the audio card are on the same line.

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Laptop Chip Level Repair Guide SATA: Hard Disk and CD/DVD-ROM. IDE: (Early) Hard Disk and CD/DVD-ROM. PCI-E device: Network card, Card Reader, Expansion card, Mini PCI-E slot & etc. EC (Embedded Controller): The name of lines connected to the South Bridge is LPC (Low Pin Count: means one of the bus with a small number of pin-out). The devices controlled by EC are Keyboard, Touch Pad, BIOS & etc. (Some of the mainboard BIOS and EC may work by the same LPC bus or connected the South Bridge directly via SPI bus). The architecture of Intel GM45 is as shown in figure 3-1.

3.2: The Architecture of Intel Single Bridge (above HM55) After Intel 5 series chipset developmental, it becomes the bridge call PCH, and that's to say the North Bridge integrated into the CPU. In the architecture of single bridge, CPU main control memory and PCI-E 16X discrete graphics card and the integrated graphics is also integrated within CPU. The bus that CPU and PCH Bridge connected to, are FDI (Flexible Display Interface) and DMI bus. PCH control USB, PCI-E IX SATA, audio card and other peripheral device. The connection of PCH and EC is still using LPC bus devices under EC remain unchanged. It was nothing that in the architecture of Intel single bridge. Although CPU integrated the graphics card, but the display signal output is not usually output by itself, and after transmitted to PCH through FDI bus, then completed output by PCH. It's different from the next AMD single architecture. The architecture of Intel HM75 chipset is as shown in figure 3-2.

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Laptop Chip Level Repair Guide

Figure 3-1: The architecture of Intel GM45

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Laptop Chip Level Repair Guide

Figure 3-2: The architecture of Intel HM75 chipset

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Laptop Chip Level Repair Guide

3.3: The Architecture of AMD Double Bridges (RS780) Because the AMD chipset uses AMD 638-pin CPU, so CPU can manage memory directly. The North Bridge manages all PCI-E devices, its difference from Intel double bridge, please remember. The North Bridge also integrated the graphics card, and is responsible to output display signal. The South Bridge manage audio card, USB, SATA, EC and etc, and the devices under EC remain unchanged. Here to mention, the BIOS has a variety of work bus, some work through XBUS under EC and some work through LPC bus connected in parallel with EC and some work through SPI bus connected South Bridge independently. This is not much associated with the architecture actually. The architecture of AMD RS780 is as shown in figure 3-3.

3.4: The Architecture of AMD Single Bridge (A70) After AMD chipset A45 (mobile version is A50) development, it changed to the single bridge called FCH. There are a lot of similarities with Intel single bridge. The bridge and devices managed by EC are almost the same, so no longer elaborated. The CPU of AMD also integrated the graphics card called APU. But it can output the display signal directly and it's difference with the architecture of Intel single bridge. The architecture of AMD A70 chipset is as shown in figure 3-4.

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Laptop Chip Level Repair Guide

3.5: The Architecture of nVIDIA Double Bridges (C51M) nVIDIA is very famous for graphics card and chipset, but they didn't product PC chipset anymore. In the desktop computer, there are many single bridge chipset and double bridge chipset, but in the laptop, there are using many double bridge. In the architecture of nVIDIA double bridge, CPU uses AMD 638 and it can manage memory directly. The North Bridge is responsible to manage all PCI-E devices and output the display signal on integrated graphics card. It is accordance with AMD double bridge architecture. Devices managed by South Bridge and EC are not big difference with AMD double bridge. The architecture of nVIDIA C51M chipset is as shown in figure-3-5.

3.6: The Architecture of nVIDIA Single Bridge (MCP67) In the architecture of nVIDIA single bridge , their memory managed by CPU and the other is managed by the Bridge, the large heat release of the bridge and it is easy to weld. The architecture of nVIDIA MCP67 chipset is as shown in figure 3-6.

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Laptop Chip Level Repair Guide

Figure 3-3: The architecture of AMD RS780

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Figure 3-4: The architecture of AMD A70 chipset

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Laptop Chip Level Repair Guide

Figure 3-5: The architecture of nVIDIA C51M chipset

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Laptop Chip Level Repair Guide

Figure 3-6: The architecture of nVIDIA MCP67 chipset

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Laptop Chip Level Repair Guide

Chapter 4 The Common Concepts of Laptop and Noun Explanation About laptop mainboard maintenance it is often involving some professional terminologies of the circuit and signal. To understand the schematic circuit diagram and learn to repair well we must understand these concepts first.

4.1: Power Supply and Signal On the mainboard, some places have 5V voltage, we called 5V power supply. And some places also have 5V voltage, we called signal, so what's the difference between them?

1. Power Supply Power supply is an output current of the voltage and current is large. During working, the voltage cannot be set higher or lower. If the power supply is low, it's short circuit. In general, set high is not allowed. The power supply is providing the power to the devices, it's marking name as: VCC, VDD, VCC3, VDDQ, VTT, VBAT, 5VALW, +3VO or etc.

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Laptop Chip Level Repair Guide The circuit symbol of power supply is shown in figure 4-1.

Figure 4-1: The circuit symbol of power supply

In the circuit diagram of Apple products, the power supply us generally beginning with PP and haven't other special symbol as shown in 4-2

Figure 4-2: Apple product circuit symbol of power supply

The Grounding is to form a loop for power supply. Without grounding, it is no current will flow through the devices. The marking names are VSS and GND. The circuit symbol of grounding is shown in figure 4-3.

Figure 4-3: The circuit symbol of grounding

2. Signal In theory, the voltage signal only considers the voltage change and current is low. In the working process of the mainboard, it can be set higher or lower at any time according to the needs. The arrow of signal in the circuit diagram below is not representing the flow of signal completely. It is because of the schematic diagram designer when drawing the circuit in unprofessional skill. The circuit diagram of signal is shown in figure 4-4.

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Laptop Chip Level Repair Guide

Figure 4-4: The circuit diagram of signal

4.2: High Level and Low Level In the digital logic circuit, the low level is represented by "0", and the high level is represented by "1". The high and low level in the circuit needs to be decided by the circuit, not to be limited to a certain value. But in general, 0V is low level and 3.3V is high level.

4.3: Jump and Pulse From high level jump to a low level also called the falling edge, shown in figure 45.

Figure 4-5: The falling edge waveform

From low level jump to low then jump to high also called rising edge, as shown in figure 4-6.

Figure 4-6: The rising edge waveform

From high jump to low then jump to high also called high-low-high pulse waveform is as shown in figure 4-7.

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Laptop Chip Level Repair Guide

Figure 4-7: The high-low-high pulse waveform

4.4: The Clock Signal The clock signal CLK (CLOCK) is to provide a benchmark for the digital circuit work, so that each connected device unified work pace. The basic unit of the clock is Hz (Hertz). There is a main clock generating circuit on the mainboard. The function of this circuit is to provide the clock for all devices on the mainboard. For different devices, the clock circuit will send different frequency, such as to the frequency of CPU is more than 100Mhz, to PCI device is 33MHz, to PCI-E device is 100MHZ , to USB controller (integrated in the South Bridge internal) is 48 Mhz. But the two connected devices must have the same clock frequency and voltage to communicate. For example, memory and North Bridge need the same clock and voltage to transmit signal normally. After main board powering on normal and also the clock chip work normal, then the clock signal can be measured correctly. We can use the oscilloscope or multimeter to measure the clock signal. The clock signal of clock chip benchmark- 14MHz is shown in figure 4-8.

Figure 4-8: The clock signal of clock chip benchmark- 14MHz

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Laptop Chip Level Repair Guide

4.5: Reset Signal The literal meaning of reset signal (RST) is a restart/new signal. When power on laptop, it will reset automatically and jump from low level to high level; during normal operation, press the reset button, it will from high level to jump to the low level then back to high level. For example, for PCI, from 3.3V to jump to 0V, after that to 3.3V, that's mean it is a normal reset jump. Reset signal is generally expressed as ***RST#, such as PCIRST#, CPURST#, IDERST# and so on. In short, the reset can only be momentary low level, but when the mainboard works normally, the reset is high level. We said not reset usually refers to no reset voltage, which is the measurement point voltage of the reset signal is 0V. The 3.3V platform reset from the South Bridge, after dividing into 1.1V as the CPU reset, shown in figure 4-9.

Figure 4-9: The circuit of the CPU reset

4.6: The Power Good Signal The power good signal PG (POWERGOOD) is used to describe the normal power supply is usually active high. For example, after sending the CPU voltage normally, then the CPU power supply chip can send PG signal. The common abbreviations of PG signal are PD, PWRGD, POK, PWRG, VTTPWRGD, CPUPWRGD and so on. For example the RT8205 chip, when it is working normally, then it will send SPOK, is shown in figure 4-10.

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Laptop Chip Level Repair Guide

Figure 4-10: PG signal diagram

4.7: Open Signal (or Start-up Signal) Some chip called it as EN (Enable), the high level represents the open signal. But some chip called SHDN#, namely SHUTDOWN, "#" represents active low level. It means that signal is closed when it's low level. So to open it or laptop mainboard power on, it must be high level. We need to emphasize that we must be combined to full name in English of signal to understand signal with "#" (when active-low level), some signal with "#", when it's low level the mainboard can work normally. For example, signal VR-PWRGD-CK410# in figure 4-11, sending the low level to open the clock chip after power supply is normal. But some signal with "#", the mainboard working normally must be high. For example 1999_SHDN# shown in figure 4-12 is the low level control signal for closing MAX1999.

Figure 4-11:VR_PWRGD signal

Figure 4-12: 1999_SHDN signal

Timing is through EN, PG and other signals to achieve control.

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4.8: Chip Select Signal CS is the Chip Select short form. When many of the chips on the same bus, then it is need a signal to distinguish data and address on bus managed by which chip. So we need a chip select signal to control it. Chip Select signal is common in BIOS chip with symbol CS#, and "#" represents active-low level. It's sent by CPU, from the North Bridge to the South Bridge and finally reaches to the BIOS. It exist or not, which can initially judge whether the North Bridge, South Bridge and CPU to work or not. And also whether BIOS information is destroyed SPI BIOS pin shown in figure 4-13 and pin-1 CS# is the BIOS chip select signal.

Figure 4-13: SPI BIOS pins

4.9: The Explanation of Common Signal Name/Symbol for Laptop Mainboard Manufacturers 4.9.1 Wistron Some of common signals names about Wistron Laptop Mainboard shown in table 4-1.

Signal Names/Symbols

Description

AD+

The first voltage that the power adapter converts.

DCBATOUT

Common point

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Laptop Chip Level Repair Guide +3VL

3.3V linear power supply, supply voltage to EC.

DCIN

Power supply input for charging chip.

ACIN

Power adapter detection input for charging chip.

ACAV-IN

Power adapter detection output for charging chip.

PWR-S5-EN

A control signal used to open standby voltage of South Bridge.

+5VALM, +3VALM

The standby power supply of South Bridge

AD_IN# , AC_IN#

The power adapter detection signal to EC, the low level represents that the adapter is inserted.

KBC-PWR-BTN#

Press the on/off switch to produce the trigger signal to EC.

LID_CLOSE#

Close cover switch

CLK_EN#

After CPU power supply being normal, send the low level that can be used to open the clock.

G792-RST#

The high level s4end by the temperature control chip when the temperature is normal.

CK-PWRGD

After the South Bridge receiving VRMPWRGD, sent this signal as high level for opening the clock.

Table 4-1 The list of some common signal names/symbols about Wistron

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4.9.2 Quanta Some of common signals names/symbols about Quanta Mainboard shown in table 4-2.

Signal Names/Symbols

Description

VIN

The common point voltage

ACIN, ACOK

Power Adapter detection

3V_AL, 5V_AL, VL

3V, 5V Linear power supply

+3VPCU, +5VPCU

EC Standby power supply

3V_S5

The voltage under the condition of S5; The South Bridge power supply; Opened by EC after Trigger switch.

+3VSUS, +5VSUS

The voltage under the condition of S3; Memory power supply; Sent by EC and opened by SUSON.

NBSWON#

Trigger signal for power on; Press the power on key to produce high-lowhigh signal to EC.

DNBSWON#

EC sent high-low-high effective trigger signal to the South Bridge PWRBTN#.

SLP_S3#, SLP_S4#

ACPI controller signal sent by the South Bridge is used to opening voltage when the power is turned on, and it also used to shutting off voltage when the power is turned off.

S5_ON

The opening signal of the South Bridge standby voltage sent by EC; Its use to convert the PCU to voltage S5.

SUSON

After EC receiving SLP_S5# from the South Bridge, then producing S3

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Laptop Chip Level Repair Guide voltage opening signal. MAINON

After EC receiving SLP_S3# from the South Bridge, after that producing S3 voltage opening signal.

VR_ON

The CPU core voltage opening signal sent by EC.

HWPG

By the PG Logic and all power supply except the CPU core power supply.

PWROK_EC

After EC received high level HWPG signal, delay producing the PWROK_EC signal.

DELAY_VR_PWG

CPU core voltage power-good signal.

VR-PWRGD-CK410#

CPU core voltage power managed the clock open signal from chip; Active low level. The South Bridge sent CL-PWRGD open clock chip after receiving VRMPWRGD.

CK_PWRGD

CPUPWRGD

In the South Bridge internal, PWROK pin and VRMPWRGD pin signal through the logic generated CPUPWRGD.

PLTRST#

The platform reset signal; After the South Bridge sending CPUPWRGD signal, through the delay buffer sent PLTRST#.

PCIRST#

The PCI reset; Used for resetting the device on the PCI bus when powered on; Making the device work from an initial state.

CPURST#

CPU reset signal; The North Bridge sent CPURST# to CPU after received

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Laptop Chip Level Repair Guide PLTRST#. BL/C#

Represents high level, low battery (only for battery mode).

D/C#

Inverse relationship with ACIN (Just for mainboard with D/C# signal, where the mainboard is without BL/C# signal).

Table 4-2 The List of some common signal names/symbols about Quanta Mainboard

4.9.3 ASUS Some of common signals names/symbols ASUS Laptop Mainboard shown in table 4-3.

Signal Names/Symbols

Description

AC_BAT_SYS

The common point voltage

ACIN

Power adapter detection

+5VAO

5V linear voltage

+3VAO

3V linear voltage

+5VA

+5VAO renamed to +5VA after jumper.

+3VA

+3VAO renamed to +3VA after jumper JP8101.

+3VA_EC

+3VA renamed to +3VA_EC after through the inductance; As the EC standby power supply.

+5VO

5V standby voltage in S5dormant state.

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Laptop Chip Level Repair Guide +3VO

3V standby voltage in S5dormant state.

+5VSUS

+5VO renamed to +5VSUS after jumper.

+3VSUS

+3VO renamed to +3VSUS after jumper.

VSUS_ON

SUS voltage open signal.

SUS_PWRGD

SUS voltage power-good signal; Send to EC.

PM_RSMRST#

The reset signal of the South Bridge ACPI controller; Can be understood that the South Bridge standby voltage is normal when received this signal.

PWRSW_EC#

Laptop boot-up trigger signal.

PM_PWRBTN#

After receiving PWRSW_EC, EC sent PM_PWRBTN# effective trigger to the South Bridge PWRBTN# pin.

SUSC_ON, SUSC_PWR

S3 voltage open signal.

SUSB_ON, SUSB#_PWR

S0 voltage open signal.

ALL_SYSTEM_PWRGD

Generated by memory power supply, Bridge power supply, bus power supply, graphics card power supply and PG signal logic.

CPU_VRON

EC delayed 99ms to send VR_ON after sending SUSB_ON; For opening CPU core voltage.

EC_CLK_EN

EC sent VRMPWRGD to the South Bridge pin to inform the South Bridge that CPU core voltage is normal.

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Laptop Chip Level Repair Guide CLK_PWRGD

The South Bridge generated CLK_PWRGD to IC clock after receiving VRMPWRGD; For opening the clock signal.

PM_PWROK

After receiving ALL_SYSTEM_PWRGD, EC delayed sending PW_PWROK.

H_CPURST#

The North Bridge sent H_CPURST# to CPU after receiving PLTRST# signal.

GATE_PWR_SW#

The booth trigger signal.

LID_SW#

Close-lid sleep switch signal; When the machine is closed, this signal is low level.

LID_KBC#

The close-lid sleep switch detection signal for EC.

KBCRSM

The keyboard wake-up signal.

FORCE_OFF#

The forced shutdown signal; Generated by the under voltage protection circuit.

HW_PROTECT#

CPU over temperature protection signal.

OTP_RESET#

CPU over temperature indication signal.

Table 4-3 The List of some common signal names/symbols about ASUS Laptop Mainboard

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Laptop Chip Level Repair Guide

4.9.4 Compal Some of common signal names about Compal shown in table 4-4.

Signal Names/Symbols

Description

B+

Common point voltage.

PACIN

The detection output signal is inserted to the adapter; The high level represents that the adapter is inserted.

VL

5V linear power supply.

+3VALW, +5VALW

Inserting the adapter, that is the opened voltage.

ON/OFFBTN#

Press power on key signal.

ON/OFF#

The trigger signal sent by boot trigger circuit to EC.

PBTNOUT#

The boot trigger signal sent by EC to the South Bridge.

SYSON

S3 voltage open signal.

SUSP#

S0 voltage open signal.

+VCCP

The working voltage of CPU front side bus; This voltage distributes in CPU, the North Bridge, and the South Bridge.

+CPU_CORE

CPU core voltage.

VGATE

CPU core voltage power-good signal.

ICH_POK

PWROS for the South Bridge; Inform the South Bridge system voltage power good.

BCLK

The front side bus clock signal.

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Laptop Chip Level Repair Guide SUS_STAT#

Sent by the South Bridge; The low level indicates that the system will be in power-down (save power) mode.

Table 4-4 The list of some common signal names/symbols about Compal

4.9.5 DELL Some of common signal names about Dell shown in table 4-5.

Signal Names/Symbols

Description

RTC_CELL

The mainboard button battery voltage.

+DC_IN

Power Adapter voltage input.

+PWR_SRC

The common point voltage.

ALWON

EC sent a ALWON signal to the system power supply chip to open/start-up the system power supply.

THERM_STP#

Overheat protection signal; Active-low level.

ACAV_IN

The Power Adapter detection signal.

POWER_SW#

A low voltage signal generated by the power switch or keyboard and EC chip receives this boot signal.

SUS_ON

After receiving the trigger signal, EC sent SUS_ON to use to open the South Bridge standby power supply and memory main power supply.

RUN_ON

EC sent open S0 state voltage.

GFX_ON

Open discrete graphics card power

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Laptop Chip Level Repair Guide supply. _VCC_GFX_CORE

The discrete graphic card core power supply.

+0.9V_DDR_VTTP

Memory VTT power supply.

RUNPWROK

The PGD signal of all RUN power convergence to this signal.

SUSPWROK

The reset signal of all SUS power brings together to generate the SUSPWROK signal.

+VCCP_1P05VP

The front side bus power supply: 1.05V.

PGD_IN

One of the conditions of that CPU power supply chip sent CLK_EN#, PGOOD and others.

CLK_ENABLE#

The open signal of clock chip: Activelow level.

H_PWRGOOD

PGD reset signal sent by the South Bridge to CPU.

H_RESET#

The North Bridge sent CPU reset signal.

+VCHGR

Charging output voltage.

+SBATT

Auxiliary/Sub battery power supply terminal.

+PBATT

Main battery power supply terminal.

SBAT_PRES#

Detection of insert the auxiliary battery.

PBAT_PRES#

Detection of insert main battery.

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Laptop Chip Level Repair Guide IMVP_VR_ON

Open CPU power supply.

IMVP_PWRGD

Power supply good signal sent by CPU power supply chip.

Table 4-5 The list of some common signal names/symbols about Dell

4.9.6 Apple Some of common signal names about Apple shown in table 4-6.

Signal Names/Symbols

Description

=PP3V42_G3H_REG

3.42V power supply in the condition of G3 equivalent to the linear power supply of other machine.

=PP3V3_S5_REG

3.3V power supply in the condition of S5 provided the standby voltage to the South Bridge and others.

PP3V3_G3_SB_RTC

3.3V power supply of the South Bridge RTC circuit.

=PPBUSA_G3H

Common point voltage.

PM_BATLOW_L

The indicator signal of low battery voltage; Active-low level.

1V8S3_RUNSS

S3 state voltage (memory supply) of 1.8V open signal.

ALL_SYS_PWRGD

Convergence from all power supply good signal except CPU power supply.

VR_PWRGOOD_DELAY

The power good signal sent by CPU power supply after generating CPU voltage normally and it will delay to send the power-good.

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VR_PWRGD_CK505_L

The lower level signal of open clock; After CPU power supply chip generating CPU voltage normally, it will send the low level signal to open clock.

SMC_BC_ACOK

The Adapter detection signal; Active high level.

SMC_ADAPTER_EN

The high-level signal output by SMC after receiving the adapter detection signal.

SMC_BATT_CHG_EN

The charging enable signal sent by SMC; Active-high level.

ACPRN

Low level ACPRN signal sent by charging chip after the adapter is detected.

ONEWIRE_EN

ONEWIRE enable signal; For the adapter to identify circuit (the power connector LED green light).

Table 4-6 The list of some common signal names/symbols about Apple

4.9.7 Inventec Some of common signal names about Inventec shown in table 4-7.

Signal Names/Symbols

Description

+VADP

Power adapter voltage.

ADP_EN#

Power adapter enable signal; Active low level.

ADP_PRES

Adapter detection output voltage; It

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Laptop Chip Level Repair Guide can be use to open the system power supply directly. +VBATR

Common point voltage.

+3VAL, +5VAL

Linear power supply.

PWR_SWIN_3#

The signal sent by trigger switch to EC chip.

KBC_PW_ON

The power signal; It is sent by EC after EC receiving trigger switch; It is use to open the system standby power supply under the battery mode (backup battery).

VCCI_POR#3

The initial reset signal of EC.

+V3A, +V5A

Power supply of standby system.

LIMIT_SIGNAL

The power adapter connector intermediate pin; Power identification signal.

OCP

Over-current protection.

Table 4-7 The list of some common signal names/symbols about Inventec

4.9.8 ThinkPad (IBM) Some of common signal names about ThinkPad (IBM) show in table 4-8.

Signal Names/Symbols

Description

DOCK_PWR20_F

The power adapter voltage.

CV20

The voltage between adapter and common point.

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Laptop Chip Level Repair Guide VINT20

The common point.

DISCHARGE

Forced to close adapter; Battery discharge signal.

-PWRSHUTDOWN

Over-Temperature and Under-voltage protection signal; Use to isolate the adapter.

VCC3SW

3.3V voltage; Output by TB chip; Pullup -PWRSHUTDOWN; To supply power to the Lenovo chip.

-EXTPWR

The adapter detection signal; Output by charging chip; Active low level.

-EXTPWR_ASIC

The adapter detection input signal of the Lenovo chip.

-EXTPWR_H8

The adapter detection input signal of H8S.

VL5

The 5V linear voltage; Generated by the standby chip.

DCIN_DRV

The spacer tube use to control the adapter; Fully turn-on the adapter spacer tube at high level.

BAT_DRV

The spacer tube uses to control the battery; Isolated the battery in a low level. Turn-on the battery at high level.

M1_ON

The high level signal of standby voltage sent by Lenovo chip for opening the South Bridge.

VCC5M

5V standby voltage of the South Bridge.

VCC3M

3.3V standby voltage of the South Bridge; It is also the power supply of

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Laptop Chip Level Repair Guide H8S. TH_DET

Multiple Thermistors connected in series; Detect temperature; When the temperature is normal, this pin is lower than 0.5V.

ACDET

The adapter of the charging chip detects input pin.

SWPWRG

The standby voltage power good signal of the Lenovo chip.

VREGIN20

The voltage with a small current generated after the adapter or battery accessing to or connected; The power supply of TB chip.

BAT_VOLT

VREGIN20 voltage detection pin; The threshold voltage is 2.9V.

MPWRG

After TB chip detected VCC3M, VCC5M voltages are normal, sent the PG signal to South Bridge RSMRST#.

-H8-RESET

The reset signal sent by Lenovo chip to H8S.

VDD15

After TB chip detects M voltage is normal, bootstrap boost 15V; To provide power to xx_DRV of TB chip output.

VCPIN28

After TB chip detects M voltage is normal, bootstrap boost 28V (is 25V in fact); Use to driving and protecting the isolating circuit with N-channel FET.

A_ON

A voltage is turned on (S3 voltage, such as memory power supply).

B_ON

B voltage is turned on (S0 voltage,

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Laptop Chip Level Repair Guide such as the bus power supply). B_DRV

B voltage drive signal; Sent by TB chip.

BPWRG

Power-good signal; Sent by TB chip after detecting VCC3B, CVCC5B normal.

AMT_ON

ME module voltage is turned on.

SLP_M#

Sent by the South Bridge; Use to control the opening of AMT power supply.

AMTPWRG

AMT power-good.

-PWRSWITCH, -PWRSW

Power switch signal.

BATMON_EN

Battery voltage monitoring enable.

M_BATVOLT

Main battery voltage feedback.

M1_DRV, M2_DRV

Main battery charging and discharging driving signal.

BAT_CRG

Battery large current charge control switch.

CHARGE_OUT12

12.6V charging voltage control output by charging chip.

M_TRCL

The main battery trickle charging control switch.

S_TRCL

The auxiliary/sub battery trickle charging control switch.

Table 4-8 The list of some common signal names/symbols about ThinkPad (IBM)

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Chapter 5 The Basic Application Circuit of Electronic Components Electronic components of laptop are resistors, capacitors, diodes, transistors, field-effect-transistors, gate circuit, comparator, voltage regulator and so on. They are the most changeful when use in the circuit. For the people who have just touched with laptop repair, it's quite difficult to understand a basic electronic circuit. It makes the circuit-based become a stumbling block for maintenance people. This chapter mainly introduces the basic application of the electronic components in the circuit, and does not include the understanding and measurement of components. If the reader is not familiar with the understanding and measurement of components, can refer to the relevant basic book, there are many of such books on the market.

5.1: The Basic Application Circuit of Capacitor l. Filter capacitor Filter capacitor used in the power rectifier circuit and used to filter out the AC components. It requires that larger capacitance adopts the high-capacity tantalum capacitor, and smaller capacitance adopts SMD capacitor. PC9 (K PC89x PC93 in figure 5-1 are 330uF tantalum capacitor.

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Figure 5-1: Filter Capacitor

2. Coupling capacitor Coupling capacitor usually adopts chip capacitor, used on the signal line of PCIE and SATA, the feature is in series in the signal circuit, the role is used to isolate DC and ensure the transmission of high-speed signals. As shown in figure 5-2, four parallel capacitors are the coupling capacitor, and both ends are thin lines.

3. Resonant capacitor Resonant capacitor is only used in the crystal oscillator circuit, the general capacitance is tens of pF, and respectively connected between two pins of the crystal oscillator and ground, the parameters of the resonant capacitor will affect the resonance frequency and the output amplitude of the crystal oscillator. Resonant capacitor adopts chip capacitor, as shown in figure 5-3. C180 and C181 are the resonant capacitor.

Figure 5-2: Coupling Capacitor

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Figure 5-3: Resonant Capacitor

5.2: The Basic Application Circuit of Resistor The application of resistance in the board circuit is mainly pull-up resistance, pull- down resistance, protective resistance and thermal resistance.

l. The pull-down and Pull Up resistance In general, the resistance connected the voltage is the pull-up resistance (in figure 5-4) and the resistance connected the grounding is the pull-down resistance (in figure 5-5).Pull-up is to clamp uncertain signal at a high level through a resistance, the resistance works current-limited effect at the same time. And pull-down is in the same way.

Figure 5-4: Pull-up resistance

Figure 5-5: Pull-down resistance

The application of pull-up and pull-down resistance shown in figure 5-6: When R206 is installed and R205 is not installed, the INTVRMEN is high level, open the internal voltage regulator of ICH7 (the default value); when R205 is

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Laptop Chip Level Repair Guide installed, R206 is not installed, INTVRMEN is low level, close the internal voltage regulator of ICH7.

Figure 5-6: Pull-up and pull-down resistance

The voltage division circuit: Both the existence of the pull-up, and the existence of the pull-down, that constitutes a voltage division circuit, as shown in figure 5-7. The formula of series partial pressure is: VA=VTotal/(R1+R2)*R2 RC delay circuit (shown in figure 5-8):+VCC_RTC charge C1704 first through R 1701, the RTCRST# voltage will slowly raise, and the time required that it rises to equal with +VCC_RTC voltage is the delayed time. A simple calculation of the delayed time can be used R*C, such as 20KΩ * l uF= 20ms.

Figure 5-7: The voltage division circuit

Figure 5-8: RC delay circuit

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2. Protective resistance

Figure 5-9: Protective resistance picture The protective resistance plays the role in protective effect. When the circuit load becomes large, beyond the range of resistance can afford, resistance will be open circuit make the corresponding circuit to stop working and as to achieve the purpose of protecting the components. The resistance of protective resistor is generally below 10Ω. In the figure 5- 9, R243 is the protective resistor.

3. Thermal resistance The thermal resistance is divided into two: "The higher the temperature, the lower the resistance" (NTC, the negative temperature coefficient) and "The higher the temperature, the higher the resistance" (PTC, the positive temperature coefficient). The thermal resistance shown in figure 5-10, but we cannot distinguish NTC or PTC from the physical.

Figure 5-10: The thermal resistance

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5.3: The Basic Application Circuit of The Diode The forward voltage drop of the common silicon is 0.7V and the germanium diode is 0.3V. In the figure 5-11, the positive electrode is on the left. The negative electrode is on the right, 3.3V input from the left, if it has, a silicon tube 2.6V will be output from the right.

Figure 5-11: Diode

l. OR Gate application of diode (shown in figure 5-12) Power failure with 3V BAT power supply, after plugging with 5VALW power supply, in order to save battery power, can ensure that VCCRTC always have electricity. Such diodes are generally composite diodes, the material object shown in figure 5-13.

Figure 5-12: OR gate application of Diode

Figure 5-13: Composite Diode Physical Map

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2. AND Gate application of diode(shown in figure 5-14) As long as any signal at the left end of the diode has low level, diode will conduct, pull HWPG low.

Figure 5-14: AND gate application of diode

3. Clamping applications of diode (shown in figure 5-15)

Figure 5-15: Clamping of application diode

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Laptop Chip Level Repair Guide (l) VIN voltage (assumed to be 18.5V) after resistance PR29, PR28 series partial pressure, the Voltage after partial pressure is 7.6V. (2) Now the positive electrode voltage of PD9 is 7.6V, the negative electrode voltage is 3.3V, so the positive electrode is greater than the negative electrode, and over the conduction voltage drop 0.7V.

Figure 5-16: Anti-Static clamping diode

(3) PD9 conduction, the diode cathode is only higher than the negative electrode 0.7V after conducting, so the A point voltage is clamped to about 4V. Clamping diodes are generally next to the USB interface or VGA interface, used to prevent static electricity, shown in figure 5-16.

4. Voltage stabilizing diode When the diode reverse voltage to a certain value, the reverse current will suddenly increase, which is called the breakdown phenomenon. In the state of breakdown, the current through the tube changes a lot and the voltage of both ends of the tube is almost constantly using this feature; it can achieve voltage regulation, which is called the voltage stabilizing diode. In the figure 5-17, U9000 is 2.5V voltage stabilizing diode, when the negative voltage applied is more than the regulated value, then the reverse breakdown current will appear, so the voltage of both ends can be fixed. R9000 is the limit current resistance, and the reverse breakdown current of the voltage stabilizing diode in between 5mA~ 40mA.

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Figure 5-17: Voltage Stabilizing Diode

In the figure 5-18, PD12 is 5.1V voltage stabilizing diode, when VS is 19V, applied to the negative, can be broken down, the voltage reaching the positive is remaining 13.9V, and after the partial pressure of PR87 and PR90 to send chip 6 pin SHDN# as open, the purpose is to limit VS minimum voltage. Only VS exceeds a certain value, the partial pressure after the reverse breakdown can meet the rising edge threshold value of SHDN#.

Figure 5-18: Example of the Stabilizing Diode

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5.4: The Basic Application Circuit of Transistor In the laptop circuit, the main application of the transistor is switching action: E pole of NPN transistor connects ground: when B pole input high level, C pole is low level; when B pole input low level. C pole is high level. Specific content as follows: Common NPN type: when VB> VE 0.7V, B-E is conducted, and C-E is also conducted. Common PNP type: when VBVS 4.5V or more).

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Figure 5-24: Example of application of field-effect-tube

5.6: The Basic Application Circuit of Gate Circuit l. NOT gate In the figure 5-25,U27 is the NOT gate: when DGPU_SELECT# is high level,U27 outputs a low level of IGPU_SELECT#;when DGPU_SELECT# inputs level, IGPU_SELECT outputs high level.

Figure 5-25: The application of the NOT gate http://www.XiuFix.com/laptop-chip-level-repair/

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2. AND gate The application of the AND gate shown in figure 5-26: only when EC_PWROK and IMVP_PWRGD are high level then U25 can output high level of SYS_PWROK.

Figure 5-26: The application of the AND gate

3. Three-state gate The application of the three-state gate shown in figure 5-27:only when OE is low level, the output level is consistent with the input level(equal to the follower);when OE is high level, no matter what state the input is, the output is always keep high impedance state. But in the figure 5-27, OE has been forced to ground, so it's no difference between this circuit and follower in the level logic.

Figure 5-27: The application of the three-state gate http://www.XiuFix.com/laptop-chip-level-repair/

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5.7: The Basic Application Circuit of Comparator Basic application of comparator shown in figure 5-28, the 3V battery is added to the inverting input of the comparator, compared with the voltage of VIN partial pressure. When VIN is greater than 15.67V,the voltage of partial pressure will be higher than 3V,the comparator open drain output (7 pin and PU48 comparator internal are disconnect),RSMVCC3 pulls up ACIN to be high level to the chip; when VIN is less than 15. 67V, the comparator will output low level (7 pin and 4 pin internal are short circuit), ACIN is pulled to the ground.

Figure 5-28: The application of the comparator

CPU overheating protection circuit shown in figure 5-29.The comparator 6 pin is divided into 2.5V by +5VALM.At the room temperature, the resistance of PHI is l0k +SVS partial pressure through PHI and PR 161, applied to the comparator 5 feet, will be less than 2.5V of comparator 6 pin. The comparator output low level. Make PQ39 cut-off. MAINPWON is not pulled down, at the same time, because the comparator output low level, leading to PR167PR 163 series, and form series with PR 161, so that the 2 pin voltage of PHI is pulled down again.

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Figure 5-29: The comparator in a temperature control circuit When the temperature of PHI increases, the resistance is reduced to less than 2.55k^, the voltage of the comparator Spin achieved will be higher than 2.5V of 6 pin, the comparator outputs 5V high level, make PQ39 conduct, pull down MAINPWON, the system power supply is shut down; at the same time, the high level comparator output, making PR167s PR163 and PHI be series, thus pull up the 2 pin voltage of PHI again. This PR167 is the hysteresis resistance, the author called it as "fence resistance". The role is to make the CPU temperature protection value not stay at a point, such as 90 degrees over temperature protection, 50 degrees to return to normal.

5.8: The Basic Application Circuit of The Converter Multiplexer (MUX) is used in the second generation dual graphics switching circuits is the control signal, when S is low, Bo connects A, when S is high, Bi connects A, as shown in figure 5-30.

Figure 5-30: The definition of converter chip

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5.9: The Basic Application of The Voltage Regulator As shown in figure 5-31, U8100 is low dropout regulator (LDO), which input power supply from 1 pin, output voltage from 5 pin, two resistances connected by 4 pin control high-low of the output voltage, the reference voltage is 1.24V. 3 pin is the open signal of chip, high level opens output and low level stops output. The calculation formula of output voltage is: VOUT =VFB x ( l+R8114/R8104 )

Figure 5-31: The voltage regulator

The voltage regulator in figure 5-32 is common in the memory VTT power supply,+3VALW is the control voltage of chip, VIN is the input voltage, REFEN is partial pressure of+1.5V to 0.75V,the conditions are satisfied, the chip output +0.75VSP from 4 pin. This chip is mainly used for the current amplification, can provide 1.5A current.

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Figure 5-32: Common voltage regulator in memory VTT power supply

There is also a commonly used voltage regulator 431L, as shown in figure 533,is the 1.24V precision voltage regulator:+3VPCU current limiting through R139,and stable output reference voltage of 1.24V through 431 L(C and R connected together, as a voltage regulator diode).

Figure 5-33: Precision voltage regulator 431L

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Chapter 6 The Use of the Circuit Diagram and the Point Bitmap (BoardView) The circuit diagram reflects the structure and working principle of the electronic circuit directly, so it is generally used in the design and analysis of the circuit. The electronic file format of laptop motherboard circuit diagram is *.PDF, a circuit diagram usually have dozens of pages to hundreds of pages, their ligature is horizontal and cross, and varied in form, beginners often do not know from where to start and how to read it. Understanding the motherboard diagram circuit is a threshold for maintenance personnel to further improve. We must have a certain basic knowledge. In addition, because the component on the laptop motherboard is too dense, even understand the principle in the circuit diagram; it is also quite difficult to find the damaged components in the real object. Some manufacturers did not even print components position number, which requires maintenance personnel must know how to use the point position diagram, in order to identify the location of components quickly and accurately.

6.1: The Use of the Circuit Diagram The file format of laptop circuit diagram is *.pdf. We can use Adobe Reader or Foxit software to open this file. When you open a drawing, in general, the first page is a schema or directory, as shown in figure 6-1.

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Figure 6-1: Architecture diagram

The figure marked the page where each function module, for example, CPU occupies page 4 and page 5.If you want to view the page with CPU, you can input the page number in the following page frame as shown in figure 6-2.

Figure 6-2: Page input box

In the figure 6-3, CLK_CPU and CLK_CPU_BCLK through the resistance, no longer regarded as the same signal, but to be regarded as two signals.

Figure 6-3: screenshot of the clock signal The pin name of components and the signal named by manufacturer cannot be considered the same concept, as shown in figure 6-4, PLTRST# is the pin name of C26 pin, but PLT_RST# is the signal named by manufacturer. Check where the signal connected to, you should find the PLT_RST#. Figure 6-5 is the test point T83 for factory testing use.

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Figure 6-4: PLT_RST# signal diagram

Figure 6-5: Circuit symbol diagram of the test point Jumper point/isolation point usually connected with tin directly, convenient to the troubleshooting, the circuit symbol shown in figure 6-6.

Figure 6-6 circuit symbol diagram of the isolation point

Figure 6-7: is the physical map of the isolation point

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Laptop Chip Level Repair Guide * or @ is printed on the device, indicating that the device is not installed in the board of the current version. NO STUFF also indicates that there is no installation. Not installed, it represents that both ends are disconnected, as shown in table 6-1:

Table 6-1: The list of some parts of the mainboard is not installed

If the parts are not installed, but cannot be disconnected, then add the "short" words, or connected with a straight line, as show in figure 6-8.

Figure 6-8 circuit diagram of parts direct connection The signal back with "#' "-L" or the front with "-", etc., indicates that the signal is active- low level. The word of "efficient" needs to be considered carefully, and need to combine with the English front of "#" to understand. As shown in figure 6-9, in fact. PERST# and 2231_SHDN# signals are high level in the boot state, but did not conflict with the expression of "active-low level".

Figure 6-9: Active-low level signal circuit diagram http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide In the common drawings, the digital followed by signal, indicates the page the signal connected to, but in the product drawing of IBM and Apple, as shown in figure 6- 10,75D3 and others indicate the place that the signal connected to page 75 coordinate position D-3,positioning is more accurate, it¡ s convenient to ® find signal.

Figure 6-10: Screenshot of Apple product circuit In addition, the direction of the arrow represents the trend of the signal, as shown in figure 6-1 but due to the randomness of drawing staff, leading to not believe all.

Figure 6-11: Screenshot of the signal When the line is crossed, only the point indicates that the line is connected together is as shown in figure 6-12. In the figure 6-13, the signal is the same kind of signal line, will be drawn together, to another page, then separate, not to say that these signal lines are connected actually.

Figure 6-12: The circuit diagram of cross connected and disconnected

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Figure 6-13: The similar signal circuit diagram

6.2: The Use of Common Point Bitmap (BoardView Software) l. CASTW----*.1st CASTW is the point position figure used by IBM, the most outstanding characteristics of this point position figure is that we can see the actual direction of signal. The red indicates that the signal is in the current layer, and the yellow indicates that the signal is in the other layer. Here "the other layer" refers to the other side of PCB and also refers to the middle layer of PCB. Here is the common use operations and shortcut menu shown in figure 6-14.

Figure 6-14: The screenshot of IBM BoardView software (point position figure)

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2. Test Link------*.brd The point position figure of Landrex corresponds to the file format of BRD. Common operations are as below: click C key to find components(also supports three components);click R key to find signal; double-click the left mouse button to enlarge; click the right mouse button to shrink; click R key to rotate the screen; click the space key to page. The specific operation can be viewed through "help" menu. Note the operation example of figure 6-15~figure 6-21, the signal found by clicking N key is "+15V" voltage. Voltage is also regard as a signal (or network).

Figure 6-15: The operation drawing 1 of Landrex point position figure http://www.XiuFix.com/laptop-chip-level-repair/

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Figure 6-16: The operation drawing 2 of Landrex point position figure

Figure 6-17: The operation drawing 3 of Landrex point position figure

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Figure 6-18: The operation drawing 4 of Landrex point position figure

Figure 6-19: The operation drawing 5 of Landrex point position figure

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Figure 6-20: The operation drawing 6 of Landrex point position figure

Figure 6-21: The operation drawing 7 of Landrex point position figure

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Figure 6-22: The schematic diagram 8 of empty pins When we click to select the pin of components, the name of signal will be shown in the below status bar. As shown in figure 6-22. A common operation is: when the welding plate appears the phenomenon of PIN dropping, we can refer to the point position figure, to check which PIN need to fill PIN and which don't need to fill.

3. Boardview------*.brd *bdv *bv The software of Boardview point position figure is used in the file of Tuo Fu (program BoardViewR4, the file format is *.brd), Hong Han (program BoardView, the file format is *.bdv), Wei Yang (program Board View 1.3, the file format is *.bv) and other company. The screenshot of Tuo Fu BoardViewR4 shown in figure 6-23, press the shortcut key "D" to find the components. Press the shortcut key "N" to find the signal.

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Figure 6-23: The interface map of Tuo Fu point position figure The screenshot of Hong Han shown in figure 6-24, press the shortcut key "D" to find the components. Press the shortcut key "E" to find the signal.

Figure 6-24: The interface map of Hong Han point position figure

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Laptop Chip Level Repair Guide The screenshot of Wei Yang B View 1.3 shown in figure 6-25, press the shortcut key "C" to find the components. Press the shortcut key "E" to find the signal.

Figure 6-25: The interface map of Wei Yang point position figure

4. TSICT------*.asc TSICT software is generally used by ASUS. Gigabyte also uses it. The common operations are as below. Click the "models" menu to load the file, if there are contents in the BOM box. Selected it and click the OK button is as shown in figure 6-26.

Figure 6-26: The schematic map of TSICT point position figure opening files

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Laptop Chip Level Repair Guide Input the device label in the input box on the left bottom to find the device; click "TOP" and "Bottom" to select the positive and negative side of the mainboard is as shown in figure 6-27.

Figure 6-27: The interface of TSICT point position figure finding the device

The mouse will be stopped on the device. Select "display connected devices and PAD" to find connected point from the context menu is as shown in figure 6-28.

Figure 6-28: The operation example of ASUS point position figure Click the right key in the blank position, and click Net query, you can find the signal, as shown in figure 6-29.

Figure 6-29: ASUS point position figure finding the signal http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide If you move the bitmap, and cannot find, you can click AUTO to automatically return to the initial state, as shown in figure 6-30.

Figure 6-30 the position map of AUTO key

Chapter 7 The Introduction of EC and BIOS EC (Embedded Controller) is a 16-bit single chip microcomputer. Which is featured in laptop, it is because of the use of EC, reflecting an important difference between laptop and desktop. In desktop, the keyboard and the mouse are independent of the system host is generally connected with the host system by PS/2 or USB interface. But in the laptop, in order to achieve the purpose of portability, it's necessary to use the built-in keyboard (matrix decoding keyboard) and the built-in mouse (such as the touchpad, TrackPoint are built-in mouse device).So the laptop needs a http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide special keyboard controller. The special EC of the laptop is equipped with this feature. Moreover, a most important problem in design of notebook is to make the system more power, increase the battery life, it must have good heat dispersion performance. And try to minimize the system noise. According to the temperature to control the stalling of CPU fan, laptop power management, such as laptop computer into standby or shutdown, the electric power dispatching of the external power supply system, power detection of intelligent battery, charging and discharging task, as well as some practical shortcut buttons. These important functions are accomplished by EC. In fact EC of the laptop is an extension of the traditional KBC (Keyboard Controller), equipped with two part function of KBC and embedded control, so EC is also called as KBC. EC is widely used in the design of laptop with intelligent power-saving function. It undertakes task of laptop built-in keyboard touchpad, laptop battery intelligent charging and discharging management and temperature monitoring and others.EC plays an important role in design of portable, intelligent personalized of the laptop. EC interior has a certain capacity of Flash to store the EC code. The position of EC in the system is not next to the North and South Bridge, in the process of open system.EC control the timing sequence of most of important signal. In laptop, no matter in the boot or shutdown state, EC is always open, unless the battery and adapter completely removed. In the shutdown state.EC has kept running, and waiting for the user's boot information. And after the boot, EC continue to control the keyboard controller charging indicator light and fan and other device, and even control the system standby, sleep and other state. BIOS is the abbreviation of "Basic Input Output System" in English. And the Chinese name is "basic input/output system" after literal translation. In fact, it is a group of program curing to a ROM chip on the computer motherboard, holds the most important basic input/output program, the system settings information, self-check program after booting and the system self-triggered program of the computer. Its main function is to provide the lowest level and the most direct hardware setup and control for the computer. It should be noted that although the BIOS is referred to the program curing in the ROM, but in maintenance, we usually called the ROM chip curing the program as BIOS. Figure 7-1 is the physical map of EC and BlOS. A large square chip is EC. A small rectangle chip is BIOS.

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Figure 7-1: The physical map of EC and BIOS

7.1: The Working Conditions and Functions of EC l. The basic working condition of EC (l)Standby power supply: the name of EC standby power supply is usually VCCCK AVCCx VCCA, etc., a small number of EC standby power supply is VBAT. (2)Standby lock: it's usually an external 32.768 kHz crystal before, now most is free of crystals. (3)Standby reset the most beginning of the EC reset signal, which name is usually ECRST WRST#, VCC_POR# etc. The reset of SMSC H8S is RES*. (4)Program: EC need to get the corresponding program, configure the GP1O pin, then to Work. The program may be stored in the EC. Also may be stored in the ROM under EC.

2. The bus communicated EC and the South Bridge EC connects with the South Bridge by LPC (Low Pin Count) bus. VCC3: the power supply of LPC bus, 3.3V. http://www.XiuFix.com/laptop-chip-level-repair/

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LPCCLK: LPC CLOCK provides 33MHz frequency for LPC, about 1.6V. LRESET#: LPC reset signal, 3.3V. LPC_AD [0:3]: address data complex line. These four signals are used to transmit the address and data of LPC bus. LPC_FRAME#: the cycle frame of LPC, when this signal is active, indicates the start or end of a cycle of LPC.

3. EC controls LCD backlight LID_SW#: lid-close switch. There are two functions of LID_SW#: in shutdown state, this signal is used for EC to determine whether it can turn on; pull down this signal after starting up, which can turn off the backlight. Commonly, now is using the Hall component (magnetic sensor, Hall Effect) to control this signal. LCD_BACKOFF: backlight control LCD_BL_PWM: brightness control.

4. EC manages the battery charging (1) Pre-charge If the battery voltage is less than 0.9V, it is determined that the battery has been damaged, will not charge the battery, because charging the damaged battery may cause safety problems, such as the explosion or burning. When the battery voltage is lower than the discharge end voltage(3V) and greater than 0.9V,with 1/10 current of the constant current charging current to charge with small current, and the time is short, generally for a few minutes. If you use a large current to charge the battery with full discharge, it will damage the battery. (2) Constant current charging When the battery voltage is greater than a certain threshold, it will be the constant current charging, and the feature is constant current Most of the energy of the battery (80%) is stored at this stage for a long time. The charge current is generally controlled at an appropriate value, if the value is too large, which will affect the charging efficiency, and the capacity will be reduced after full.

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Laptop Chip Level Repair Guide (3) Constant voltage charging When the battery voltage reaches the end voltage of the charging, the battery is charged with constant voltage, and the feature is that the battery voltage is kept constant. The charging current is gradually smaller. When the current is less than 1/10 of constant current charging current, charging end, the battery capacity will be fully replenished. (4) Trickle charge When the charging current is less than 1/10 of the value of constant current charging, the charging current is close to 0, which is the trickle charge. And the feature is the battery voltage constant. The purpose is to supplement the selfdischarge of the battery; the self-discharge rate off the lithium battery is usually 5%~10% per month.

5. How to judge whether EC comes with the program EC needs the program (EC CODE) configuration to complete its various work. The program may be stored in its internal ROM, also may be stored in the motherboard BIOS. If the EC comes with the program, when doing maintenance, you must find the same motherboard to disassemble. If EC not comes with the program, you can find the same type of chip to replace. How to judge whether EC comes with the program? First, observe the appearance, EC with stickers > marked on the surface is usually bring their own procedures.EC in the figure 7-1 not comes with the program, and EC in the figure 7-2 comes with the program.

Figure 7-2: EC comes with the program

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Laptop Chip Level Repair Guide Second, observe the architecture, in machines can be repaired on the current market, there are four kinds of connection ways for EC and BIOS, as shown in figure 7-3.

Figure 7-3: The relational graph of EC and BIOS

Firstly, BIOS connects to EC through X-BUS and SPI bus, and then EC connects to the South Bridge through LPC, in general, in this case, EC code is placed in the BIOS, that is share a chip with BIOS. Secondly, BIOS connects to the South Bridge through SPI bus, there is not ROM under EC, it uses its own internal ROM. Common in ThinkPad and Apple, some models of the latest Lenovo also use this way. Thirdly, the main BIOS connects to the South Bridge through SPI bus, hang a SPI ROM chip under EC for storing EC CODE, such EC is not comes with the program. Fourthly, EC and the South Bridge connect BIOS through SPI bus, such EC is not comes with program.

7.2: The Function and Working Conditions of BIOS BIOS is the program to provide the lowest level and the most direct hardware control in the computer system. It controls the input device and output device of the computer system, and is a hub connected the software program and hardware device. For the PC, B1OS includes the controlling keyboard, display screen, disk drive, serial communication device and some other functions of the code. The computer technology develops into today, there are all kinds of new technologies, many of the techniques of software part is to use BIOS to manage

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Laptop Chip Level Repair Guide and accomplish. For example, PnP technology (Plug and Play) is accomplished by adding PnP module in the BIOS. Again, the hot swap technology also transmit the hot swap information to the configuration management program of BIOS by the system BIOS, and reconfigured(such as interruption, DMA channel and other allocation) by the program, In fact, the hot swap technology is also PnP technology.

In addition to the motherboard, on the other device, such as network card, graphics card, MODEM, digital camera, hard disk and so on, are also have the so-called BIOS, some SCSI cards and some interface cards with special function also have its own BIOS. For example, BIOS on the graphics card is used to complete the communication between the graphics card and the motherboard. The start and using of the hard disk also needs HDD BIOS to complete. In the process of the boot, the mainboard BIOS will call and execute these additional BIOS program complete the initialization of this hardware. So theoretically speaking, each kind of hardware can have its own BIOS. But too many BIOS, it will not only increase the cost, and will lead to compatibility problems, therefore, in general, integrated the standardized device in the motherboard, for those unique specification of manufacturers, appears with the form of additional BIOS. These BIOS on the external and the motherboard BIOS using Flash ROM as BIOS ROM chip, also easy to upgrade, to modify its defects and enhance its compatibility.

l. The function of BIOS (l) POST power on self-test: after the computer power-on, POST (Power On Self-Test) program check each device in the system. Usually complete POST includes to test CPU, 640KB basic memory, more than 1MB of extended memory, ROM, CMOS, memory, serial and parallel graphics card soft and hard disk and keyboard, once found the problem during self-test, the system will give message or whistle warning, (2) BIOS system start the bootstrap program: after the system finishing POST self-test, ROM BIOS according to the boot sequence stored in the system CMOS settings to search the soft and hard disk drives and CD-ROM, network server and others for booting drive effectively, read the operating system boot

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Laptop Chip Level Repair Guide record, then give the system control power to the boot record, and completed the sequence boot of the system by the boot record. (3) Interrupt service routine: responsible for the allocation of the motherboard hardware interrupt number assigned. (4) Program settings: refers to enter the CMOS settings after booting.

2. BIOS capacity identification For example, the model of SST 39VF040, three digits with underlined are different, representing different capacity: 001/010/100: 1M=128KB 002/020/200: 2Mb=256KB 004/040/400: 4Mb=512KB 008/080/800: 8M=1MB 160: 16Mb=2MB 320: 32Mb=4MB 640: 64Mb=8MB Note: 8b (bit) =1B (byte)

3. The package type of BIOS There are many kinds of BIOS package, the specific as follows. (1) TSOP48 BIOS with TSOP48 package are under EC, through X-BUS, the material object shown in figure 7-4.

Figure 7-4: BIOS with TSOP48 package http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide The definition of BIOS pins is shown in figure 7-5.

AO~A18: the address line

DO~D15: the data line

VCC: Power Supply 3.3V OE#: output enable

CE#: Chip select WE#: write enable

RESET#: reset VSS: ground connection

Figure 7-5: The definition of BIOS pins with TSOP48 package

(2) TSOP40 BIOS with TSOP40 package are generally X-BLJS bus, the material object shown in figure 7-6, and the definition of pin shown in figure 7-7.

Figure 7-6

the material object of BIOS with TSOP40 package

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Figure 7-7

the definition of X-BUS BIOS pin with TSOP40

(3) TSOP32 BIOS with TSOP32 are generally X-BUS bus, pin function is similar to TSOP40, the definition of pin shown in figure 7-8.

Figure 7-8 the definition of X-BUS BIOS pin with TSOP32 package http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide (4) PLCC32 BIOS with PLCC32 package are also X-BUS bus in the laptop, the definition of pin shown in figure 7-9, and the material object shown in figure 7-10.

CS#: chip select OE#: enable WE#: write enable VCC: power supply pin GND: ground AO~A17: the address signal line DO~D7: the data signal line Figure 7-9: The definition of X-BUS BIOS pin with PLCC32 package Figure 7-10: The material object of BIOS with PLCC32 package

(5) SOPS8 BIOS with 8 pin are SPI bus, the definition of pin shown in figure 7-11, the material object shown in figure 7-12.

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CS#: chip select

SO: serial signal output

GND: ground

SI: serial signal input

HOLD: pause

WP#:write protection SCLK: serial clock

VCC: power supply Figure 7-11: The definition of SPI bus BIOS pin Figure 7-12: The material object of SPI bus BIOS

(6) SOP16 BIOS used by IBM X200 part of the model uses 16 pin SPI bus, the definition of pin shown in figure 7-13,the material object shown in figure 7-14.The definition of pin is similar to 8 pin SPI,NC is Not Connected.

Figure 7-13 the definition of SPI bus 16pin BIOS Figure 7-14 the material object of SPI bus 16 pin BIOS

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Chapter 8 The Basic Working Process of Laptop Computer As professional laptop computer maintenance, personnel, in addition to have a certain basic knowledge, also need to understand the working process and Intel chipset standard timing of the laptop and other maintenance theories knowledge. This chapter focuses on the boot process and Intel standard timing.

8.1: The General Boot Process of Laptop Computer The working process of the laptop follows a certain sequence. In the repair of the laptop, in most cases, Timing applied on the power-on part in the system boot, so also called Power Sequence. Mainly refers to a laptop motherboard having done from standby to CPU get RESET signal. So literally, timing is time and sequence. The motherboard from standby to power-on, and then to CPU work, we feel just a short time.is almost a second, but in the work of the motherboard, it will happen a lot of things in a second, from the standby voltage producing.to press the switch, and to the motherboard received the switch signal, then to send out each working voltage. And the motherboard made so much action; it will strictly obey an established order, that is to say, in the process of these steps, if the first step isn't completed. Then the next step is not start. And there is a strict time requirement between each step, some will be accurate to a few milliseconds, for example, PWRGD Signal generation requires that each voltage stabilize about 5ms will be sent.

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Laptop Chip Level Repair Guide From the above introduction, we can see that the timing has very important significance for the normal working of a motherboard, the most common fault, such as no electricity, no boot and others, there have an important relationship with the timing. It can be said that if you master the timing, then you have a basic idea of maintenance for all kinds of faults of the laptop.

8.1.1 Hard starting process and Intel chipset standard timing 1. Hard starting process in general. The boot process of the laptop with Intel chipset (below series 4) is as follows: (a) Without any electrical equipment supply power (no battery and no power), through 3V button battery to produce VCCRTC to supply RTC circuit of the South bridge, to keep the operation of the internal time and save the CMOS information. (b) After plugging in the battery or adapter, produce the common point. (c) Then produce the EC standby power supply (usually linear voltage), after the standby power supply is normal, EC supply power to crystal oscillator to produce the EC standby clock, the standby power supply delay produce EC reset, EC reads the program configuration own pin(BIOS chip select waveform as shown in figure 8-1).

Figure 8-1: BIOS chip select waveform http://www.XiuFix.com/laptop-chip-level-repair/

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(d) If EC detected the power adapter, it will automatically send a signal to open the standby power supply of the South bridge (VCCSUS3_3, V5REF_SUS), and send RSMRST# signal to the South bridge to notice the South bridge that the standby voltage is normal; if EC is not detected the adapter (battery mode), EC need to receive the switch trigger signal, then will open the South bridge standby power supply, to save power. (e) Press the switch, after EC receiving the switch signal, delayed send a highlow-high boot signal to the South bridge PWRBTN# pin. (f) After the standby condition of the South Bridge is normal and receiving PWRBTN# signal, raising SLP_S5#, SLP_S4#, and SLP_S3 #signal in turn. (g) SLP_S5# or SLP_S4# control the production of the memory main power supply etc,SLP_S3#control the production of the bridge power supply. The bus power supply (VCCP), the independent graphics power supply etc. (some is controlled directly by SLP signal. And some is controlled by EC after SLP sending to ECX (h) EC delay send signal or other circuit switching to open CPU core voltage (VCORE).Thus, the voltage of the machine has been fully opened. (i) After CPU power supply being normal, CPU power management chip send PG to the South Bridge VRMPWRGD pin at last. (j) After CPU power supply being normal, open the clock chip through the conversion circuit then produce various clocks. (k) The South bridge received the power supply, clock, VRMPWRGD, and received EC or power supply circuit delay conversion PWROK, the South bridge will send CPUPWRGD to inform CPU that its core voltage has been successfully opened, and send PLTRST# and PCIRST# signal at the same time. (l) After the North bridge receiving PLTRST#, send CPURST# signal to CPU, then CPU officially start to work. The above is the hard start process of the laptop. In the process of hard start we can divide the power supply of the laptop into 4 levels. (1) G3 power: voltage generated just plug the power, generally supply to power switch and EC, is usually produced by linear way.

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(2) S5 power: the standby voltage of the South bridge, supply to VCCSUS3_3 of the South Bridge, power in the state of power off is usually produced by PWM way. (3) S3 power: the power supply of the memory, the power in the state of S3 sleeping. (4) SO power: the main power supply to the normal operation of the machine also called RUN power, including the bridge main power supply, the bus power supply, CPU power supply and others. Sometimes, 3V, 5V produced by PWM way under the condition of G3 or S5 are also called the system power supply. For example, Quanta series PCU voltage is the system power supply. But it exits under the condition of G3.And for example: ASUS A8E South bridge standby voltage is produced by PWM way it is the system power supply.

2. Intel The Intel chipset standard timing as figure 8-2 is Intel chipset standard sequence diagram.

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Figure 8-2: Intel Series-4 Chipset Standard Sequence Diagram

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Laptop Chip Level Repair Guide According to the sequence diagram shown in figure, 8-2 is explained as follows. (1) System State G3: the power of the whole system are closed.

(2) The interpretation of the signals  VCCRTC: the power supply of the South bridge RTC circuit, 3V, supply power to CMOS chip (RAM) inside the South Bridge.  RTCRST#: the reset signal of the South bridge RTC circuit, 3 V.1CH9 added another RTC reset signal later, the name is SRTCRST#.  32.768 kHz: after the South Bridge receiving VCCRTC and RTCRST #, supply power to the crystal oscillator. The crystal oscillator running. The voltage of two pins of the crystal oscillator is 0.1-0.5 V.  V5REF_SUS:5V standby voltage.  VCCSUS3_3: 3.3V standby voltage.  VCCSUS1_05: The South Bridge internally produced the power supply 1.05V for itself, not to consider this voltage when we analyze the timing.  RSMRST#: inform the South Bridge that 3.3V standby voltage is normal. The external circuit controls voltage 3.3V.  SUSCLK: after the South bridge receiving RSMRST#, then send the 32kHz clock, most machines do not use, it can be ignored.  PWRBTN#: POWER BUTTON, 3.3V-0-3.3V pulse signal.  SLP_S5#: 3.3V, the control signal when the South Bridge exit the power off state.  SLP_S4#: 3.3V, the control signal when the South Bridge exit the dormant state. (Usually just use S5# or S4#, used to control the production of the memory power supply, and another is idle.)  SLP_S3#: 3.3V, the control signal when the South bridge exit the sleeping state. (usually used to control the bridge power supply, the bus power supply, the independent graphics power supply, CPU power supply etc.)  VDIMM: the memory power supply.  VCORE/VCC: refers to the bridge power supply, the bus power supply, the independent power supply, CPU power supply etc.  VRMPWRGD: inform the South Bridge that CPU power supply is normal, 3.3V. CLK GEN: the clock chip starts to work, send various clock. http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide  PWROK: inform the South bridge that power supply is normal (SLP_S3# complete task), 3.3V. CPUPWRGD: The South Bridge sends PG to CPU, 1.05V.  PLTRST#: the platform reset, the South bridge send the first reset, 3.3V is generally sent to the North bridge, EC, MINI slot etc.  PCIRST#: PCI reset, the South bridge send the second resettle 3.3V computer is not usually used.  CPURST#: after the North bridge receiving PLTRST#, send the reset of CPU, 1.05V.

8.1.2 The soft start process Next to the Intel Bridge (such as GM45) as an example, see CPURST#, addressing process of CPU and power-on self-test process. In the process of the computer hard start, CPURST reset signal is sent and keep a low level of a certain time, when the power supply circuit has been stable, then removed the RESRT low level and keep a high level, CPU start to work, the hard start finished, and start to the soft start. 1) CPU will check FSB front bus line is busy or not through the DBSY# signal of the interface circuit. When DBSY# is low level, it means that FSB bus is busy, only released it, CPU will be the next step work; when DBSY# is high level, it means that FSB is not busy, CPU will through ADS# address strobe signal line to tell the North Bridge ready to send the data. ADS waveform is as shown in figure 8-3. 2) After the North bridge receiving this signal, if it's in good condition and has been ready, the North bridge will send a low level of H_TRDY# to CPU, told the CPU is ready, and can receive the data. Then CPU will through A31~AO send FFFFOH address signal, which is a jump instruction in the BIOS.AO-A31 to FSB front bus interface of the North Bridge, through FSB frequency conversion. Level conversion and address decoding send to the North Bridge. After the North, bridge receiving CPU addressing instruction. Through DMI, bus sends to the South Bridge. The North bridge and the South bridge DMI bus consists of 16 lines, point to point transmission, signal lines including DMI _RXP(0:3), DMI_RXN(0:3), DMI_RXN(0:3), DMI_TXN(0:3), as shown in figure 8-4.

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Figure 8-3: ADS# Waveform

Figure 8-4: DMI bus signal diagram 3) After the South Bridge receiving the addressing instruction of the North Bridge. Then start to search BIOS, first search whether there is BIOS on the PCI bus (see figure 8- 5).When there is no BIOS on PCI bus. According to the PCI bus signal set to determine where BIOS is. If the BIOS is under EC, after the South Bridge through PCI decoding module, then to communicate with EC on the LPC bus. When EC receiving the addressing instruction, after that through X-BUS or SPI bus to BIOS. BIOS returns the data to the CPU, CPU running POST self-check program in the BIOS, and start self-check action.

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Figure 8-5: BIOS location settings

The key signal to determine whether PCI bus action: PCI_FRAME# (Cycle Frame). PCI frame period signal is low level; it means that PCI bus start work. And when it is high level, it means that PCI bus is not to work. The key signal to determine whether LPC bus action: LPC_FRAME# (LPC frame period). The key signal to determine whether BIOS action: CS# (chip select).Selected when low level, and is not selected when high level.

4) After CPU reading BIOS self-test correctly, and then start to execute the process of POST instruction. (a) When CPU addressing is normal, received POST self-test program returned by BIOS, then start initialized the chipset(the South bridge and the North bridge),and also initialized PCI-E bus(independent graphics). (b) After the South Bridge initializing, grab the memory through SMBUS bus to be initialized, the waveform is shown in figure 8-6. (c) After the memory self-test finishing, BIOS stores the self-test program into the memory. (d) Then called the BIOS program from the memory to test each device one by one, such as the keyboard controller, network cards, sound cards etc. (e) Testing the graphics cards, find BIOS of the graphics cards, and call them to complete the initialization of the graphics cards. (f) The graphics cards starts to read the screen information through ED1D bus (shown in figure 8-7), after reading the screen, then sends a signal to open the screen power supply and backlight. http://www.XiuFix.com/laptop-chip-level-repair/

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Figure 8-6: SMBUS waveform of the memory

Figure 8-7: EDID waveform

(g) Display the boot picture, and start to test the extended memory and give the corresponding address. (h) Test some standard equipment, including hard disk, CD drives, serial ports, parallel ports, floppy drive etc. (i) After testing the standard equipment, the plug and play code supported by the system will start to test and configure the plug and play equipment in the

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Laptop Chip Level Repair Guide system, and distributes the interrupt address, DMA channel and I/O port and other resources for this equipment. (j) After all hardware testing and being assigned the interrupts address, that is, all the hardware set up a hardware system, then it will generate a ESCD file (it is the method that the system BIOS exchange hardware configuration information for the operation system, the data is in CMOS), CPU will compare the generated ESCD with the last ESCD if finds the difference, it will update the data in ESCD. (k) After updating ESCD, CPU will complete POST and the interrupt service routine. Then carry out the bootstrap program of the system. The boot code of the system BIOS start the operating system according to the boot sequence specified by users, find the boot files in the starting device first then write in the memory, BIOS give the control power of the computer to the boot files. The operation system guided by the boot files, such as Windows XP, Windows 7 and so on.

8.2: About ACPI Specification 8.2.1 ACPI summarize ACPI (Advanced Configuration & Power Interface) is the standard of the advanced configuration and the power interface. Before ACPI proposed, the universal power management standard is APM with a BIOS level developed by Microsoft. ACPI is to replace the previous APM. ACPI is jointly developed by Intel, Microsoft, Toshiba, is to have a common power management interface between the operating system and the hardware, and to improve the disunity interface developed by the different manufacturers on the power management before. From Windows 98/SE, Windows ME and Windows 2000, Windows XP starting to support ACPI. From the laptops to the desktops and servers are included in this specification. ACPI can make the system to enter a low power consumption of "sleep state", such as standby and sleep; the purpose is to control the power consumption of the computer. All state of ACPI can be divided into G (Global), D (Device), S (Sleeping), C (CPU). http://www.XiuFix.com/laptop-chip-level-repair/

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8.2.2 G (Global) State of ACPI Global refers to all system, and can be divided into the following 4 kinds. 1) GO: Working state. The user program can be executed normally. But the device dynamically allocates their own state. When not used this device. This device can enter other non-operating state. Under this state, the system responds the external events in real time. And the machine cannot be disassembled and assembled under this state. 2) G1: Sleeping state. Under this condition, the system consumes less power, and no user's program is executed. The system looks like in the shutdown state. Because the display screen is turned off at this time. As long as any wake-up activation events message into the system, it will soon be restored to a working state. Under this state, the machine cannot be disassembled and assembled. 3) G2/S5: Soft Off state. System only keeps very little power under this state, no users and the operating system programs are executed. The state takes a long time to return to a working state. Under this state, the machine cannot be disassembled and assembled. 4) G3: Mechanical Off state. Under this state, the power of the whole system is closed, there is no current through the system, and the system can only reopen the power supply switch to active. Under this state, the power consumption is zero.

8.2.3 D (Device) State Device refers to some devices, such as modems. Hard drives, CD-ROM, etc. also can be divided into the following 4 kinds. 1) DO: Fully On. The normal working state. 2) Dl: It can save less power consumption; the device function with keeping activities is much more than which in D2 state. The device itself determines this state. And some devices cannot enter into the Dl state. 3) D2: Some functions are shut down; it can save a lot of power. The device itself determines this state; some devices cannot enter into the D2 state. 4) D3: Off. The power of the device under this state is completely removed, so the next time when the power is supplied once again, it needs the operating http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide system to make a setting again. Under this state, the device does not decode the addressing line. This state needs the longest wake-up time. All devices can enter into this state.

8.2.4 S (Sleeping) State of ACPI S state means Sleeping, and refers the system enter into the sleeping state in G1, also can be divided into SO, S1, S2, S3, S4, S5. 1) SO: In fact, this is our normal working state, all devices are fully open, and the power consumption is generally more than 80 W. 2) SI: CPU internal clock has been shut down under this state, but the contents of the system (CPU, Cache, chipset) are not lost, the other parts are still working normally. At this time, the power consumption is generally below 30W. In fact, some of CPU cooling software is developed in this working principle. 3) S2: Similar to SI, at this time. CPU is in the state of stop, the content of CPU and Cache has been lost, and the bus clock is also shut down, but the rest of the device is still running. 4) S3:This is STR(Suspend to RAM) we familiar with, in addition to the information of the memory, the content of CPU, Cache, chipset is lost the content of the memory is provided by the hardware, the power service data is exist. The power consumption is less than 10W at this time. 5) S4: is also called STD (Suspend to Disk), the system main power supply is shut down, but the system information will stored in the hard disk. By the operating system implementation after Windows 2000, all the data of the memory saved to hiberfil.sys file in the hard disk, the hard disk is not charged. 6) S5:A11 devices are shut down. Which is soft shutdown, the power consumption is closed to 0. The most commonly used is the S3 state, that is Suspend to RAM state, referred to STR.As the name implies, STR is that to save the data of the working state before the system entering STR into the memory. Under the state of STR, the power still continues to supply the power for the most necessary devices, such as memory, to ensure that the data is not lost, while other devices are in a closed state, the power consumption of the system is very low. Once we press the power button, the system will be awakened immediately read the data from the memory and return to before working state of STR. The read-write speed of the

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Laptop Chip Level Repair Guide memory is very fast, so users feel that it takes just a few seconds to enter and leave STR state. And S4 state, that is, STD, the data is stored in the hard disk. Because the read/write speed of the hard disk is much slower than the memory, so it does not so fast like STR in using.

8.2.5 C State of ACPI The C state of ACPI refers to the state of CPU, and can be divided into the following 5 kinds. 1) C0: the normal working state of CPU. 2) C1: CPU suspends work automatically, the software is completely unaffected under this state, and there is a minimum time to wake up. The hardware wakeup time in this state must be small enough, so the operating software can completely ignore the hardware wake-up time in this state when determine whether use this device or not. 3) C2: Similar to Cl, the South bridge send STPCLK# to CPU, and stop CPU internal clock, but CPU continues to monitor the consistency of the bus and cache. The sequence of CO-C2-CO is shown in figure 8-8.

Figure 8-8: The sequence of C0-C2-C0

5) C4: Similar to C3 sleeping state, after the South Bridge sending STP_CPU and closing CPU clock, the South bridge send DPRSLPVR and DPRSTP# signal to CPU power management chip, to close the CPU core voltage. The sequence of CO-C4-CO is shown in figure 8-10.

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Figure 8-10: The sequence of C0-C4-C0

8.2.6 The power and the control signal of ACPI 1) 3VSB:3.3V standby voltage, supply the power to the wake-up of ACPI controller, the network card, PCI and others in the South bridge.3SVSB is the customary name, the name of each manufacture is different, but the same chipset, the name in the South bridge is the same. The standard name of 3VSB in the three chipset: Intel is VCCSUS3_3; nVIDIA is +3.3V_DUAL; AMD is S5_3.3V or VDDIO_33_S. 2) RSMRST#: the normal signal of the standby voltage. The voltage is 3.3V. The name of RSMRST# in the three chipset: lintel and AMD are RSMRST; nVIDIA id PWRGD SB. 3) SLP_S3#, SLP_S4#, SLP_S5#: the signal of the low level control enter S3,S4,S5state.Forexample,the system is in the state of SO when running normally, three signals should be invalid, is 3.3V. SUSB#, SUSC# and others

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Laptop Chip Level Repair Guide are similar to SLP_S*# signal. The state of the sleep signal in each sleeping state is shown in figure 8-11.

Figure 8-11: The state of the sleep signal in each sleeping state PWRBTN#: Power Button. At shutdown, pull low PWRBTN# signal, ACPI will set high SLP_S5#> SLP_S4#^ SLP_S3# to 3.3V in turn. If PWRBTN# continues being the low level for 4s, the system will be forced into the S5 state.

8.3: Clock, PWRGD and The Reset Circuit If we analogy to the each device of the computer system is a group of people, then the clock chip is like a password. But this is not a password, is the group with integrated multiple password. It provides the different frequency to the main system chip and the slot on the motherboard, but there will have the same frequency between connected devices, then it can exchange data information normally between these chips. PG and the reset in this section are for the South Bridge. One is the working condition of the South Bridge. And another is the affair the South Bridge done after getting this working condition.

8.3.1 The clock circuit 1. The working condition of the clock chip. 1) As shown in figure 8-12, the working condition of the clock chip is following: The power supply: +3VS produces +CLK_VDD> +CLK_VDD1 through L16 and L32 and provides 3.3V, +1.05V produces +CLK_VDDSRC through L15 and provides 1.05V. 2) The open signal CK_PWRGD/PD#: the high-level 3.3V opened. http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide 3) 14.318MHz reference crystal Y2. 4) CPUJSTOP^ PCI_STOP#: CPU and PCI clock stop instructions needs to be the high level when working normally. 5) SMBCLK SMBDATA system management bus: used to transfer BIOS instructions. 6) FSLA> FSLB> FSLC frequency selection: according to the different CPU to produce the different front bus clock.

2. GM45 -The clock signal distribution of GM45 chipset The clock signal distribution of GM 45 chipset is shown in figure 8-12, the specific is following. 1) CLK_CPU_BCLK, CLK_CPU_BCLK# of 71, 70 pin is the front bus clock that the clock chip send to CPU, more than 100MHz, the specific value is set by FSA/FSB/FSC. 2) CLK_MCH_BCLK> CLK_MCH_BCLK# of 68,67 pin is the front bus clock that the clock chip send to the North bridge, more than 100MHz,the specific is set by FSA/FSB/FSC. 3) 24,25,28,29 pin is the set display clock that the clock chip sends to the North bridge, 96MHz and 100MHz. 4) 32, 33 pin is the SATA controller clock that the clock chip sends to the South Bridge, 100MHz. 5) 35, 36 pin is the PCI-E module clock that the clock chip sends to the South Bridge, 100MHz. 6) 57, 56 pin is 100MHz core clock that the clock chip sends to the North Bridge. 7) 44, 45 pin is 100MHz clock that the clock chip sends to MIMI PCI-E slot, used for wireless network cards, etc. 8) 48.47 pin is 100MHz clock that the clock chip sends to the onboard card. 9) 15 pin is 33MHz clock that the clock chip sends to the EC chip. 10) 17 pin is 33MHz clock that the clock chip sends to the South Bridge, used in the reset circuit in the South Bridge.

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Laptop Chip Level Repair Guide 11) 20 pin is 48MHz clock that the clock chip sends to the SD card reader chip and USB controller in the South Bridge. 12) 7 pin is 14.328MHz reference clock that the clock chip sends to the South Bridge. 13) 58, 43, 46, 21 pin is the request signal of each clock, the low level is effective.

Figure 8-12: The clock signal distribution of GM45 chipset

3. HM55 The clock signal distribution of HM55 chipset The clock signal distribution of HM55 is shown in figure 8-13, the characteristic is that the clock chip is just sent to PCH clock, and then sent out each clock by PCH to other devices. If it supports the display stand, the display set supports DVI/DP/HDMI/e-DP interface. The bridge needs 25MHz crystal.

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Figure 8-13

4. The clock signal distribution of above HM65 chipset The clock signal distribution of above HM65 chipset is shown in figure 8-14, the characteristic is that it must be 25MHz crystal when the bridge integrates the clock chip.

Figure 8-14: The clock signal distribution of above HM65 chipset http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide 5. AMD- The clock signal distribution of AMD double bridge chipset The clock signal distribution of AMD double bridge chipset is shown in figure 8-15, the clock chip sends each clock, but is just not responsible for sending 33MHz clock, 33MHz clock is sent by the South bridge.

Figure 8-15: The clock signal distribution of AMD double bridge chipset

6. AMD- The clock signal distribution of AMD single bridge The clock signal distribution of AMD single bridge is shown in figure 8-16, the characteristic is | that the bridge integrates the clock chip.

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Figure 8-16: The clock signal distribution of AMD single bridge chipset

7. nVIDIA- The clock signal distribution of nVIDIA chipset The clock signal distribution of nVIDIA chipset is shown in figure 8-17; the characteristic is that the bridge integrates the clock.

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Figure 8-17: The clock signal distribution of nVIDIA chipset

8.3.2 PWRGD and the reset circuit The explanation of VRMPWRGD, PWROK, CPUPWRGD, PLTRST#, PCIRST# signal in the South Bridge is following: VRMPWRGD: this signal should be connected to the PWRGD signal of CPU power supply chip, used to indicate that the CPU core voltage is stable. This signal phase with PWROK signal is in the South Bridge. The text of VRMPWRGD pin definition is shown in figure 8-18. VRMPWRGD

I

VRM Power Good: This should be connected to be the processor's VRM is stable. This signal is internally ANDed with the PWROK input. Figure 8-18: The screenshot the text about VRMPWRGD pin definition

PWROK: when the signal is effective, PWROK inform that all power of ICH has been generated ' and stable for 99ms, PCICLK has been stable for http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide 1ms.When PWROK becomes lower level, ICH produces PLTRST# with low level. Note: PWROK must be inactive for three RTCCLK clock cycles at least. The screenshot of the text about PWROK pin definition is shown in figure 8-19. CPUPWRGD: CPU power good, this signal should be connected to PWRGOOD pin of the processor, indicates that CPU power supply is effective. This is an output signal, formed by the phase of PWROK and VRMPWRGD. The text of CPUPWRGD pin definition is shown in figure 8-20.

Figure 8-19: The screenshot of the text about PWROK pin definition

Figure 8-20: The screenshot of the text about CPUPWRGD pin definition

PLTRST#: ICH produces PLTRST# signal to reset all devices (such as SIO, FWH, LAN, GMCH, TPM, etc.) on the entire hardware platform. When PWROK and VRMPWRGD are high level, ICH will delay 1ms and drive PLTRST# to be high level. The text of PLTRST# pin definition is shown in figure 8-21.

Figure 8-21: The screenshot of the text about PLTRST# pin definition

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Laptop Chip Level Repair Guide PCIRST#: This is the second reset signal, which is produced by the PLTRST# delayed buffer. The text of PCIRST# pin definition is show in figure 8-22.

Figure 8-22: The screenshot of the text about PCIRST# pin definition

At last, after the RST1N# pin (the pin definition is shown in figure 8-23) of the North bridge receiving PLTRST# sent by the South bridge. Delayed 1ms send CPURST# to CPU, to complete the hard start. HCPURST# pin definition is shown in figure 8-24.

Figure 8-23: The screenshot of the text RSTIN# pin definition

Figure 8-24: The screenshot of the text about HCPURST# pin definition

The sequence of the reset circuit is as shown in figure 8-25.

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Figure 8-25: The sequence of the reset circuit

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Chapter 9 The Explanation of PWM Circuit PWM is that pulse width modulation; it is a very effective technique of using the digital output of the microprocessor to control the artificial circuit, is widely used in many fields from measurement, communication to power control and transformation. This way is used in most of the power supply circuit in the laptop. Compared with the linear regulated power supply, the PWM circuit has the advantages of high efficiency, high output power, but also has the disadvantages of complex circuit.

9.1: The Introduction of PWM Circuit The PWM circuit in the laptop motherboard is generally composed of PWM chip, MOS, the coil, and the capacitance.

9.1.1 Introduction to PWM Working Principle The brief introduction of the working principle of PWM regulates the output voltage by adjusting the effective pulse period T1, which accounts for the proportion of the entire pulse period T (duty cycle).As the figure 9-1 an example, the validity period of the highest voltage amplitude is about 5V, the duty ratio is about 50%, so the output voltage is 5V x 50%=2.5V.

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Figure 9-1: PWM waveform

1. PWM The working principle of PWM power supply The principle of PWM power supply circuit is shown in figure 9-2,PWM chip controls the high speed switch of the upper and lower tube to adjust the voltage, when the upper tube is opened, the VIN passes through the upper tube to charge LC energy storage circuit and supply power to the rear; the chip through FB monitor to charge full, then closes the top tube, and opens the down tube, forms the discharge circuit of LE energy circuit, and continues to supply power to the rear.T1 in the figure is the open state,T2 is the closed state, as long as control the duty cycle of T1,then it can control the height of output voltage.

Figure 9-2: The principle figure of PWM power supply circuit

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Laptop Chip Level Repair Guide 2. PWM The working process of PWM power supply The specific working process of PWM power supply can be subdivided into four stages: (1) Before T1, the dead time, the top tube and down tube are cut off, at this time, the top and down tube drive signals are low level and two tubes are cut off. (2) The period of timeT1, the top tube drive signal is high level. The down tube drive signal is low level, at this time, the top tube is conducted, and the down tube is cut off. VIN voltage through the D-S pole of the top tube and L1, then

Figure 9-3: The waveform of the top and down tube drive signal Flows through the load, and flows to the ground finally, when the current flows through the inductance, produces the positive on the left and the negative on the right induced voltage on the inductance. Figure 9-3: the waveform of the top and down tube drive signal. (3) The period of time T1~~T2, at this time, closes the top tube. The current flowed through the inductance disappeared suddenly, because of the inductive effect of the inductance, both ends of the inductance will produce a reverse voltage, the direction of this voltage is the positive on the right and The negative on the left. The enlarged drawing of the top and down tube signal waveform is shown in figure 9-3, after UGATE becoming to be low, LGATE will be driven to be high after delaying time, and this period of time is also the dead time. (4) The period of time T2, at this time, the top tube drive is low level, and the down tube drive is high level. So the top tube is cut off, the down tube is conducted, the induced voltage with the positive on the right and the negative on the left inducted on the inductance through the right end of L1 to the load, flows through the S-D pole of the down tube, then flows to the negative terminal of the voltage, that is the left end of L1. The real object of the single phase PWM circuit is shown in figure 9-4,is usually used for the memory power supply, the bridge power supply, the bus power supply, the graphics card power supply and others.

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Figure 9-4: The real object of the single-phase PWM circuit

The real object of the multiphase PWM circuit is shown in figure 9-5, is usually used for the CPU core power supply.

Figure 9-5: The real object of the multiphase PWM circuit

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9.1.2 The meaning of common English abbreviation in PWM circuit SKIP, SKIPSEL: the work mode setting. TON, RT, FS: the frequency setting (set the frequency by the resistance connecting the ground or the power supply). BOOT, BST, BOOST: boot-strap pin, the power source of the G pole of the top tube. UGATE, DH, HDRV, DRVH: the top tube drive. LGATE, DL, LDRV, DRVL: the down tube drive. FB: the feedback-adjusting pin. COMP: feedback compensation, correct the error of the feedback circuit. OUT, VOUT, VO: output voltage detection input pin. PHASE, SW, LX: the phase pin, connects the S pole of the top tube/the D pole of the down tube/the inductance, forms the loop with BOOT, and some can be the current detection. CSP/CSN: the current detection pin. ILIM, TRIP, CS: the over current protection threshold value sorting, the limited current setting. * Notes: "tube" is meaning the MOSFET.

9.1.3 The boot-strap circuit In the PWM power, the top tube is usually N channel, the output voltage is from the common point. Because the power chip is limited to the driving ability of the top tube, and almost all of the chips are used the boot-strap circuit to improve the driving ability and the name of boot-strap pin are usually BOOT, BST, BOOST. PWM circuit using the method of boot-strap is shown in figure 9 -6 . As the figure 9-6 an example, explains the principle of boot-strap: B+ of 19V supplies power to the high-end tube PQ5, at this time, the G pole is no power, so the S pole outputs OV. At the same time, B+ of 19V is input to http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide PU3,the internal produces the linear voltage VL with 5V,through the internal diode supplies power to BOOT1, if skips the pressure drop, it's still 5V,added to 1 pin of PC33,to charge it, the capacitor stored 5V voltage. BOOT1 of 5V supplies the power to UGATE1, sends the high level about 5V, is sent to the G pole of PQ5, at this time, the G pole of the moment PQ5 is 5V, the S pole is 0V, the channel of PQ5 can be conducted completely, 19V flows through PQ5 and PL4 to charge PC35, the voltage output by PQ5 is gradually increased.

Figure 9-6: PWM circuit using the boot-strap method

When the voltage output by PQ5 is gradually increased, if this voltage is 2V, and 2V is added to 2 pin of the capacitance PC33 at the same time, because of the feature of the capacitance. it just stores the power with 5V,at this time, adds 2V,so,the left of the capacitance (that is BOOT1) will become to be 7V,and 7V continues to supply power to UGATE1, the G pole of PQ5 will also become to be 7V,keeps PQ5 VG>Vs, and is higher than 4.5V,PQ5 keeps conducted completely, the voltage of the S pole will also follow to rise, adds again to PC33. So, we can measured the square wave with the highest 19V and the lowest 0V on the left of PL4.Because the power of the capacitance PC33 always not be discharged, the voltage of BOOT1 will forever be higher than the left of PL4 to

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Laptop Chip Level Repair Guide 5V, that is 19+5=24V, the waveform of UGATE1 is also that the lowest is OV, and the highest is 24V.

9.1.4 Output voltage regulation circuit As shown in figure 9-7, through two sampling resistance connected by FB feedback pin dividing into voltage, compared with the internal reference voltage, so as to realize the output voltage regulation. The computational formula is: VOUT= FB x (1+R1/R2) If FB=0.8V, R1 is equal to R2, then Vout=1.6V

Figure 9-7

9.1.5 The voltage detection circuit PWM power needs to detect at any time that if the output voltage meets the required standard, avoids that the output voltage is too high or the output voltage is too low. In the figure 9-8, OUT pin is used for the output voltage detection.

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Figure 9-8: The figure of the voltage and current detection circuit

When the output voltage is over voltage, the chip internal uses OVP (over voltage protection); when the output voltage is too low, the chip internal uses UVP (low-voltage protection). The 3.3V of standby voltage over-voltage protection waveform is shown in figure 9-9.

Figure 9-9: The 3.3V of standby voltage over-voltage protection waveform

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9.1.6 The current detection circuit

Figure 9-10: The figure of the current detection

PWM power needs to detect the output current at any time .When its overcurrent, the chip internal starts using OCP (over-current protection) mechanism. There are two methods of detecting current: As shown in figure 9-8, PWM chip can detect the current through CSH, CSL pin: series a milliohm resistance, CSH detects the resistance input end voltage; CSL detects the resistance output end voltage. To calculate the differential pressure at both ends of the resistance, divides the resistance value to get the current, the computational formula is: I= (CSH-CSL)/R The figure of the current detection as shown in figure 9-10, no CSH and CSL chip, it can detect through the down tube between PHASE pin and PGND pin: after the down tube conducting, the resistance value is dozens of milliohm, detects conducted voltage drop of the down tube to get the current. By this method to detect the current, it's not very precise. During calculating, we should use the maximum value of the worst case in the data manual of the field effect transistor, and considers that the resistance value after the field effect transistor conducting will be increased with the rising of the temperature, so it's also need the certain allowance. The benefit of this way is reliable, and it is the nondestructive over-current detection. When the output voltage is over or the output current flows through, the chip will use the internal output discharging mode. In this mode, the top tube G pole driver signal is turned off to be 0V low level, the G pole driver signal of the down tube is driven to 5V high level, at this time, the top tube is cut off, the down tube continues to be conducted, the charge stored on the output filter capacitance is quickly discharged to the ground through the down tube, the output voltage is closed.

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Laptop Chip Level Repair Guide Special reminder: in the PWM circuit, is strictly prohibited to remove the chip then power up. The G pole of the top tube is suspended, which will cause that VIN is added to the rear stage directly, and burns the components.

9.1.7 The working mode In the laptop, most of PWM power 1C can work in the different two modes, PWM mode and SKIP (pulse separation mode), the purpose is to adapt to different sleep state. and outputs the different current (output voltage constant).There is SKIP# in the chip, is used to realize the mode switch, when SKIP# is low, the chip works in the pulse separation mode(SKIP mode),at this time, the output current is small, such as 3V standby voltage, it just needs to work in the SKIP mode when in the standby mode. But after powering on, the output current of 3V standby voltage must be increased, because some of the system voltage at this time is from the 3V standby voltage conversion, so that the output current must be increased, SKIP#(usually controlled by SLP_S3# sent by ICH) of the chip is high. The chip works in PWM mode, the output voltage is constant, but the output current is greatly increased. 1. PWM, PWM mode In PWM mode, the voltage load capacity is strong, the output current is large. The waveform in PWM mode is shown in figure 9-11,the frequency is 299.4kHz. 2. SKIP# mode (pulse separation mode) Within the unit time, the less of the PWM waveform, it will smaller the output current. The waveform in SK1P# mode is shown in figure 9-12; the frequency is just 34.63 kHz.

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Figure 9-11: The waveform in PWM mode

Figure 9-12: The waveform in SKIP mode

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9.2: Analysis of The Standby Power Chip

Figure 9-13: The pin name of MAX8734A (the top view)

9.2.1 Analysis of MAX8734A MAX8734A (is in common use with MAX 1999) is the standby power chip with high efficiency and four of the output produced by MAXIM company to use for the laptop. The main features: not need the current detection resistance; 1.5% output voltage accuracy; supplies the linear output with 3.3V and 5V; the maximum current with 100mA; can output two path of PWM power supply: 3.3V and 5V; the operating voltage range of 4.5~24V; the choice of the pulse mode and PWM mode; over-voltage and under- voltage protection.

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Laptop Chip Level Repair Guide 1. MAX8734A pins description

Table 9-1: The definition of the pin function of MAX8734A

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(Pins) ----- (Description) of MAX8734A (1 )

the vacant pin

(2) the power good, open drain output. If the output of any path is forbidden or the output is 10% lower than the standard value, PGOOD is pulled low. (3) 3.3V SMPS enable input.ON3 connects to REF, 3.3VSMPS will start after 5V SMPS being stable.

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Laptop Chip Level Repair Guide (4) 5V SMPS enable input.ON5 connects to REF,5V SMPS will start after 3.3V SMPS being stable. (5 )

3.3V SMPS current limit adjustment

(6 ) Shutdown control input. The main switch of the chip is the opening of the linear voltage. (7) 3.3V SMPS feedback input.FB3 connects GND to choose the fixed output 3.3V, FB3 connects to the resistance divider between OUT3 and GND, it can achieve the adjustable output of 2~5.5V. (8) 2V reference voltage output. It can only provide 100 current, and it will lead to lower output accuracy with REF load. (9) 5V SMPS feedback input.FB5 connects GND to choose the fixed output 5V, and connects FB5 to the resistance divider between OUTS and GND, it can achieve the adjustable output of 2~5.5V. (10) Over-voltage and under-voltage protection enable pin. When PRO# connects VCC, forbids the protection.PRO# connects the ground, then opens the protection function (11)

5V SMPS limit current regulation.

(12) Low noise mode control. When SKIP# connects the ground, works in the idle mode, when SKIP# connects VCC, works in the PWM mode. When SKIP# connects REF or is vacant, works in the ultrasonic mode. (13) Frequency selective input. When TON connects VCC, chooses 200/300 kHz working mode, when it connects the ground, chooses 400/500kHz working mode (respectively corresponding the switching frequency of 5V, 3.3V SMPS) (14)

The bootstrap capacitor connection terminal of 5V SMPS

(15) The inductance connected 5V SMPS. It¡ s the internal low-end power ® supply rail of DH5.LX5 is the current detection input of 5V SMPS (16)

The high-end G pole driver of 5V SMPS

(17) The analog supply voltage input of PWM core. It needs a 1 capacitor bypass

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Laptop Chip Level Repair Guide (18) 5V linear regulation output. It can provide 100 current. If the voltage of OUTS end is higher than the LDO5 switch threshold, then LDO5 regulator is turned-off, and LDO5 connects to OUT5 through a small resistance. (19)

The low-end tube G pole driver of 5V SMPS

(20)

The main power input

(21) 5V SMPS output voltage detection input. When the voltage of this pin is higher than 4.56V,it will replace the internal LDO5 output. (22) 3.3V SMPS output voltage detection input. When the voltage of this pin is higher than 2.91 V,it will replace the internal LDO3 output. (23)

Ground connection

(24)

The low-end G pole driver of 3.3V SMPS

(25) 3.3V linear regulator output. It can provide 100mA current lf the voltage of OUT3 terminal is higher than the LDO3 switch threshold, then LDO3 regulator is turned-off and LDO3 connects to OUT3 through a small resistance. (26)

The high-end G pole driver of 3.3V SMPS

(27) The inductance connected 3.3V SMPS. It's the current detection input of 3.3V SMPS (28)

The bootstrap capacitor connection terminal of 3.3V SMPS

The electrical features of SHDN# threshold value in the MAX8734A data manual are described as shown in figure 9-14.

Figure 9-14: The screenshot of the description of the electrical features of SHDN# threshold value of MAX8734A.

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Laptop Chip Level Repair Guide HDN# input threshold value level: the lowest value of the rising edge is 1.2V, usually is 1.6V, the maximum is 2.0V. SHDN# input threshold value level: the lowest value of the falling edge is 0.96V, usually is 1.00V, the maximum is 1.04V. In the MAX8734A data manual, the electrical features of ON3 and ON5 threshold value is described as shown in figure 9-15.

Figure 9-15 Explanation: ON3 and ON5 input voltage: when its less than0.8V, .the switching power supply is turned off. ON3 and ON5 input voltage: when it is 1.7~2.3V, delays start. ON3 and ON5 input voltage: when it's higher than 2.4V, opens directly. In the MAX8734A data manual, the electrical features of over-voltage protection threshold value described as shown in figure 9-16. When the output voltage is higher than the set voltage to a certain value, then it will start the over-voltage protection: the minimum value is 8%.usually is 11%, the maximum value is 14%. For example, sets to be 3.3V, achieves 3.3+3.3*11% = 3.663V, then the chip to protect.

Figure 9-16: The screenshot of the description of the electrical features of the over-voltage protection in the MAX8734A data manual.

In the MAX8734A data manual, the electrical features of the output undervoltage protection threshold value described as shown in figure 9-17.If the output voltage can only reach 70%(the common value) of the set voltage, then it will start the under-voltage protection.

Figure 9-17: The screenshot of the description of the electrical features of the under-voltage protection threshold value in the MAX8734A data manual

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Laptop Chip Level Repair Guide The switching circuit of OUT, LDO5 and OUT3, LDO3 is shown in figure 9-18: when OUT5/3 is higher than 4.56/2.91 V, it will replace the internal linear voltage output. 2. Output voltage regulation FB3/FB5 connects to the ground; you can choose a fixed output 3.3V and SV. If FB3/FB5 connects to the resistance divider between OUT3/OUT5 and the ground, then it can adjust the output in the range of 2~5.5V.The specific calculation formula is VOUT=VFB x (R1+R2)/R2, is shown in figure 9-19

Figure 9-18: The switching graph of OUTx and LDOx of MAX8734A

Figure 9-19: The output voltage regulation diagram of MAX8734A

The typical application diagram is shown in figure 9-20.

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Laptop Chip Level Repair Guide 3. General workflow First,V+ inputs, V+ through the resistance divider input or the high level sent by the external acts the open for SHDN#,MAX8734A will produce LDO5,the internal structure is shown in figure 9-21.

Figure 9-20: The typical application diagram of MAX8734A

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Figure 9-21: The internal block diagram of MAX8734A

LDO5 supplies power to VCC, is shown in figure 9-22. After VCC input being sent MAX8734A, the chips produce 2V reference voltage REF, is shown in figure 9-23.

Figure 9-22: The relationship between LDO5 of MAX8734A with VCC

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Figure 9-23: The production of the reference voltage of MAX8734A After REF being stable, outputs the linear voltage LDO3 of 3.3V.The timing sequence waveform of V+, LDO5, LDO3 is shown in figure 9-24.

Figure 9-24: The timing sequence of the linear voltage of MAX8734A ON5 connects VCC,ON3 connects REF, is shown in figure 9-25,so,the chip produces PWM power supply of 5V first, after being stable, then produces PWM power supply of 3.3V. FB3 and FB5 are connected the ground, is shown in figure 9-26,chooses the fixed output 3.3V and 5V.After all outputs being stable, the chip open drain outputs PGOOD finally, is pulled up by the VCC through look.

Figure 9-25: The origin of the opening signal http://www.XiuFix.com/laptop-chip-level-repair/

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Figure 9-26: FB setting

4. Control timing relationship (Power-up Sequencing) The original of MAX8734A control timing relationship in English is shown in table 9-2.

Table 9-2: MAX8734A Power-Up Sequencing Explanation: If SHDN# is low level, then, no matter what ON3 and ON5 is, the linear 5V, linear 3V, 5V switching power supply and 3V switching power supply will be closed, there is no output. If SHDN# is higher than 2.4V, and ON3 and ON5 are low level, the linear 5V and linear 3V will be opened (the linear 3V will start after REF being stable), 5V and 3V switching power supply are closed. If SHDN# is higher than 2.4V, ON3 and ON5 are high level, LDO5, LDO3, 5V switching power supply and 3V switching power supply will be opened, there is a voltage output. If SHDN# is higher than 2.4V, ON3 is low level, ON5 is high level, the linear 5V, the linear 3V and 5V switching power supply are opened, and 3V switching power supply is closed.

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Laptop Chip Level Repair Guide If SHDN# is higher than 2.4V,ON3 is high level,ON5 connects REF pin, the linear 5V,the linear 3V and 3V switching power supply are opened,5V switching power supply will start after 3V being stable. If SHDN# is higher than 2.4V,ON3 connects REF pin,ON5 is high level, the linear 5V,the linear 3V and 5V switching power supply are opened,3V switching power supply will start after 5V being stable. If SHDN# is higher than 2.4V, ON3 is high level, ON5 is low level, the linear 5V,the linear 3V and 3V switching power supply are opened,5V switching power supply is closed.

9.2.2 Analysis of TPS51125 TPS51125 is an economical and efficiency dual channel synchronous buck controller produced by TI in the US to use for the standby voltage of the laptop. The voltage is 5.5~28V,the output voltage is 2~5.5V adjustable, with 5V and 3.3V two path of 100mA linear voltage output and 2V reference voltage output with internal error l%, integrates the over-voltage, under-voltage and overcurrent protection, with the function of over- heat protection. It provides VCLK output of 270 kHz to use to drive the external bootstrap circuit, in the case of no reduction in the working efficiency of the main converter to generate the gate drive voltage for the rear power conversion switch. TPSS 1125 supports efficient, fast transient response and provides a combination of enable signal. Out-of-Audio™ mode light load operation realizes low noise, and its efficiency is higher than the traditional mandatory PWM. The introduction of the pin definition and the common pin of TPS51125 is shown in figure 9-27.

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Figure 9-27: The name of the pin of TPS51125 (the top view)

1. The definition of TPS51125 Table 9-3: The pins definition of TPS51125

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(Pins) ---------- (Descriptions) of TPS51125 (1) Channel 1 open and current limit set pin. The direct grounding closes the output, sets the threshold value of the over-current through the resistance grounding (2 )

the feedback of channel 1

(3 )

2V reference voltage output

(4 )

the frequency setting

(5 )

the feedback of channel 2

(6) channel 2 open and current limit pin. The direct grounding closed the output, sets the threshold value of the over-current through the resistance grounding (7) channel 2 output voltage detection. The function: (1) voltage detection; (2) is used to replace the linear voltage (8 )

the linear voltage output of 3.3V

(9 )

the starting pin of channel 2, boot-strap terminal

(10) the top tube drive of channel 2 (11) the phase pin of channel 2.Function: (1) the top tube conducts the loop; (2) the current detection (12) the down tube drive of channel 2.

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Laptop Chip Level Repair Guide (13) the main starting signal. Function: (1) open the linear when its vacant, ready to open VCLK and PWM; (2)only open the linear when through the resistance grounding, close VCLK and ready to open PWM; (3)direct grounding, close the whole chip. (14)

PWM mode and pulse mode select pin

(15)

ground connection

(16) the main power supply input, is the origin of the linear voltage power supply (17)

the linear voltage output of 5V

(18) 15V|

the frequency output of 270 kHz, is used for the boot-strap circuit of

(19)

the down tube drive of channel 1

(20) the phase pin of channel 1 .Function; (1) the top tube conducts the loop; (2) the current detection (21)

the top tube drive of channel 1

(22)

the starting pin of channel 1, the boot-strap terminal

(23)

the power good output, open drain output

(24) the voltage detection of channel 1 .Function: (1)voltage detection;(2)is used to replace the linear voltage

In the TPS51125 data manual, the threshold value of EN0 described as shown in figure 9- 28:when the voltage of EN0 is less than 0.4V,the chip will be closed; when the voltage of ENO is higher than 0.8V,opens the linear and closes VCLK; when the voltage of EN0 is higher than 2.4V,opens the linear and VCLK.

Figure 9-28: The screenshot of the description of electrical features of EN0 threshold value in the TPS51125 data manual

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Laptop Chip Level Repair Guide In the TPS51125 data manual, the threshold value of ENTRIP# described as shown in figure 9-29: the minimum value of the turn-off level threshold value of ENTRIP1 and ENTRIP2 is 350mV, the general value is 400mV, the maximum value is 450mV; the minimum value of the hysteresis is 10mV, which means that the minimum value of the open level is 360mV, the general value is 30mV, that is 430mV, the maximum value is 60mVthat is 510mV.

Figure 9-29: The screenshot of the description of the electrical features of EN pin threshold value of TPS51125

Figure 9-30: The equivalent circuit of the ENTRIPx in the chip TPS51125 produces REF first, then produces VREG*, is shown in figure 931,after EN being produced, VIN converts to be VREF first, then VREF is input to the inverted input terminal of the comparator of VREG5 and VREG3,controls the production of VREG5 and VREG3. In the TPS51125 data manual, the electrical features of VCLK described as shown in figure 9-32: VCLK is the waveform of 270 kHz, is 4.92V in the high level, and is 0.06V in the low level (the typical value).

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Figure 9-31: The internal schematic diagram of the production of VREF and VREG* in the TPS51125 data manual

Figure 9-32: The screenshot of the description of the electrical features of VCLK in the TPS51125

The schematic diagram of the boot-strap of TPS51125 VCLK is shown in figure 9- 33.First,VCLK is low level,VO1 charges Cl through DO,5V.When VCLK comes,4.92V add 5V(ignore the diode voltage drop) is IOV. The voltage of 10V flows through Dl and C3 voltage rectifier filter, then charges C2 through D2.Add again is 15V,outputs 15V(the measured voltage is between 12~ 14V) through D4 and C3 rectifier filter.

Figure 9-33: The boot-strap circuit of 15V

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Laptop Chip Level Repair Guide 2. The open signal control relationship The original table in English of the open signal control relationship of TPS51125 is shown in figure 9-4. Table 9-4: The signal control relationship of TPS51125 (Enabling State)

Explanation: When EN0 is ground connection, no matter what the state of ENTRIP1 and ENTR1P2 is, VREF, VREG5, VREG3, channel 1, channel 2 and VCLK are closed. When EN0 is ground connection through the resistance, and ENTRIP1 and ENTRIP1 are low level, VREF, VREG5, VREG3 are opened, channel 1, channel 2, VCLK are closed. When EN0 is ground connection through the resistance, ENTRIPl is high, ENTRIP2 is low, channel 2 and VCLK are closed, others are opened. When EN0 is ground connection through the resistance, ENTRIPl is low, ENTRIP2 is high, channel 1 and VCLK are closed, others are opened. When EN0 is ground connection through the resistance, ENTRIPl and ENTRIP2 are high, VCLK is closed, and others are opened. When EN0 is vacant, ENTRIPl and ENTRIP2 are low, two channels and VCLK are closed, others are opened. When EN0 is vacant, ENTRAP1 is high, ENTRIP2 is low, only channel 2 is closed, and others are opened. When EN0 is vacant, ENTRIPl is low, ENTRIP2 is high, channel 1 and VCLK are closed, others are opened. When EN0 is vacant, ENTRIP 1 and ENTRIP2 are high, all of them are opened.

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9.2.3 Analysis of RT8206A/RT8206B Analysis of RT8206A/RT8206B RT8206A/RT8206B is the standby power supply chip produced by RichTek, the internal of the chip includes a linear voltage regulator module, which provides the output of 5V 70mA.It can provide a fixed output the adjustable voltage of 3.3V and 5V or 2V to 5.5V.The range of the main power supply input:6~25V.

1. The introduction of the pin definition and the common pin The top view of the pin name of RT8206A/RT8206B is shown in figure 9-34.

Figure 9-34: The pin name of RT8206A/B (the top view)

The definition pin function of RT8206A/B is shown in table 9-5.

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Laptop Chip Level Repair Guide Table 9-5: The pin definition of RT8206A/B (Functional Pin Description)

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Laptop Chip Level Repair Guide (Pins)------------ (Description) of RT8206A/B 1

2.0V reference voltage output terminal

2 the switching frequency setting terminal, connects VCC (200kHz/250kHz), connects REF(300kHz/375kHz),connects GND (400kHz/500kHz) 3 the switching power supply input, connects the capacitor of 1 u F directly with the ground 4 LDO module open signal input, in the high level, LDO/REF is opened, in the low level, LDO/REF is closed 5

the vacant pin

6

the input of the chip main power supply

7 5V 70mA LDO voltage output, after the system power supply 5V being produced, LDO module is closed, and through internal switch of 1.5 converts to 5V power supply produced by external SMPS 8

the vacant pin

9 the voltage output by connecting 5V SMPS.is used to convert LDO voltage output 10

SMPS 1 output voltage detection

11 SMPS1 feedback input. When FB1 connects to VCC or the ground wire, SMPS 1 is the fixed output 5V voltage mode; when FBI connects to the resistance partial pressure between VOUTl and the ground, you can set the output voltage to be 2~5.5V 12

SMPS1 output current threshold setting

13 SMPS1 power good signal output, when SMPS1 output voltage is less than the standard 7.5%,this signal becomes to be the low level 14 SMPS1 enable signal input. If EN1 is high level, SMPSl is opened, if its low level, SMPS 1 is closed. If connects to REF,SMPS1 is opened after SMPS2 working 15

high-end OSFET driver signal output terminal

16

the connecting end of SMPS1 output inductance

17

the connecting end of SMPS 1 boost capacitor

18

the output terminal of low-end MOSFET driver signal http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide 19

the input terminal of 5V power supply

20

the connecting end of 14V boost feedback; (RT8206B) is vacant pin

21

ground terminal

22

ground terminal

23

the output terminal of low-end MOSFET driver signal

24

the connecting end of SMPS2 boost capacitor

25

the connection of SMPS2 output inductance

26

the output terminal of high-end MOSFET driver signal

27

the input terminal of SMPS2 enable signal

28

the output terminal of SMPS2 power good signal

29 SMPS working mode setting end. Connect the ground: custom mode. Connect REF: ultrasonic mode. Connect VCC: PWM mode 30

SMPS2 output voltage detection

31

SMPS2 output current threshold setting

32 SMPS2 feedback input. When connects FB2 to VCC or the ground wire,SMPS2 is the fixed output 3.3V voltage mode .connects FB2 to the resistance partial pressure between VOUT2 and the ground, you can set the output voltage to be 2~5.5V

In the RT8206 data manual, the threshold value of ENx and ENLDO described as shown in figure 9-35.

Figure 9-35: The screenshot of the description of the electrical features of ENx and ENLDO threshold value of RT8206

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Laptop Chip Level Repair Guide The explanation is below: When ENx is less than 0.8V,closes SMPS; between 1.8~2.3V,delay starts; when its higher than 2.5V,opens SMPS. ENLDO, the minimum value of the rising edge(from low level to high level) is 1.2V,the typical value is 1.6V,the maximum value is 2.0V. ENLDO, the minimum value of the falling edge(from high level to low level) is 0.49V,the typical value is IV. the maximum value is 1.06V.

2. Control timing sequence The original in English of control timing sequence of RT8206A/RT8206B is shown in table 9-6. Table 9-6: The control timing sequence of RT8206A_B

Explanation: When ENLDO is low, no matter what the state of EN1 and EN2 is, LDO and 3V, 5V switching power supply is closed. When ENLDO is high lever more than 2V.EN1 and EN2 are low level, LDO is output after REF being stable, 5V, 3V switching power supply are closed.

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Laptop Chip Level Repair Guide When ENLDO is higher level more than 2V, EN1 is low, EN2 connects REF pin, LDO is output after REF being stable, 5V, 3V switching power supply are closed. When ENLDO is high level more than 2V, EN1 is low, EN2 is high XDO is output after REF being stable, 5V switching power supply is closed, 3V switching power supply is opened. When ENLDO is high level more than 2V, EN1 connects REF pin, EN2 is low, LDO is output after REF being stable, 5V, 3V switching power supply are closed. When ENLDO is high level more than 2V, EN1 connects REF pin, EN2 also connects REF pin, LDO is output after REF being stable, 5V, 3V switching power supply are closed. When ENLDO is high level more than 2V,EN1 connects REF pin,EN2 is high, LDO is output after REF being stable,3V is opened directly,5V is output after 3V being stable. When ENLDO is high level more than 2V, EN1 is high, EN2 is low, LDO is output after REF being stable, 5V is opened, 3V is closed. When ENLDO is high level more than 2V, EN1 is high, EN2 connects REF pin, LDO is output after REF being stable.SV is opened directly, 3V is output after 5V being stable. When ENLDO is high level more than 2V, EN1 is high, EN2 is also high, LDO is output after REF being stable, 5V, 3V are opened directly.

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9.3: Analysis of The Memory Power Supply Chip 9.3.1 Analysis of ISL88550A Analysis of ISL88550A Used for the power supply chip ISL88550A of the memory power supply, it can output one path of PWM (the memory main power supply) and two path of LDO (the memory REF power supply and VTT power supply).

1. The introduction of the pin definition and common pin The name of the pin of ISL88550A is shown in figure 9-36.

Figure 9-36: The name of the pins of ISL88550A (the top view)

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Laptop Chip Level Repair Guide Table 9-7: The table of the pins definition of ISL88550A

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(Pins) --------- (Description) of ISL88550A 1 frequency selection: TON connects AVDD (200 kHz), when it¡ s in vacant, ® connects REF (450 kHz), connects the ground (600 kHz) 2 over-voltage/under-voltage protection control input. Connects AVDD (open the over- voltage protection and the discharging mode, open the under-voltage protection).When It's in vacant (open the over-voltage protection and the discharging mode, close the under-voltage protection), connects REF (close the over-voltage protection and the discharging mode, open the over-voltage protection), connects the ground (close the over-voltage protection and the discharging mode, close the under-voltage protection) 3

2V reference voltage output

4

the limiting current setting

5

PWM power good

6

LDO power good

7

when STBY# is low, VTT will be closed, is the high resistance state

8

soft start

9

VTT voltage detection input

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Laptop Chip Level Repair Guide 10

the terminal reference voltage, the value is the same with VTT

11

ground connection

12 the terminal voltage output, connects to VTTS to keep it to be half of VREFIN 13 the input voltage of VTT voltage regulator, in the application of the memory power supply, will usually connect it to PWM output terminal 14 the external reference voltage input, is used to adjust VTT and VTTR, the voltage output by them is the half of REFIN 15 the feedback of PWM. When it connects AVDD, fix output 1.8V,when it connects the ground, fix output 2.5V.If its adjusted by the resistance partial pressure, it can output the voltage between 0.7~3.5V 16

the output voltage detection input of PWM

17

the main power supply input the range of 2~25V

18

the top tube driver of PWM

19 the phase pin of PWM. the function of the top tube drive loop and the current detection 20

the boot-strap terminal

21

the down tube driver of PWM

22 the power supply of the chip .the origin of the driving force of the down tube 23

ground connection

24

ground connection

25 the working mode setting. when it connects AVDD, low noise forced PWM mode, when connects the ground, jump pulse mode 26

the main power supply of LDO and PWM

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Laptop Chip Level Repair Guide 27 turn-off the control input A, the rising edge clear fault latch, connects the high level open chip 28 the test pin

The control relationship between SHDN# and STBY# of ISL8850A is shown in table 9-8.

Table 9-8: The open signal control relationship of ISL88550A

Explanation: When SHDNA# connects the ground, no matter what the state of STBY# is, PWM,VTTR are closed, VTT is also closed(discharge to 0V). When SHDNA# connects AVDD,STBY# connects the ground, PWM and VTTR are opened, VTT will be closed(the high resistance state). When SHDNA# and STBY connects AVDD,PWM,VTT,VTTR are opened.

2. The typical application The typical application of ISL88550A is shown in figure 9-37.

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Figure 9-37: The typical of ISL88550A

The specific working process: 1) 5V supplies power to 22V, 4.5 ~25V supplies power to 17 pin. 2) 3 pin produces 2V reference voltage. 3) The south bridge sends the high level of SLP_S5#SLP_S4#to 27-pin SHDNA# 4) PWM is opened, outputs VDDQ, 1.8V (FB connects AVDD, sets to be the fixed output 1.8V). 5) VDDQ is returned to OUT detection, the chip outputs POK 1; at same time, VDDQ supplies power to REFIN.

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Laptop Chip Level Repair Guide 6) Output VTTR, the voltage is the half of REFIN, that is 0.9V(as shown in figure 9- 39,after REFIN entering the chip, through two of 10kΩ resistance series divides into the voltage to be 0.9V,then outputs VTTR with 0.9V through voltage follower).At the same time, the chip outputs POK2. 7) The South Bridge sends the high level of SLP_S3# to STBY# pin. 8) Outputs a voltage from the external to 13 pin VTTI as the power supply of VTT regulator. 9) Outputs VTT, the voltage is the half of REFIN, 0.9V.

Figure 9-38: The screen shot of the internal relationship of REFIN and VTT, VTTR of ISL88550A

9.3.2 Analysis of RT8207 Another common memory power supply chip RT8207,is also responsible to output three paths of power supply: the memory main power supply, the memory REF voltage, the memory VTT voltage, the pin definition is shown in table 9-9.

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Laptop Chip Level Repair Guide Table 9-9: The pin definition of RT8207 (Functional Pin Description)

(Pins) ----------- (Descripton) of RT8207 1

the ground pin of the internal integrated VTT regulator

2

the voltage detection input pin of VTT output

3

the ground connection

4 output discharging mode setting pin. Connect to VDDDQ trace discharge; connect to the ground, the non-trace discharge; connect to VDD, not discharge

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Laptop Chip Level Repair Guide 5

VTTREF voltage output pin, is sent to the memory reference voltage

6 the diode emulation mode open pin. Connect to VDD to open the diode emulation mode; connect to the ground, is always working in the forced CCM mode 7

the vacant pin

8 the reference input pin of VTT and VTTREF. The output voltage of VTT and VTTREF is the half of VDDQ. If FB connects VDD or GND,VDDQ can be acted as the output voltage feedback input pin 9 VDDQ (PWM) output voltage-setting pin. Connects to GND, outputs 1.5V; connects to VDD, outputs 1.8V; it can set the adjustable output voltage between 0.75 ~ 3.3V through the resistance partial pressure 10

SLP_S3# sent by the South Bridge, is used to control the output of VTT

11 SLP_S5# sent by the South Bridge, is used to control the output of PWM and VTTREF 12

connects to VIN through a resistance. Sets the frequency

13 the open drain output pin of the power good, it means that PWM control output VDDQ voltage has normal 14

the power supply 15 the

power supply 16

connects to VDD through a resistance, sets the limited current

17

the vacant pin

18 the ground connection (the ground connection of the driver of the down tube) 19

the down tube drive

20 the phase pin; it can be used as the current detection pin: detects the current through the detection of the pressure drop of the down tube. 21

the top tube drive 22 the boot-strap pin

23

the power supply of the regulator of VTT 24 the output of VTT

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Laptop Chip Level Repair Guide The typical application of RT8207 is shown in figure 9-39.

Figure 9-39: The typical application of RT8207 The original in English of the control logical relationship between S3 and S5 of RT8207 is shown in table 9-9. Table 9-9: The control logic relationship of RT8207

Explanation: In the S0 state,S3 is high,S5 is high ------VDDQ,VTTREF,VTT are opened. In the S3 state,S3 is low,S5 is high ------VDDQ and VTTREF are opened, VTT is closed(the high resistance state). In the S4/S5 state, S3 and S5 are low ------VDDQ,VTTREF and VTT are closed(discharge to the ground). The working process of RT8207 is shown in figure 9-40.

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Figure 9-40: The working process of RT8207

9.4: Analysis of The Bridge/Bus Power Supply Chip The bridge power supply and the bus power supply chip is relatively simple, is usually used a single PWM or dual PWM controller.

9.4.1 Analysis of the single PWM controller RT8209 The common single PWM controller RT8209 can be used for the bridge power supply, bus power supply, the memory main power supply and other circuits. Note: RT series chip body usually do not have a real model, only the product code. For example, RT8209BGQW, the chip body is only the word "A0=", is shown in figure 9- 41.About the actual type recognition of this series chip, you need to download the packaging file of RT chip, at present the latest version of the new efferent is 2009,the name of this field is Richtek_Marking_Code_090424.PDF, you can download in their official website.

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Figure 9-41: The marking code of RT8209 series chip body

The definition of the RT8209 series chip is shown in figure 9-42.

Figure 9-42: The pin definition of RT8209 series chip (the top view)

The important pin: in addition to the PWM related pin, the power supply pin VDD,VDDP are usually connected to 5V,CS is the current limit set, TON is the frequency setting, the definition of the open pin EN/DEM is the start using/the diode emulation mode control input(the threshold value of EN/DEM in RT8209 data manual described as shown in figure 9-43).Connected to VDD, is the diode emulation mode, connected to the GND turn off chip, is CMM(the continuous current) mode when its vacant. Generally, It¡ s the vacant state during working, ® and is the ground state when it's turned off.

Figure 9-43: The screenshot of the description of the electrical features of EN/DEM pin threshold value in RT8209 data manual

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Laptop Chip Level Repair Guide The application of RT8209A/B/C is shown in figure 9-44,the description of the working process is below. 1) The power supply inputs 4.5 ~5.5V to VDD,VDDP pin, pulls up TON pin through the resistance to set the frequency, and pulls down CS pin through the resistance to set the limited current. 2) EN inputs the high level. Or the external circuit is disconnected, makes it to be vacant. 3) Starts PWM, outputs VOUT. 4) Detect the voltage from VOUT pin. 5) Open drain output PGOOD, is pulled up to be the high level by VDDP.

Figure 9-44: The application of RT8209A/B/C

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9.4.2 Analysis of The Dual PWM Controller TPS51124

Figure 9-45 The input voltage range of the dual PWM power supply chip TPS51124 which is commonly used in the bridge power supply and the bus power supply is from 3V to 28V, and the output voltage range is from 0.76V to 5.5V. The pin name of TPS51124 is shown in figure 9-45. The explanation of the important pin: 15 pin and 16 pin are the power supply,4 pin is the frequency selection, from 5 pin to 14 pin, are the first path of PWM power supply control, the 1 pin,2 pin and from 17 pin to 24 pin, are the second path of PWM power supply control, TRIP1/TRIP2 sets respectively the overcurrent limit of the two path of PWM.EN1/EN2 opens respectively the two

path of PWM. In the TPS51124 data manual, the power supply range of V5IN and V5FIIT described as shown in figure 9-46: the power supply range of V5IN and V5FIIT is from 4.5V to 5.5V.

Figure 9-46: The screenshot of description of the power supply range of V5IN and V5FIIT in the TPS51124 data manual

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Laptop Chip Level Repair Guide In the TPS51124 data manual, the threshold value of EN described as shown in figure 9- 47,the lowest threshold value of EN is 1 V ,is usually 1.3V,the maximum is 1.5V.

Figure 9-47: The screenshot of the description of the electrical feature of EN pin threshold value in the TPS51124 data manual

In the TPS51124 data manual, the frequency setting described as shown in figure 9-48.

Figure 9-48: The screenshot of the description of the frequency setting of TPS51124 When TONSEL is the ground connection, the first path of PWM works in 240 kHz, the second path of PWM works in 300 kHz. When TONSEL is vacant, the first path of PWM works in 300 kHz, the second path of PWM works in 360 kHz. When TONSEL connects V5FIIT, the first path of PWM works in 360 kHz, the second path of PWM works in 420 kHz.

In the TPS51124 data manual, the electrical features of FB pin described as shown in figure 9-49.1n the SKIP mode, the reference value of FB voltage regulation is 764mV,in the PWM mode, the reference value is 758mV.theo error precision is about 0.9% in 25oC,the error precision is about 1.3% in 0~85 C,and the error precision is about 1.6% in -40~85oC.

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Figure 9-49: The screenshot of the description of the electrical features of FB pin reference value in the TPS51124 data manual The typical application of TPS51124 is shown in figure 9-50.

Figure 9-50: The typical application of TPS51124

The description of the working process is below. 1) The power supply outputs 4.5~5.5V to 15 pin and 16 pin. 2) EN1 or EN2 input 3) Starts the first path of PWM or the second path of PWM. 4) Detect the voltage from VO1 or VO2. 5) Open drain output PGOOD1 or PGOOD2.

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9.5: Analysis of CPU Core Power Supply CPU generally requires a number of power supply, for example, CPU of 478 needs three kinds of power supply, the first generation 13/15/17 needs five kinds of power supply, but only VCC pin is the core power supply. In this section, we mainly explain the working principle of several common CPU core power supply chip.

9.5.1 The features of CPU VCORE power supply The multiphase output is that the output of multiple current sources are connected together, supplies power to CPU, which meets the demands of CPU large current. The real object of two-phase CPU power supply is shown in figure 9-51. Since the working voltage required by CPU at the different times is different, so it needs the control way to adapt automatically the requirements of the different CPU on the voltage, that is, the VID control of the output voltage. VID is the voltage identification technology, loaded with different CPU, it will produce the different voltage. VID can be divided into PVID (parallel VID) and SVID (serial VID).

Figure 9-51: The real object of two-phase CPU power supply

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Laptop Chip Level Repair Guide AMD early and before Intel 5 series chipset (HM55, etc), are all belong to PVID. The basic principle is that, sets 4~8 VID recognition pin on the CPU, and through the high and low level values preset in these recognition pin, to form a group of VID recognition signal, when its high level on VID recognition pin, then is the 1 state of the binary, and when it's the low level on the VID recognition pin, is the 0 state of the binary according to the combination of these 1 and 0,forms the group of the most basic machine language signal, and is transmitted to the power management chip in the CPU power supply circuit by CPU, according to the VID signal, the power management chip adjusts the duty cycle of the output pulse signal, which forces the DC voltage output by CPU power supply circuit to be consistent with the value represented by pre-set VID. Intel company developed the corresponding voltage regulation module design specifications for each CPU produced at different time, starts from the Prescott core microprocessor, the voltage regulation specification used VRD (Voltage Regulation Down) to name, in the laptop, uses the Voltage Mobile Positioning, the VID digit, the voltage regulation accuracy and the voltage regulation range in the various version of the power supply design specification are not the same. VID with this mode can "cheat" the CPU to come out by loading the dummy load. After loading the dummy load, connects one or more VID signal of VIDO~VID7 to the ground, at this time,VIDO~VID7 pin of the power IC gets the new voltage combination, according to this different combination, the power IC will control to send the corresponding voltage. That is to say, let CPU ' power supply chip mistakenly assume that the true CPU is loading. Starting from AM2+ CPU,CPU contains two pans of the voltage(AMD calls it to be Dual-Plane),one is the core voltage of CPU, one is the voltage of the North bridge integrated in CPU.A group of parallel VID control modules cannot asynchronous control these two voltages at the same time. Unless provides a group of parallel VID again to control the voltage of the North bridge in CPU, but this will be more complex. So AMD launched a new generation of voltage regulation module specification, using serial VID (SVID) mode to solve this problem. Serial VID is a type of bus protocol. From the hardware point of view, the required external interface is from the previous VIDO ~VID5 a total of 6 becoming into SVC (serial clock), SVD (serial data), it's very simple. However, because the serial VID is the bus-working mode, so it needs the cooperation of the software. But it also means that the operability adjusted latter will be stronger. Most of the previous AMD motherboard used PVI/SVI compatible of PWM controller in order to compatible with AM2/AM2+/AM3. Intel integrated the display core in Core i3/i5/i7 matched with 5 series platform, in order to control these two groups of power supply better, so provides two

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Laptop Chip Level Repair Guide groups of PVID interface to control respectively the core voltage of CPU and the display core voltage. These two groups of voltages are accord with the specification of Intel VRD 11.1.which is more complex. Starting from 6 series platform, Intel imports VRD12 specification, that is the serial VID mode, it's exactly the same with AMD SVI mode. There are three lines of SVID of Intel platform: SVD (serial VID data), (SVC serial VID clock), ALERT# (warning signal).

9.5.2 Analysis of MAX8770 MAX8770 is the control chip produced by MAXIM company, which is used for the CPU core power supply, in accordance with the IMVP-6 specification, the main features are as follow.

• • • • • • • •

Support two-phase CPU power supply. Support 7 bit VID, the output voltage is adjusted from 0V to 1.5000V. Support for dynamic phase adjustment and sleep. Integrated driver 1C. With power, ready (PWRGD) output and clock enable (CLKEN#) output. With the power monitoring and over-heat protection. Support 4~26V input voltage range. Output over-voltage protection. The pin name of MAX8770 is shown in figure 9-52, the real object of MAX8770 is shown in figure 9-53.

Figure 9-52: The pin name of MAX8770

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Figure 9-53: The real object of MAX8770 The definition of MAX8770 is shown in table 9-11. Table 9-11: The pin definition of MAX8770

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Laptop Chip Level Repair Guide (Pins) -------- (Description) of MAX8770 l. the output of the clock enables logic signal. When the output voltage detected from FB pin reaches the specified value, this pin outputs the effective logic low level. the power good signal of the open drain output. When the output voltage 2. detected from FB pin reaches the specified value, this pin open drain outputs the high level. this low voltage logic signal and DPRSLPVR commonly set the power 3. mode. If PSI# is low, then enter the PWM mode of N-l phase. When PSI# is high, then recovery the PWM mode of N phase. 4.

power monitor output

5. the open drain output pin of the internal comparator. When the voltage of THRM terminal is less than 1.5V (30%VCC),VRHOT# is pulled low. It's the high resistance at shutdown 6. the input terminal of the internal comparator. Connects one end of the thermistor (usually is NTC) to the ground, and another end to THRM, and through a resistance to VCC at the same time. By selecting the proper device, at the required temperature, the voltage of THRM end is reduced to less than 1.5V. the voltage slew rate(is the rate of voltage swing)control pin. TIME 7. connects a resistance to the ground, used to set the internal slew rate. The application of the voltage slew rate contains: the chip enter or exit the pulse interval mode, the chip enter VID MODE from BOOTMODE. For the soft start and shutdown process, the chip reduced automatically the slew rate to 1/8. 8. the switching frequency setting pin. The switching frequency is set by a resistance connecting to the power supply end and the TON end. 9.

the capacitor connection of the voltage integrator. 10. the current balance compensation

11. 2.0V reference voltage output, through a maximum of 1uF capacitor bypass to the ground. REF can provide 500 uA current to the external loads. 12. the feedback input. The external resistance capacitance element is used for detecting the output voltage. 13. the negative of the inductance input end of the feedback bypass. Connects to GND of the load end in general.

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Laptop Chip Level Repair Guide 14. the positive input end of the second phase output current detection. This pin must be connected to the positive end of the output current sense resistor. Connects the PIN pin to VCC, the second phase is closed. 15. The negative input end of the second phase output current detection. This pin must be connected to the negative end of the output current sense resistor. Under the case of the DC inductance of the output inductance being used as the output current detection resistance, this pin is connected to the output filter capacitor 16. the negative input end of the first phase output current detection. This pin must be connected to the negative end of the output current sense resistor. Under the case of the DC inductance of the output inductance being used as the output current detection resistance, this pin is connected to the output filter capacitor 17. the positive input end of the first phase output current detection. This pin must be connected to the positive end of the output current sense resistor. Connects this PIN pin to VCC, the first phase is closed 18.

simulated ground

19. the controller power supply pin. Connects the voltage end of 4.5~5.5V,through a minimum of 1uF bypass capacitor to connect to the ground 20. the boost resistor connection end of the second phase. It can set up the open signal for the top tube on the DH2 through this signal, when the down tube is turned on, the internal switch between VDD and BST2 charges the boost capacitor 21. the output end of the top tube drive signal of the second phase. The voltage values is changed between LX2 and BST2.Its low in shutdown. 22. the connection end of the output inductance of the second phase. It sets up the opening voltage on the DH2 for the top tube, acts as the input end of the zero crossing comparator of the second phase at the same time 23. The second phase power ground. It's the ground end ofDL2.It acts as the input end of the zero crossing comparator of the second phase at the same time. 24. The output end of the down tube drive signal of the second phase. The voltage value is changed between VDD and GND.DL2 is high in the shutdown. When the output voltage is abnormal, it has been forced to be high. It also is low in the small load mode, until detecting the inductance current 9PGND2LX2) zero crossing

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Laptop Chip Level Repair Guide 25. The power supply pin of the down tube drive of each phase. It acts as the charging source of the boost capacitor of each phase at the same time. This pin connects to the voltage source of 4.5~5.5V 26. the output end of the down tube drive signal of the first phase. The voltage values are changed between VDD and GND.DL1 is high in the shutdown. When the output voltage is abnormal, it has been forced to be high. It also is low in the small load mode, until detecting the inductance current (PGND1-LX1) zero crossing 27. the power ground of the first phase. Its the ground end of DLl. It acts as the input end of the zero crossing comparator of the first phase at the same time. 28. the connection end of the output inductance of the first phase. It sets up the opening voltage on DH1 for the top tube, acts as the input end of the zero crossing comparator of the first phase at the same time 29. the output end of the top tube drive signal of the first phase. The voltage values is changed between LX1 and BSTl. Its low in shutdown 30. the connection end of the boost resistance of the first phase. It can set up the open signal on DH1 for the top tube through this signal, when the down tube is opened, the internal switch between VDD and BST1 charges the boost capacitor 31~37. the input end of the low voltage VID digital signal.D0~D6 does not pull up in IC. The digital logic signal is directly connected to the relevant interface of CPU. The output voltage is controlled by VID. When VID is high, its turned off. When VID changes from high to other value, IC starts to start the timing sequence immediately 38. the voltage open signal. When it connects VCC, uses the default mode. When it connects GND, the chip enters into the close mode. During starting. the output voltage ramp slowly to the start voltage(the voltage slew rate is 1/8). When the voltage is closed, uses the same voltage slew rate to decline. The voltage of SHDN# pin can't be more than 13V,at this time, OVP and UVP protection of the chip internal are closed 39. The input end of the depth sleeps control. This signal and PSI# signal set commonly the power mode. 40. The deep sleep awaken signal. When this signal is low, it means that CPU is in a deep sleep state.

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Laptop Chip Level Repair Guide In the MAX8770 chip, the combination of DPRSLPVR and PSI# sets the power mode is shown in figure 9-54.

Figure 9-54: The screenshot of the original of combination DPRSLRVR and RSI# setting in the information of MAX8770 chip When DPRSLPVR is high, PSI# is low, the chip working mode is that the current is very small, the 1 phase jump pulse. When DPRSLPVR is high, PSI# is high, the chip works in the 3A small current mode, the 1 phase jump pulse. When DPRSLPVR is low, PSI# is low, the chip works in the PWM mode of 1 phase, the current is moderate. When DPRSLPVR is low, PSI# is high, the chip works in the PWM mode of the full phase, the maximum current output. The over-voltage protection: IC will detect if the output voltage meets the OVP standard or not in real. When the output voltage is higher than the value of the output voltage current VID corresponding 300mV(the typical value, is shown in figure 9-55),or is higher than 1.8V in the pulse interval mode, IC starts OVP protection. When OVP is low in the multiphase mode(DPRSLPVR is low and PSI# is high),IC pulls DL1 and DL2 high immediately, and pulls DH1 and DH2 low. It makes the down tube driving signal duty ratio is 100%,the down tube is emptying the output capacitor rapidly, the using output voltage is pulled low.

Figure 9-55: The screenshot of the description of the electrical features of the over-voltage threshold value in MAX8770 data manual

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Laptop Chip Level Repair Guide The over-voltage protection when the output voltage is less than the output voltage value 400mV(the typical value, is shown in figure 9-56) that VID corresponding to, IC starts SHUTDOWN timing sequence and sets the fault latch until the output voltage as low as OV. At this time, IC will be forced to pull high DL1 and DL2, and pull DH1 and DH2 low. Pull the SHDN# voltage clamp or VCC voltage down to less than 0.5V to clear the fault latch, and reactivate IC.

Figure 9-56: The screenshot of the description of the electrical features of the over-voltage protection threshold value in the MAX8770 data manual

The operating voltage range of VCC and VDD is shown in figure 9-57.

Figure 9-57: The screenshot of the description of the electrical features of VCC pin and VDD pin threshold value in the MAX8770 data manual As shown in figure 9-58,is the screenshot of the description of the electrical features of the key signal threshold value of MAX8770, SHDN and DPRSLPVR are the high level(the maximum value) when its higher than 2.3V,VIDO ~ VID6, PSI and DPRSTP are the high level(the minimum value) when its higher than 0.67V,are the low level (the maximum value) when its less than 0.33V

Figure 9-58: The screenshot of the description of the electrical features of the key signal threshold value in the Max8770 data manual

VID voltage corresponding of 1MVP-6 specification is shown in table 9-12.

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Laptop Chip Level Repair Guide For example: when D~D0 are the low level, the output voltage is 1.5000V;when D6 is the low level,D5~D0 are the high level, the output voltage is 0.7125V; when D6~D0 are the high level, the output voltage is 0V.

Table 9-12: The table-1 of VID corresponding of IMVP-6

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The application circuit of MAX8770 is shown in figure 9-59, several key working conditions are indicated in the figure:

Figure 9-59: The typical application figure of MAX8770

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Laptop Chip Level Repair Guide The timing sequence of MAX8770 starting and closing is shown in figure 9-60.

Figure 9-60: The MAX8770 starting and closing timing sequence 1) First the chip gets the power supply, the internal will pull up CLKEN# to be high level. 2) Then, the external sends the high level of the open signal SF1DN#. 3) VCORE soft starts to a certain voltage range first (the starting speed is 1/8 of the TIME 4) Pin resistance setting the slew rate, forced PWM mode. 5) The chip starts to decode VID signal sent by CPU. VCORE starts to the corresponding voltage set by VID. 6) After CPU soft start being normal, delays 60¦s to set CLKEN# low. Ì 7) After CPU power supply achieving the voltage set by VID, delays 5ms to set PWRGD high (MAX8770 has not the PHASEGD signal). 8) SHDN# changes to be low level. 9) VCORE, CLKEN# and PWRGD are turned into the invalid state, PWM restores the forced PWM mode, VID stops decoding. 10) When there is not VCC, CLKEN# also a change to be low level, the chip is outage.

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9.5.3 Analysis of ISL6260 ISL6260 is the CPU power supply chip confirmed the IMVP-6 specification; its main features are as follows:

• Precise multiphase kernel voltage regulator, supports for three-phase power supply, is programmable; • 7 bit of VID input recognition; • Support a variety of methods of the current detection; • Support PSI#; • Temperature monitoring; • Not integrated driver chip. The pin name of ISL6260 is shown in figure 9-61.

Figure 9-61: The pins name of ISL6260 (the top view)

The definition of the ISL6260 is shown in table 9-13.

Table 9-13: The pins definition of ISL6260

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(Pins) ----------- (Description) of ISL6260 l. low loading current input indication; is effective in the low level.ISL6260 can be used to close the PWM2 2. the high level input means that VCCP and VCC_MCH has been normal. this signal is the precondition of CLK_EN# and PGOOD sent by ISL6260

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Laptop Chip Level Repair Guide 3. through 147k bias resistance connect the ground. set the internal reference current 4.

over-heat indication output, is effective in the low level

5. connecting to the negative temperature coefficient thermistor; As the part of the VR_TT# circuit 6. through a single capacitor set the maximum voltage conversion rate (the slew rate. the range of the voltage increasing within 1 s, its the time that the square-wave voltage rising from the trough to the crest needs. the units are usually V/s, V/ms and V/ s) 7.

the over-current setting input pin

8.

through the resistance connect COMP to set the switch frequency 9.

the error compensation; which is connected to the output end of the internal error amplifier 10. the feedback pin, which is connected to the inverting input end of the internal error amplifier 11.

the output of the differential amplifier

12.

the voltage detection, the plus end

13.

the voltage detection, the negative end

14.

the output end of the internal attenuation amplifier

15.

the inverting input end of the internal attenuation amplifier

16.

the input end of the output voltage detection

17.

the total current detection

18.

the power supply input

19.

grounding

20.

5V power supply input

21 .

the third phase current detection

22 .

the second phase current detection

23 .

the first phase current detection

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Laptop Chip Level Repair Guide 25 .

the third phase PWM output

26.

the second phase PWM output 27. the first phase PWM output

28~34. 35.

the voltage recognition input pin the opening signal, is effective in the high level 36. the high level means that its in the deep sleep mode

37.

the low level means that its in the deep sleep mode

38. the opening signal of the clock chip; is effective in the low level. After PGD_IN and VCORE being normal, then it will output 39.

3.3V power supply of CLK_EN# circuit

40. the power good. Open drain output, it needs to be pulled up by the external The original screenshot of the description of the electrical features of several key signals threshold value of ISL6260 is shown in figure 9-62,the minimum of the rising edge threshold value of VR_ON,DPRSLPVR and PGD_IN is 2.3V,the maximum of the falling edge threshold value is IV; the minimum of the rising edge threshold value of VK)0- VID6,PSI# and DPRSTP# is 0.7V,the maximum of the falling edge threshold value is 0.3V.

Figure 9-62: The original screenshot of the description of the electrical features of VR_ON and other key signals threshold value of ISL6260

As shown in figure 9-63, when all VID of ISL6260 are OV, the maximum of the output voltage of VCC_CORE is 1.5V; when VID is 1100000, the output voltage of VCC_CORE is 0.3V, when all VID are 1V, VCC_CORE outputs 0V.

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Figure 9-63: The original screenshot of the decoding range of ISL6260VID PGD_IN mainly controls PGOOD logic circuit, is shown in figure 9-64, after CPU power supply being normal. The logic circuit of PGOOD needs to receive PGD_ FN, then it will send PGOOD, and sends to the logic circuit of CLK_EN# at the same time, the circuit of CLK_EN# must receive the power supply of 3V3, then it will send CLK_ EN#. So, no PGD_IN will not cause no CPU power supply it will only cause no output of PGOOD, no 3V3 will not cause PGOOD does not output it will only cause CLK_EN# does not output low level. The simplified application diagram and the key pin of ISL6260 are shown in figure 9-65.

Figure 9-64: The internal logic figure of PGOOD and CLK_EN# of ISL6260

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Figure 9-65: The simplified application diagram and the key pin of ISL6260 Note: (1.) = The chip main power supply (2.) = Temperature measurement and over-temperature instruction (3.) = VIDs (4.) = Sleep and Energy-saving control (5.) = Opening (start-up) (6.) = The voltage detection (7.) = The condition of PGOOD (8.) = CLK_EN# module power supply (9.) = First phase square waveform output http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide (10.) = The current detection (11.) = Second phase square waveform output (12.) = The current detection (13.) = Third phase square waveform output (14.) = The current detection (15.) = The total current detection (16.) = Driver chip power supply (17.) = CPU voltage output

Figure 9-66: The start timing sequence of ISL6260 The start timing sequence of ISL6260 is shown in figure 9-66. 1) The chip gets the power supply first, including VDD and VIN. 2) The high level of VR_ON sent from the external. 3) After delaying 100us, the chip starts soft start 4) VCORE to 1.2V, the starting speed is 2mV/us. 5) After VCORE starting to 1.2V and PGD_IN is high, the chip will send low level of CLK EN#. The chip decodes VID, drives VCORE to the voltage set by VID according to IMVP-6 standard, the starting speed is 10mV/us. 6) 7ms later, the chip outputs PGOOD signal.

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9.5.4 Analysis of commonly used chip ISL95831 by HM65 mainboard ISL95831 is the controller supported three phase CPU core power supply and 1 phase integrated graphics power supply, is mainly used for HM6x and above platform of Intel, in compliance with the IMVP-7/VR12 specification^ TQFN packaged, 48 pin. The main features are as follow:

• Support dual output; The first path of the voltage regulator can be configured as 3 phase, 2 phase and single phase; the second path of the voltage regulator supports a single phase output. • Two path of output shared SVID control. • Integrated three driver chips (the first path has two, the second path has one). • Support kinds of methods of current measurement. • Support the over-heat and over-current protection. The pin name of ISL9583 1 is shown in figure 9-67.

Figure 9-67: The pin description of ISL95831

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Laptop Chip Level Repair Guide The pin definition of ISL95831 is shown in table 9-14.

Table 9-14: The pin definition of ISL95831

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Laptop Chip Level Repair Guide (Pins) ----------- (Description) of ISL95831 1. this pin is connected to the COMPG by a resistance to set the switching frequency of the voltage regulator 2(8k Ω resistance is about 300kHz) 2. the analogue output. The output current and the current of the voltage regulator 2 forms a certain proportion 3. the open drain output pin of the power good. Indicates that the voltage regulator 2 has normal. The external needs to be pulled up by the resistance 4,5,6. the communication bus between CPU and the power management chip. Serial VID bus 7.

the enable pin of the controller. The high level is turned on. 8. the open drain output of the power good. Indicates that the

voltage regulator 1 has normal. The external needs to be pulled up by the resistance 9. the analog output. The output current and the current of the voltage regulator 1 forms a certain proportion 10.

over-heat indication signal

11. connects the ground through a negative temperature coefficient thermistor. used to monitor the temperature of the voltage regulator 1 12. connects this pin to COMP through a resistance to set the switching frequency of the voltage regulator l(8k resistance is about 300kHzi 13. the output end of the error amplifier of the first path of the voltage regulation 14.

the inverting input end of the error amplifier of the voltage regulator 1

15. when the voltage regulator 1 is configured as a 3 phase, is used to detect the current of the third phase. When its configured as 2 phase. The internal connects the switch of FB2 and FB, is used to adjust the precision of the compensation voltage regulator l. When its configured as 1 phase, the switch is invalid 16.

the second phase current detection of the voltage regulator 1 17. the first phase curer.: detection of the voltage regulator 1 18. the input end of the voltage detection of the voltage regulator 1

19 .

the loop end of the voltage detection of the voltage regulator 1

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Laptop Chip Level Repair Guide 20, 21. regulator 22.

the input pin of the droop current detection of the first path of

5v power supply 23.the power supply

24. the maximum output current of the voltage regulator 1 and VBOOT voltage of the two path of regulator are configured by the resistance connecting to the ground 25. the first phase boot-strap pin of the voltage regulator l. Through a resistance connects the PHASE pin of the first phase 26.the first phase of the top tube drive signal of the voltage regulator 1 27. the first phase of the top tube driver loop of the voltage regulator 1,connects the S pole of the top tube, the D pole of the down tube and the output inductance 28. the first phase of the down tube driver loop of the voltage regulator 1.connects to the S pole of the down tube 29 .

the first phase of the down tube drive signal of the voltage regulator 1

30. the third phase of the square wave output of the voltage regulator l. When it connects to 5V, disable the third phase 31. the power supply of the internal driver chip. connects to +5V,at least is 1 uF decoupling capacitors 32.

the second phase of the down tube drive signal of the voltage regulator 1

33. the second phase of the down tube driver loop of the voltage regulator l, connects to the S pole of the down tube 34. the second phase of the top tube driver loop of the voltage regulator 1,connects the S pole of the top tube. the D pole of the down tube and the output inductance 35.

the second phase of the top tube drive signal of the voltage regulator 1

36. the second phase of the boot-strap pin of the voltage regulator 1.Connects the PARSE pin of the second phase through a capacitor

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Laptop Chip Level Repair Guide 37.

the down tube drive signal of the voltage regulator 2

38. the top tube driver loop of the voltage regulator 2,connects the S pole of the top tube, the D pole of the down tube and the output inductance 39.

the top tube drive signal of the voltage regulator 2

40. the boot-strap pin of the voltage regulator 2.Connects the PHASEG pin through a capacitor 41. the maximum output current and the maximum limit temperature of the two regulators are configured by a resistance connecting the ground 42 . through a negative temperature coefficient thermistor, used to monitor the Temperature of the voltage regulator 2 43, 44. the input pin of the droop current detection of the second path of the regulator, when ISUMNG is connected to 5V. it will disable the second path of the voltage regulator 45.

the loop end of the voltage detection of the voltage regulator 2

46.

the input end of the voltage detection of the voltage regulator 2 47. the inverting input end of the error amplifier of the voltage

regulator 2 48. the output end of the error amplifier of the second path of the voltage regulation

In the ISL95831 data manual, the screenshot of the description of the input level threshold value of VR_ON is shown in figure 9-68,the maximum value of VR_ON in the low level is 0.3V,in the ISL95831HRTZ,the minimum value of VR_ON in the high level is 0.7V,in the ISL95831IRTZ,the minimum value of VR_ON in the high level is 0.75V.

Figure 9-68: The screenshot of the description of the electrical features of VR_ON threshold value in the ISL95831 data manual The simplified application circuit of ISL95831 is shown in figure 9-69. http://www.XiuFix.com/laptop-chip-level-repair/

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Figure 9-69: The simplified application figure of ISL95831

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Laptop Chip Level Repair Guide The configuration of PROG1 pin of ISL95831 is shown in table 9-15.

Table 9-15: The configuration of PROG1 in the ISL95831 data manual

Give some examples to explain: When PROG l pin connects the ground through 0Ω resistance, the voltage of Vboot is 0V. When CPU power supply outputs three-phase, two-phase and onephase. The maximum current are respectively 99A, 66A and 33A. When PROG1 connects the ground through 24.15kΩ, or infinitely resistance, the voltage of Vboot is 1.1V. When CPU power supply outputs three-phase, twophase and single-phase, the maximum are respectively 99A, 66A and 33A. The configuration of PROG2 of ISL95831 is shown in table 9-16.

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Laptop Chip Level Repair Guide Give some examples to explain: When PROG2 connects the ground throuogh 0Ω resistance, the value of the overtemperature protection of the chip is 120 C, the maximum of the output current of the second path of the voltage regulator is 33A. When PROG2 pin connects the ground through 24.15kΩ or infinitely resistance, the value of the over-temperature protection of the chip is 95oC, the maximum value of the output current of the second path of the voltage regulator is 33A. The waveform of SVID is shown in figure 9-70.the channel 1 is SCK, the channel 2 is SVD. The configuration of PROG2 of ISL95831 is shown in table 9-16.

Give some examples to explain: When PROG2 connects the ground throuogh 0Ω resistance, the value of the overtemperature protection of the chip is 120 C, the maximum of the output current of the second path of the voltage regulator is 33A. When PROG2 pin connects the ground through 24.15kΩ or infinitely resistance, the value of the over-temperature protection of the chip is 95oC,the maximum value of the output current of the second path of the voltage regulator is 33A. The waveform of SVID is shown in figure 9-70.the channel 1 is SCK, the channel 2 is SVD.

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Laptop Chip Level Repair Guide Table 9-16: The configuration of PROG pin in the ISL95831 data manual

The starting timing sequence of ISL95831 is shown in figure 9-71.

Figure 9-70: The waveform of SVID

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Figure 9-71: The starting timing sequence of ISL95831

The starting procedure of ISL95831: 1) ISL95831 gets VDD and VIN, the chip power on reset(POR),to enter the standby state. the threshold value of VDD is 4.5V(the maximum value),the threshold value of VTN is 4.35V(the maximum value). 2) ISL95831 get the opening signal VR_ON, when the voltage value of this pin reaches to 0.7V(the minimum value of ISL95831FIRTZ),starts soft start. 3) The internal DAC voltage starts to rise as the slope of 2.5mV/us 4) When DAC voltage rises to the value set by the RPROG1 resistance, the soft start is over. 5) ISL95831 open drain outputs PGOOD, and pulls ALERT# low to send to CPU. 6) CPU sends a serial VID signal to ISL95831. 7) According to the serial VTD signal setting, ISL95831 adjusts and outputs the CPU core power supply to the corresponding value (VID setting is shown in table 9-17). 8) After the core voltage being normal, ISL95831 again pulls ALERT# low, means that the voltage has been normal. 9) When the chip again received the corresponding SVID signal of control second of power supply, the chip outputs an integrated graphics (UMA) power supply.

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Laptop Chip Level Repair Guide Table 9-17: The standard table of serial VIN decoding of ISL95831

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9.5.5 Analysis of commonly used chip ISL6265 by AMD platform ISL6265 is commonly used in the motherboard of AMD CPU, as the output control of the CPU core power supply and VDDNB power supply. The size of chip is 6mm*6mm, QFN48 packaged. The pin name of ISL6265 is shown in figure 9-72.

Figure 9-72: The pin name of ISL6265 (the top view)

The pin definition of ISL6265 is shown in table 9-18.

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Laptop Chip Level Repair Guide Table 9-18: The pin definition of ISL6265

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Laptop Chip Level Repair Guide (Pins) ----------- (Description) of ISL6265 l. the external connects the resistance to the ground programming DC current source. If this pin is 1.2V, VFIX mode is closed; if this pin is pulled up to be 3.3V, VFIX mode is opened. DAC decoder analyzes the input information of SVC and SVD, OFS function is closed; if this pin is pulled up to be 5V, OFS and VFIX are closed 2. the power good signal, open drain output, needs to be pulled up by the external. then it will be high level 3. the system po2wer good signal input. When this pin is high, SVID interface is active, I C protocol is running. When this pin is low, the input state of SVC,SVD and VFIXEN decides PRE-PWROK METAL YID or YFIX mode voltage. Before ISL6265 sent the high level of PGOOD, this pin must be low 4.

serial VID identification pin data signal, connects with AMD processor

5.

serial VID identification pin clock pin, connects with AMD processor

6.

the enable signal input, when its high level,ISL6265 is opened

7. connects the 117kΩ resistance to the ground, sets the internal reference current 8.

the over-current of CORE_0 and CORE_1 setting signal input

9.

CORE_0 differential amplification output

10. CORE_0 feedback input, to the input end of the internal CORE_0 error amplifier 11.

CORE_0 controller error amplifier output

12. from this pin connecting the resistance to COMPO to set the switch frequency, for example, 6.81kΩ is 300kHz 13.

the positive input of CORE_0 current detection

14.

the negative input of CORE_0 current detection

15

.CORE_0 voltage detection input

16.

the input loop of CORE_0 voltage detection

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The input loop of CORE_1 voltage detection

18.

CORE_1 voltage detection input

19.

CORE_1 differential amplification output

20. CORE_1 feedback input, to the input end of the internal CORE_1 error amplifier 21.

CORE_1 controller error amplifier output

22. from this pin connecting the resistance to COMF1 to set the switch frequency of the chip, for example,6.81kΩ is 300kHz 23.

the positive input of CORE_1 current detection

24.

the negative input of CORE_1 current detection

25.

CORE_1 boot-strap end

26.

CORE_1 high-end MOSFET driver signal output

27. CORE_1 phase pin, connects the output inductance. This pin is the loop of the high-end tube drive signal 28.

the ground terminal

29.

CORE _1 low-end MOSFET driver signal output

30. the internal MOSFET driver power supply, connects the external 5V power supply voltage input 31.

CORE_0 low-end MOSFET driver signal output

32.

the ground terminal

33. CORE _0 phase pin, connects the output inductance. This pin is the loop of the high-end tube drive signal 34.

CORE_0 high-end MOSFET driver signal output

35.

CORE_0 boot-strap end

36.

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Laptop Chip Level Repair Guide 37.

the high-end MOSFET driver signal output of NB power supply

38. the phase pin of NB power supply, connects the output inductance. This pin is the loop of the high-end tube drive signal 39.

the low-end MOSFET driver signal output of NB power supply

40.

the ground terminal

41.

the over-current protection setting of NB power supply

42 .

the voltage feedback of NB power supply

43.

the voltage feedback input of NB power supply

44. the switch frequency setting end of NB power supply, for example, 22.1 kΩ is set to be 260kHz 45.

the error amplification input of NB power supply

46.

the feedback input of NB power supply

47. 5V power supply input, external connection of a decoupling capacitor with 0.1 uF 48. the chip power supply input pin; is used to improve the transient performance

The important pin threshold voltage of ISL6265: When VCC input voltage is higher than 4.35V(the typical value),is shown in figure 9- 73, the chip implements POR (Power-On Reset).When VCC input voltage is less than 4.1V (typical value), the chip stops working.

Figure 9-73: The screenshot of the description of the electrical features of VCC threshold value in ISL6265 data manual

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Laptop Chip Level Repair Guide The typical value of the low level of threshold value of EN pin of ISL6265 is 1.35V,the high level of threshold value is 2V(typical value),is shown in figure 974.

Figure 9-74: The screenshot of the description of the electrical features of EN threshold value in ISL6265 data manual

The input low level of threshold value of PWROK pin of ISL6265 is usually 0.65V,the high level of threshold value is usually 0.9V,is shown in figure 9-75.

Figure 9-75: The screenshot of the description of the electrical features of PWROK threshold value in ISL6265 data manual

When PWROK is low level.ISL6265 chip does not implement SVID instruction, but implement the corresponding voltage according to the state set by VFIXEN: when WIXEN connects to 1.2V below or about SV. implements PRE-PWROK METAL VID mode, the voltage configured by VID is shown in table 9-19.in this working mode, when SVC and SVD are low level, the output voltage is 1.1V; when SVC and SVD are high level, the output is 0.8V.

Table 9-19: The ISL6265 PRE-PWROK METALVID mode decoding

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Laptop Chip Level Repair Guide Table 9-21: VFIX mode decoding

When WIXEN of ISL6265 connects to 3.3V, implements WIX mode, the voltage configured by VID is shown in table 9-20.in this mode, when SVC and SVD are low level the output voltage is 1.4V; when SVC and SVD are high level, the output voltage is 0.8V. Figure 9-76 is the typical application figure of ISL6265. The working process of ISL6265 is shown in figure 9-77. The transverse digital means the time, the vertical signal will change with time. As follows: Time 1-2: VCC input. And crossed POR (4.3V),to complete the chip self-reset. Time 2-3: SVC and SVD are pulled up or pulled low by the external, sets pre_ Metal VID code Time 3-4: after EN changing to be the high level. VDD and VDDNB starts up, rises to the value set by pre_ Metal VID mode. Time 4-5: VDDPWRGF changes to be the high level. Indicates that CPU power supply has been normal. Time 5-6: PWROK inputs the high level, indicates that the chip ready to receive SVI code. Time 6-7: CPU drives SVD and SVC to start to transmit SVI instructions. Time 7- 8: ISL6265 responds to SVI code instructions. Time 8-9: if PWROK changes to be low, the chip stops SVI decoding immediately, and drives CPU voltage to the value set by Pre_ PWROK Metal VID.

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Figure 9-76: The typical application figure of ISL6265

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Figure 9-77: The working timing sequence figure of ISL6265

Time 9-10: PWROK changes to be high, indicates that the chip readies to receive instructions again. Time 10-11: SVC and SVD transmits new VID code. Time 11-12: ISL6265 drives CPU power supply voltage to the new value set by SVI.

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Chapter 10 Analysis of QUANTA OEM Laptop Mainboard Circuit There have three kinds of the protective isolation circuit of Quanta, the RTC circuit, standby circuit and the sequence of subsequent trigger power-on are basically no difference. This chapter mainly takes CT6 as an example to explain RTC circuit, protective isolation circuit and complete power-on sequence. In addition, to explain the protective isolation circuit of ZQ5 and AX1.

10.1: Analysis of Quanta CT6 RTC Circuit The RTC circuit of Quanta CT6 mainly includes the following voltage and signal: VCCRTC, RTCRST#, 32.768kHz, INTVRME.

1. VCCRTC The name of VCCRTC of the South Bridge still comes from VCCRTC, is shown in figure 10-1.

Figure 10-1: The screenshot of VCCRTC power supply about the South Bridge

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Laptop Chip Level Repair Guide The origin of VCCRTC voltage is shown in figure 10-2, when there is no external power supply, is produced by the CMOS battery BT1 with 3V through R196, D5; after 3VCPU producing (the principle of production is shown in 10.3 section), 3VCPU with 3.3V is added to VCCRTC through D4.due to the characteristic of the diode, D5 will be cut-off, CMOS battery can save electricity. In addition, the CMOS battery in this circuit is a rechargeable battery:5VCPU produces 3.8V voltage through the partial pressure of R201 and R203 to the B pole of Ql8,the triode Q18 will convert the voltage of 3 pin input to 1 pin output the voltage is about 3.1 V this 3.1V is directly charged to BT1.

2. RTCRST# In the figure 10-2,also shows the origin of the RTCRST#, that is, after VCCRTC being normal, delay produced through R198.C220.G1 is the short contact, CMOS discharged can be achieved.

3. 32.768kHz In the figure 10-2, 32.768 kHz crystal, that is the South bridge connects the crystal Y2 through RTXC1, RTCX2 pin, and get 32.768kHz frequency.

Figure 10-2: The screenshot of RTC Circuit

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4. INTVRMEN Internal Voltage Regulator Enable (INTVRMEN): This signal enables the internal 1.05 V Suspend regulator when connected to VccRTC. When connected to Vss. the internal regulator is disabled.

Figure 10-3: INTVRMEN

Another key RTC signal of the South Bridge is INTVRMEN, is easily overlooked by many people. the definition of this signal in ICH7 is: Internal Voltage Regulator Enable: This signal enables the internal 1.05 V Suspend regulator when connected to VccRTC. When connected to Vss, the internal regulator is disabled. If the South bridge hasn't this signal, it will lead to not trigger fault. The origin of this signal is shown in figure 10-3,in this figure,R205 is not installed, INTVRMEN is pulled up to be high by VCCRTC through R206.and is set to be the voltage regulator to open the internal of the South bridge. Figure 10-3 the screenshot of INTVRMEN circuit

10.2: Analysis of Quanta CT6 Protective Isolation Circuit Let's look at the full figure about the protective isolation and the charging circuit of Quanta CT6, is shown in figure 10-4.

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Figure 10-4: The full figure about the protective isolation and the charging circuit of Quanta CT6

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Laptop Chip Level Repair Guide In the figure 10-4,the production of the common point(the battery and the adapter pass through this point together to supply the power to the system, then this point is called the common point)voltage VIN. Need to go through PQ 15, this P channel tube need to be conducted, and controlled by PQ4, and PQ4 is controlled by ACOK with high level, is shown in figure 10-5. Figure 10-4 the figure of CT6 protective isolation and the charging circuit.

Figure 10-5: The circuit where PQ4 is in Let's look at the production of ACOK: as shown in figure 10-6, the docking station voltage VA and the adapter interface voltage VA2 supply the power supply pin DCIN of MAX1772, the inside of MAX1772 produces LDO voltage 5.4V and 4.096V reference voltage (shown in figure 10-7);the other path through PR40 and PR49 divided into the voltage, then send to AC1N pin of MAX 1772.

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Laptop Chip Level Repair Guide Figure 10-6: The circuit diagram of DCIN and ACIN of MAX1772

Figure 10-7: The internal block diagram of the LDO production of MAX1772

The detailed pin definition text of ACIN and ACOK in the MAX1772 data manual is in the following. ACIN: AC Detect Input. Detects when the AC adapter voltage is available for charging. ACOK: AC Detect Output. Open-drain output is high when ACIN is less than REF/2. According to the pin definition of ACIN and ACOK in MAX 1772 data manual, when ACIN input voltage is higher than half of RET, the chip will output the low level signal from ACOK pin. As shown in figure 10-6,VA/VA2 through the diode divide into the voltage, then ACIN is produced, after calculation, as long as the diode cathode is greater than 13.26V,it can make ACIN greater than 2.048V,and producing the low level of ACOK, this signal send to B pole of PQ1,E pole of PQ1 has 5.4V linear voltage, so PQ1 is conducted, and producing ACOK signal with 5V. As shown in figure 10-8, ACOK with 5V is sent to PQ4,to make it to be conducted,3 pin is grounded,VA3 through PQ5 internal resistance and PR46 divide into the voltage, after dividing into the voltage, the conducted condition of PQ15 is satisfied; produces the common voltage VIN.

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Figure 10-8: The production circuit of VIN

Note: there is a circuit to be payed attention, as shown in figure 10-9,this circuit is valid just in the battery mode, is the battery low-voltage protection circuit. The test conclusion by the author is: BL/C# and D/C# in this circuit are used in combination. Under the adapter mode, BL/C is driven as high by EC,PQ34 is always conducted, 1 pin of the comparator PU10 is greater than 3 pin,4 pin open leak output is pulled up as the high level by 3VPCU,and added to S pole of PQ36.At this time, no matter whether D/C is low or high,PQ36 will not be conducted. Under the battery mode, BL/C# is not defined by EC, the initial is low level. When VIN voltage is normal, through the series partial pressure of PR143and PR146 and the clamping of PD19, it's also greater than the voltage of the comparator 1 pin the comparator 4 pin output the low level, at this time. D C will be driven as high level by EC, make PD7 to be conducted, pull low the G pole of PQ4.cut-off PQ4,close the isolation circuit it of the adapter. At the same time, EC receives BL/C# with low level, indicating that the battery voltage is enough. Under the battery mode, when VIN voltage falls below 7.5V,the comparator 1 pin will be greater than 3 pin,4 pin output the high level, produces the high level of BL/C#(Battery Low is valid / at the high level) through PR144,inform EC to execute outage. And the high level of BL/C# will control PQ34 to be conducted, continues to pull low the comparator 3 pin, and keeps the comparator + port is greater than - port, always output the high level of BL/C#, the lock-in circuit

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Laptop Chip Level Repair Guide can realize the battery low-voltage protection function. When the adapter is inserted again, it can be unlocked.

Figure 10-9: The low-voltage circuit diagram under the battery mode

10.3: Analysis of Quanta CT6 Power-On Sequence Circuit The common point VIN supplies to MAX1999,through PR79 and PR80 divide into the voltage to SHDN, is shown in figure 10-10.According to the working principle of MAX 1999,MAX 1999 outputs 3V_AL, 5V_AL respectively from LDO3 pin and LDO5 pin. And 5V_AL is sent to VCC pin of the chip, as well as ON3, ON5.When VCC is normal, it produces 2V reference voltage, and when ON3 and ON5 are normal, MAX1999 controls two paths of PWM work, produces 3VPCU, 5VPCU respectively. After working of the chip being normal, open leak outputs PGOOD, and connects to HWPG. 5VPCU through PD11, PC63 and 1999_DL3 superimposing, and outputs +10V after PD11, PC59 rectifying. +IOV produces +15V through PD10, PC62, PC61 circuit.

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Figure 10-10: MAX1999 Standby circuit

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Laptop Chip Level Repair Guide Produced 5VPCU to send to V5REF_SUS of the South bridge, is shown in figure 10-11. 3VPCU voltage is supplied to EC, to be EC (U23) standby voltage, is shown in figure 10- 12.

Figure 10-11: V5REF_SUS power supply of the South Bridge

Figure 10-12: EC Standby power supply

EC external 32.768 kHz crystal oscillator, supplies the clock in the state of standby for EC is shown in figure 10-13.

Figure 10-13: EC Standby clock

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Laptop Chip Level Repair Guide 3 VPCU delayed through the resistance, capacitance, supplies the reset in the state of standby for EC PC87541, is shown in figure 10-14.

Figure 10-14: EC Standby reset

EC reads the EC code stored in the BIOS chip and configures GPIO pin through X-BUS bus, is shown in figure 10-15 and figure 10-16. The power supply of BIOS is 3VPCU.

Figure 10-15: X-BUS bus of EC

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Figure 10-16: BIOS chip Press the power button and produce the boot trigger NBSWON# to EC, is shown in figure 10-17.

Figure 10-17: EC receive the switch signal

EC sends S5_ON to produce 3V_S5 through the circuit as shown in figure 1018, and finally sends to VCCSUS3_3 of the South bridge.

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Figure 10-18: S5_ON control circuit

Next, EC delays send RSMRST# to the South Bridge, is shown in figure 10-19.

Figure 10-19: EC sends RSMRST# RSMRST# is sent to the South Bridge, then. after, EC meeting the condition that ACIN,LID_EC# are high(as shown in figure 10-20:when SW1 is not closed, LID_EC# is pulled up to be high level by 3VPCU),sends the pulse DNBSWON#591 with "high-low-high" level, and converts to DNBSWON# through D20 to send to PWRBTN# of the South bridge, is shown in figure 1021.

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Figure 10-20: SW1 circuit

Figure 10-21: EC sends DNBSWON#591

Figure 10-22: South Bridge sends SLP_S*#

The South bridge standby condition RTC,cireuit,VCCSUS3_3,RSMRST# are normal, and after receiving PWRBTN#, sends SLP_S5#,SLP_S4#,SLP_S3# first, the SLP_S5# is not to be used.SLP_S4# renamed SUSC# through the resistance R347,SLP_S3# renamed SUSB# through the resistance R342,is shown in figure 10-22.

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Laptop Chip Level Repair Guide SUSB# and SUSC# signal are sent to EC, after EC receiving SUSC# and SUSB#, sends SUSON and MAINON successively. SUSON is sent to PU3, after PU3 meeting the power supply of 14, 19, 22 pin and the opening of 23 pin, outputs the memory main power supply +1.8VSUS, when the memory main power supply is normal, open leak outputs POK, and connects to HWPG, is shown in figure 10-23.

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Figure 10-23: The Producing circuit of the memory main power supply

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Figure 10-24: SUSON control produced SUSD

SUSD is used to control PQ37 and PQ10 conducted, produces 5VSUS and 3VSUS is shown in figure 10-25.

Figure 10-25: The production of 5VSUS and 3VSUS

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Laptop Chip Level Repair Guide MAINON is used to open the following voltage: MAINON controls to produce the memory load power supply (the memory bus termination voltage SMDDR_VTERM),is shown in figure 10-26.This is the production chip of the memory load power supply and the reference voltage, after getting VIN and VCDDSSNS and S5,it will output VTTREF; and after getting VLDOIN,S3,it will output VTT, tests the voltage of VTT by VTTSNS.

Figure 10-26: The production of the memory load power supply

MAINON send to ON1,ON2 of MAX1540,controls to produce the South bridge main power supply with -M.5V and the front bus voltage with +1.05V,is shown in figure 10- 27.This is a dual PWM power supply chip. the main power supply V+, open signal ONl,ON2.When two paths of the power supply are normal, open leak outputs PGOODl,PGOOD2,are connected to HWPG.

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Figure 10-27: The production circuit of +1.5V and +1.05 http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide MAINON produces MAIND through the circuit shown in the figure 10-28.

Figure 10-28: The production of MAIND

MAIND is used to open +5V and +3V with the state of S0, is shown in figure 10-29.

Figure 10-29: MAIND control circuit

PG signal from PCU standby power supply chip, the memory power supply chip, the South bridge main power supply and the front bus power supply chip connected together through the resistance to form HWPG and sent to 63 pin of EC, is shown in figure 10- 30.1f EC don't receive this signal, it will lead to the common fault of power down for Quanta motherboard. http://www.XiuFix.com/laptop-chip-level-repair/

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Figure 10-30: EC received HWPG After EC receiving HWPG, delays send VR_ON to 35 pin of the CPU power supply chip, is used to open CPU power supply VCC_CORE, when the CPU power supply is normal, then sends VR_PWRGD_CK410# with low level and DELAY_VR_PWRGDOOD with high level, is shown in figure 10-31.

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Figure 10-31: CPU power supply circuit

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Laptop Chip Level Repair Guide VR_PWRGD_CK410# opens the clock chip, and the clock chip sends each clock is shown in figure 10-32.

Figure 10-32: The clock chip circuit VR_PWRGD_CK410# is sent to VRMPWRGD pin of the South bridge by U42 inverted, informs the South bridge that CPU power supply has been normal at this time, is shown in figure 10-33.

Figure 10-33: The South Bridge received VRMPWRGD

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Laptop Chip Level Repair Guide CPU power supply chip sends DELAY_VR_PWRGOOD to U29,phase with PWROK delayed sent by EC after receiving HWPG, output 1CH_PWROK to send to PWROK pin of the South bridge, is shown in figure 10-34.

Figure 10-34: The South Bridge received PWROK At last, the South Bridge sends H_PWRGD from CPUPWRGD pin to CPU, is shown in figure 10-35.

Figure 10-35: CPU received PWRGOOD The South bridge sends PLTRST# and PCI_RST# to each onboard chip and slot, is shown in figure 10-36.

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Figure 10-36: The South Bridge sent PLTRST# and PCIRST# One of the paths of PLTRST# is sent to RSTIN# pin of the North Bridge, DELAY_VR_WRGOOD is also sent to the North Bridge, is shown in figure 10-37.

Figure 10-37: The North Bridge received PG and Reset

At last the North Bridge sends H_CPURST# to CPU, is shown in figure 1038.After CPU receiving the reset, sends H_ADS# from HI pin to E8 pin of the North Bridge. If we can catch this signal from T4 test point, then indicates that the motherboard hard boot is finished, and CPU has started addressing.

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Figure 10-38: The North Bridge sent CPURST#

10.4: The Analysis of Quanta ZQ5 (Acer AS4733Z) Protective Isolation Circuit First, the voltage of the adapter produces VA1 through PL12, is shown in figure 10-39.

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Figure 10-39: Insert adapter to produce VA1

VA1 reaches the common point VIN through PD10 and PQ56,is shown in figure 10- 40.The conducted conduction of PQ56 is that the voltage of G pole should be low level relatively, that is, l pin and 6 pin of PQ5 should be cut off, VA2 partial pressure to be about 9.5V through PR19 and PR17.

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Figure 10-40: The producing circuit diagram of VIN http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide The condition of 1 pin and 6 pin of PQ5 been cut off is that 2 pin should be high level (PNP triode), it also can be understood us 3 pin and 4 pin must be cut off (NPN triode), so 5 pin D/C should be low level. D/C# comes from EC, when used the adapter singly. Due to the system just connected to the power, the subsequent stage power supply is not produced, EC has not power supply, and D/C #is low level. So VIN can come out directly. The means of D/C#: DISCHARGE in the high level, CHARGE in the low level. This board just have D/C#, not BL/C#, according to the actual measurement, the adapter is low after detecting D/C#, and is high in the battery mode. Let's us analysis the adapter detection circuit of EC. VA1 supplies the power to DCIN of ISL88731 through PD1 and PR78 is shown in figure 10-41.

Figure 10-41: VA1 supplies the power to DCIN of ISL88731

Figure 10-42

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Laptop Chip Level Repair Guide According to the internal block diagram (shown in figure 10-42) of ISL88731, ISL88731 will produce VDDP and VREF. the description of the electrical characteristics about the threshold value of VDDP and VREF output voltage in the data manual is shown in the figure 10-43,the standard value of VDDP output voltage is 5.1V,when VDDP load current is less than 30mA,the output is only 35mV error; VREF output voltage is 3.2V(the standard value). Then, let's us look the pin definition of ACIN and ACOK. ACINL: AC Adapter Detection Input. Connect to a resistor divider from the AC adapter output. ACOK: AC Detect Output. This open drain output is high impedance when ACIN is greater than 3.2V. The ACOK output remains low when the ISL88731 is powered down. Connect a 10k pull-up resistor from ACOK to VDDSMB.

Figure 10-43: The text screenshot of the electrical specification description about the threshold value of VDDP and VREF output voltage It means that AC is the adapter detection input pin. ACOK is the adapter detection output pin. When the voltage of ACIN is higher than the reference voltage 3.2V, ACOK open drain output, it can connect ACOK to VDDSMB pin through 10kΩ resistance. VA1 through PD1 and is divided into the voltage in series by PR149 and PR150,then is sent to ACIN ,by calculating, the lowest voltage cannot be less than 15.2V after VA1 through the diode PDI. The calculation of the partial pressure is shown in figure 10-44.

Figure 10-44: The calculation of the series partial pressure

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Laptop Chip Level Repair Guide If the voltage of VA1 is not lower than the limit value, ACOK will open drain output, 3VPCU through PR131 and is pulled up to be 3.3V, then sends to EC. After EC receiving this signal, can keep D/C to be the low level. PQ 15 is cut off, G pole of PQ39 is pulled up to be the high level by VIN through PR40 directly.PQ39 is cut off the battery is isolated, is shown in figure 10-45.In the battery mode, BAT produces small current VIN through PQ39 diode, then produces the power supply of EC.EC detects the high level of D/C# sent by the adapter, and makes PQ15 conducted, VIN partial pressure through PR40 and PR39, PQ39 is conducted completely.

Figure 10-45: The isolation and discharge of the battery

10.5: Analysis of Quanta AX1 Protective Isolation Circuit It needs to through PD20, PQ52 from the adapter CN17 to the common point VIN; and it needs to through PQ55 from the battery CN16 to the common point, is shown in figure 10-46.PQ52 is connected together to the G pole of PQ55, are BATDIS_G. lf BATD1S_G is high level, PQ52 will be conducted, PQ55 will be cut off; on the contrary, PQ52 will be cut off. PQSS will be conducted. If it needs the adapter supply the power to the system, then BATDIS_G must be high level and the voltage should be high enough (more than 23.5V).

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Figure 10-46: VIN production circuit

Amplifier the part of the PQ52 circuit is shown in figure 10-47. There are three conditions of BATDIS_G being high level: (1) Pull-up voltage +VH28; (2) ACOK# must be low level, PQ56 is cut off, and PR229 does not participate in partial pressure; (3) ACOK_IN can't be grounded. In the figure 10-47,if ACOK# is high, or ACOK_ IN is low, it will cause the +VH28 partial pressure to form BATDIS_G. the voltage is only 0.019V. The specific calculation is shown in figure 10-48.

Figure 10-47: PQ52 circuit

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Figure 10-48: Partial pressure calculation

Then, lets us analysis these three conditions: Condition (1): +VH28 comes from PU2(P2805MF),is shown in figure 1029,this is the boost chip with internal integrated the boost circuit.VA of 19V through PDO to +VAD_1,supplies to PU2,PU2 internal boost produces +VH28.When the boost is successful .the chip open drain output 6251ACIN.

Figure 10-49: The production of +VH28 Conduction (2): ACOK# comes from the ACPRN output of ISL6251, is shown in figure 10-50.

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Figure 10-50: The source of ACOK#

According to the data manual of ISL6251, the pin definition of ACPRN is: Open-drain output signals AC adapter is present. ACPRN pulls low when ACSET is higher than 1.26V; and pulled high when ACSET is lower than 1.26V From the figure 10-50, +VA produces +VAD_1 through PD0, and supplies the power to DCIN of ISL6251 through PD1, the other path is to through PR235, PR236 partial pressure to ACSET.ISL6251 outputs ISL6251_VDDP from VDD after receiving DCIN, the voltage is 5.07V (the typical value), is shown in figure 10-51.

Figure 10-51: The screenshot of the description of the electrical characteristic about VDD output threshold value in ISL6251 data manual (datasheet)

The internal principle is shown in figure 10-52, after inputting DCIN, then output VDD. In the figure 10-50,after ISL6251 getting ACSET, it will compare with the internal 1.26V,if ACSET is higher than 1.26V,the comparator outputs the high level, the field- effect transistor is conducted and pulls ACPRN low, is shown in figure 10-53.

Figure 10-52 VDD output internal principle diagram of ISL6251

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Figure 10-53: ACSET internal principle diagram of ISL6251 By calculation, the +VAD_ l voltage must be higher than 11.4V. (According to the figure 10-49, figure 10-59,6251ACIN signal of ACSET pin connected to the PG of the boost chip PU2, if PU2 does not succeed in boosting, 6251ACIN will also be pulled low.) Condition (3):ACOK_IN connects to PQ9 is shown in figure 10-54.To keep ACOK_IN not grounded, PQ9 must be cut off, and then there must have the low level of D/C#.

Figure 10-54: ACOK_IN connection circuit D/C# comes from EC, is shown in figure 10-55, before the common point produced, the standby chip is not working, EC has not voltage, and is also not working, so D/C# will not be high level; after EC getting the power supply, EC must detect that the adapter exists (ACIN is high), then will keep D/C to be low. If EC is not detected the adapter, D/C# will be set high by EC.

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Figure 10-55: The screenshot of D/C# and ACIN of EC

The origin of the adapter test signal of EC is shown in figure 10-56. ACOK# with low level controls PQIO conduction, converts -1SL6251__VDD to ACOK, then through PR84, PR85 partial pressure, produces ACIN to EC as the adapter test signal.

Figure 10-56: The production circuit of ACIN

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Chapter 11 Analysis of WISTRON OEM Laptop Mainboard Circuit The circuit and sequence of Wistron are not too many features, it can also be said that its feature is quite satisfactory. The RTC circuit is similar to those of the Quanta, the batter}' is usually not chargeable; the power-on sequence is the Intel 'standard sequence. This chapter is not much introduced the RTC circuit and the power-on sequence. Mainly, to explain the protective isolation and the standby circuit.Then.as Wistron HBLJ16-1.2 an example to analyze the protective isolation and the standby circuit.

11.1: Analysis of Wistron HBU16-1.2 Protective Isolation Circuit Insert the adapter, producing AD_JK, added to the S pole of U1, though the partial pressure of R2 and RI produced the low level of 6.3V, control U1 conducted and produced AD+ (when inserted the adapter. because EC is no power, AD_OFF is low level; only when the system program control forced to discharged the battery, then EC will send the high level of AD_OFF), is shown in figure 11-1.

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Figure 11-1: The screenshot of AD+ production circuit AD+ produced the small current common point DCBATOUT through U2 body diode, 18.3V, is shown in figure 11-2.

Figure 11-2: The production of the small current common point AD+ is added to the G pole of U7, makes it cut off, the battery is isolated, is shown in figure 11-3.

Figure 11-3: The screenshot of the battery isolation circuit

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Laptop Chip Level Repair Guide AD+ supplies the power to DCIN of the charge chip U44 (MAX8731) and divides into the voltage to ACIN, is shown in figure 11-4.

Figure 11-4: The screenshot of DCIN and ACIN circuit When DCIN is power on, U44 outputs 5.4V MAX8731_LDO from LDO pin is shown in figure11-5. About the figure 11-6, is the relationship between DCIN and LDO of MAX8731 internal block diagram.

Figure 11-5: LDO output

Figure 11-6: The internal principle diagram of LDO production

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Laptop Chip Level Repair Guide In the data manual of MAX8731, the screenshot of the electrical characteristic description about DCIN effective value is shown in figure 11-7. DCIN effective value is 8-26V, the under-voltage lockout value is 7.4V (typical value).

Figure 11-7: The screenshot of the electrical characteristic description about DCIN threshold value in the data manual of MAX8731 MAX8731_LDO supplies the power to VCC pin through R204, is shown in figure 11-8.

Figure 11-8: The circuit screenshot of LDO supply power to VCC When VCC is power on, 4.096V reference voltage REF produced by the MAX8731 internal, is shown in figure 11-9. The ACOK pin definition is: AC Detect Output. This open-drain output is high impedance when ACIN is greater than REF/2. The ACOK output remains low when the MAX8731 is powered down. Connect a 10kΩ pull up resistor from VCC to ACOK. ACIN compared with the half of REF in the internal, when ACIN is greater than REF/2(2.048V), ACIN open drain output, is shown in figure 11-10.

Figure 11-9: The internal principle diagram of the production of MAX8731 reference voltage

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Figure 11-10: The screenshot of ACOK output principle of MAX8731 As long as AD+ voltage is higher than 17.767V,ACIN will be greater than 2.048V,ACOK Will open drain output ACAV_IN, is shown in figure 11-11.The calculation process is shown in figure 11-12.

Figure 11-11: The screenshot of ACOK output ACAV_IN

ACAV_IN is divided into the voltage by MAX8731_LDOto be 3.3V high level by MAX873l_LDO. Through Q3 to produce the low level of AD_IN# to EC (as the adapter test signal of EC), is shown in figure 11-13. The other path controls 3-4 pin conducted of U3, makes R183 grounded. The small current common point through R182 and R183 to form partial pressure, and produces about 6V voltage to send to 4 pin (G pole) of U2, the S pole of U2 is 18.3V.the G pole is 6.1V,U2 channel is fully opened, AD+ directly flows to the common point, producing the large current common point, is shown in figure 11-14.

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Figure 11-12: The screenshot of AD+ threshold value calculation

Figure 11-13: The screenshot of the adapter test signal production of EC

Figure 11-14: The screenshot of the large current common point production circuit

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11.2: Analysis of Wistron HBU 16-1.2 Standby Circuit After the common point voltage DCBATOUT producing, input to supply the power to VIN of the standby chip U30.is shown in figure 11-15.

Figure 11-15: The circuit diagram of VIN supply power to U30 The standby chip is using TPS51125. When it got VIN, because ENO is grounded through 820K resistance, set the linear voltage opened automatically, but close VCLK, is shown in figure 11-16.

Figure 11-16: The screenshot of TPS51125 circuit

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Laptop Chip Level Repair Guide According to TPS51125, working principle analyzed in the 9.2.2 section. After TPS51125 getting VIN and ENO, the chip outputs +3VL, and renamed to be +3VL_KBC, is shown in figure 11-17. +3VL_KBC is supplied to EC as the standby voltage, is shown in figure 11-18.

Figure 11-18: The screenshot of EC standby power supply After EC getting power supply, to supply the voltage to X2, crystal oscillator starts, and sends to EC standby clock 32.768 kHz, is shown in figure 11-19.

Figure 11-19: EC standby clock circuit http://www.XiuFix.com/laptop-chip-level-repair/

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Laptop Chip Level Repair Guide +3VL_KBC pulled up VCC_POR#, as the standby reset of EC, is shown in figure 11-20.

Figure 11-20: The principle of EC reset production After the standby condition of EC being satisfied, reads ROM (U25) through SPI bus of 86,87,90,92 pin (shown in figure 11-21).ROM circuit is shown in figure 11-22.the power supply of U25 is also came from +3VL_ KBC.

Figure 11-21: SPI bus pin of EC

Figure 11-22: The screenshot of U25 circuit

After EC reading the program normally, will configured their pin. Then EC identifies the adapter insert test signal AD_IN# of 93 pin, is shown in figure 1123. EC detects that the low level of the adapter is inserted an indication signal, then sends automatically the high level of PWR_S5_EN, is shown in figure 11-24.

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Figure 11-23: The adapter test signal of EC

Figure 11-24: E sends PWR_D5_EN PWR_S5_EN controls Q42 conduction, Q40 and Q41 will cut off, is shown in figure 11- 25. 51125_ENTRIP1 and 51125_ENTRIP2 are cannot grounded directly, it just can be grounded through R498 and R508.

Figure 11-25: The screenshot of the circuit controlled by PWR_S5_EN

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Laptop Chip Level Repair Guide 51125_ENTRIP1 and 51225_ENTRIP2 connected to 1 pin and 6 pin of TPS51125. According to the pin definition of TPS51125 in the 9.2.12 section, it can open chip through the resistance grounded and as an over-current threshold value setting. TPS51125 outputs two paths of PWM power supply, is shown in figure 11-27: 3D3V_PWR, 5V_PWR, through isolation point respectively to rename to be +3VALW and +5VALW.

Figure 11-26: The screenshot of 1 pin and 6 pin of TPS51125

Figure 11-27: The screenshot of the circuit of 3D3V_PWR and 5V_PWR renamed

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Laptop Chip Level Repair Guide +3VALW and +5VALW supply respectively to VCCSUS3_3 and V5REF_SUS of the South bridge; as the South bridge standby voltage, is shown in figure 1128 and figure 11- 29.

Figure 11-28: 3.3V standby voltage of the South Bridge

Figure 11-29: 5V standby voltage of the South Bridge

EC delayed send PM_RSMRST#, is shown in figure 11-30.

Figure 11-30: EC sends PM_RSMRST#

PM_RSMRST# is converted to be RSMRST#_SB, is shown in figure 11-31.

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Figure 11-31: PM_RSMRST# renamed to be RSMRST#_SB

RSMRST#_SB is sent to the South Bridge, is shown in figure 11-32.

Figure 11-32: RSMRST#_SB is sent to the South Bridge

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Chapter 12 Analysis of COMPAL OEM Laptop Mainboard Circuit The greatest feature of the motherboard designed by Compal is the protective isolation and the standby circuit. the power-on sequence and the RTC circuit is almost the standard sequence. This chapter introduces three kinds of Compal protective isolation circuit. Then explain one of the Compal standby circuit.

12.1: Analysis of Compal LA-5891P Protective Isolation and The Standby Circuit In this section, takes Compal LA_5891P as an example to analyze the protective isolation and the standby circuit.

1. The protective isolation circuit Insert the adapter, through the power connects to PJPl, and produces VIN, 19V through PL24, is shown in figure 12-1.The figure of Compal motherboard power interface is shown in 12-2.

Figure 12-1: The production of VIN http://www.XiuFix.com/laptop-chip-level-repair/

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Figure 12-2: Compal Mainboard power interface

VIN produces VS through the parallel connection of PD2, PR304 and PR305, and produces Nl through PQ42 diode, changes to be CHGRTCP through PR306, then through PR309 to produce N2 to supply the power to the pressure regulator, PU14 outputs 3.3V of RTCVREF, is shown in figure 12-3.

Figure 12-3: The production circuit of RTCVREF

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Laptop Chip Level Repair Guide VIN compares with RTCVREF after through PR297 and PR301 diving into the voltage, if the voltage of VIN is higher than 17.24V (make a rough calculation after ignoring the hysteresis resistance: the results of VIN/ (PR297+PR301) x PR301 is higher than 3.3V), the comparator will open drain output as is diving into the voltage by VIN and through PD1 steady pressure to produce the high level of PACIN and ACIN, is shown in figure 12-4.

Figure 12-4: The production circuit of PACIN and ACIN If we count in the hysteresis resistance, the falling edge of the VIN voltage threshold value is 17.525 V, the rising edge is 17.901V, is shown in figure 12-5.

Figure 12-5: The screenshot of the VIN threshold value voltage VIN crosses PD14 and four parallel resistances, makes PQ67 conduction. Supply power to B+, is shown in figure 12-6. (When PD14 pressure drop of 1mA, the voltage is about 0.7V, when pressure drop of 10mA, the voltage is about 1V. You can consult the data manual of LL4148). If the value of resistance of B+ grounded is higher than 1.35kΩ. Make a rough calculation: if VIN is 19V, PD14 pressure drop is lV: (19V-lV)/(250+RB+) x RB+=15.2V, so RB+ =1357Ω So the voltage B+ got is higher than 15.2V.

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Figure 12-6: Power supply in B+ production circuit After detected the adapter, PACIN is high level, makes PQ69 conducted and makes PR395 and PR394 to be parallel connection. the value of resistance is 138kΩ after parallel connection, B+ through PR387 and divides into the voltage with the parallel resistance, is shown in figure 12-7.If the voltage of B+ is higher than 15.2V (ignore the hysteresis resistance PR385), the voltage will higher than 3.3V after dividing into the voltage, the comparator open drain outputs, and is pulled up to be a high level by VL. ACON is not pulled low (VL comes from the standby chip, we will analyze it in the standby circuit).

Figure 12-7: The screenshot of the ignition loop circuit

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Laptop Chip Level Repair Guide If B+ line short circuit, the value of resistance is less than 1.35kΩ, the voltage value is pulled below 15.2V; the voltage got by the resistance dividing into the voltage will be lower than RTCVREF voltage 3.3V,the comparator 7 pin outputs the low level. Then ACON, MAINPWON are pulled low. This is the power supply in advance circuit also called ignition loop. The ignition loop is divided into three cases (ignore the hysteresis resistance).

Figure 12-8: B+ threshold voltage setting in the adapter and battery mode (1) When PACIN is low, PQ69 is cut off, PR394 is not grounded, does not participate in the partial pressure circuit, B+ minimum cannot be less than 6.6V (the battery mode). (2) When PACIN is high, but before +5VALW produced, PQ71 is cut off, PQ69 is conducted, PR394 and PR395 being in parallel, then series partial pressure with PR387. B+ minimum cannot be less than 15.2V (when the adapter is just inserted). (3) When PACIN is high.+5VALW is produced.PQ71 is conducted,PQ69 is cut off,PR394 is not grounded, as long as B+ is not less than 6.6Y.then it can make the comparator open drain output the high level, ACON and MAINPWON are not pulled low(the adapter mode, the ignition has been completed). As the figure 12-8 shown, after adding the hysteresis resistance, the detection threshold value of B+, the adapter mode is 14.8V~15.9V.the battery mode is 6.2V~7.3V (select the intermediate value). About Compal machine, for example to non-program controls the correction of the battery electricity and forces to open the battery discharge, EC always outputs the low level of ACOFF, PQ65 is cut off. PACIN is high, ACON is not pulled low by the comparator, PQ63 obtains the G pole voltage with high level, PQ63 is conducted, is shown in figure 12-9.

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Figure 12-9: The circuit of PACIN and ACON VIN produces P2 through the body diode of PQ51, through PR354 and PR361 then through PQ63 to be grounded, and forms partial pressure, produces about 8V voltage to add to the G pole of PQ51 and PQ52, make it conducted completely, VIN flows to B+, the common point of the large current produced, is shown in figure 12-10.

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Figure 12-10: The production circuit of the large current B+ (1) ACON is high, and makes PQ59 conducted at the same time, PQ58 will be cut off, and PQ56 will also be cut off. (2) If ACON is low or PACIN is low, it will make PQ63, PR354 and PR361 not partial pressure, P2 with 18V through PR354 to pull up the G pole of PQ51 & PQ52, two separate tubes are cut off. At the same time,PQ59 is cut off, the B pole of PQ58 is pulled up by VIN,PQ58 is conducted,PQ56 is also conducted,P2 flows to the C pole through the E pole of PQ56,then added to the G pole of PQ51,PQ52,and make it cut off. The circuit of the battery isolation and discharge is shown in figure 12-11.

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Laptop Chip Level Repair Guide In the figure 12-11, when PACIN is high, PQ61 is conducted, pulls low the positive pole of PD12, PD12 is cut off; ACOFF is also low, PD9 is cut off; the B pole of the triode PQ57 is pulled down to be the low level by its own resistance, PQ57 is cut off, VIN through PR352 to pull up the G pole of PQ53, PQ53 is cut off, the battery is isolated. (1) If VIN is no power, the G pole of PQ53 will pulled down to the grounded by PR352, PQ53 is conducted, the battery discharge. (2) If VIN is power on. but PACIN is low level,PQ61 is cut off, the positive of PD12 is pulled up to be high by PR357,PD12 is conducted,PQ57 is also conducted, VIN through PR352 and PR356 divides into the voltage to the G pole of PQ53,PQ53 is conducted. the battery discharge.

Figure 12-11: The battery isolation circuit (3) If VIN is power on, PACIN is high level, but ACOFF is also high(when the program control forces to discharge to the battery),PD9 is conducted,PQ57 will also be conducted, VIN through I PR352 and PR356 divides into the voltage to the G pole of PQ53,PQ53 is conducted, the battery discharge.

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2. Analysis of the production of VA (the adapter mode and the battery mode) VS production circuit is shown in figure 12-12. Look at the following analysis.

Figure 12-12: VS production circuit The adapter mode: VIN through PD2, then through PR304 and PR305 to produce VS directly. The battery mode: BATT+ through PD3 to produce Nl, sends it to 3 pin of PQ42, it cannot be conducted to VS. PQ42 is a P channel, the condition of conduction is: when 51ON# is the low level, PR307 and PR308 forms partial pressure, produces relatively the low level about 2V, at this time, the G pole is 2V, the S pole is 11V, VGV-, outputs VCC logic, when V+