Tessent MBIST [PDF]

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Why do Memory BIST?

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Architectural overview

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Generation of BIST hardware

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Insertion

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Verification

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We need to be on job !!

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Nearly 90% of chip area is covered by memories.

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Are the most fallible chip components.

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Need to detect in lowest possible cost!

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Parallel and sequential testing of memories.

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Selection of library Algos, provision to define userdefined Algos.

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Diagnose memory fails to freeze on specific BIST step, error count or memory test port.

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Perform repair analysis.

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Post-silicon Programmability.

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Flexibility to design optimal BIST configurations to meet chip power & test-time budget.

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Non- Programmable Controllers

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Programmable Controllers

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Usage of Pre-defined memory test algorithms for optimized controller and memory collars size and performance. Uses TAP/WTAP Interface. Patented serial-access technique –single bit data path b/w controller and the memory. Less routing and gate overhead. Mirafra Technologies

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Define your own memory test algorithms. ◦ HardProgrammable in the hardware.

◦ SoftProgrammable 

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User-defined algorithms implemented

defined at tester time.

Uses TAP/WTAP Interface. More hardware to enable algorithm programmability and diagnosis.

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Comparators within the Controller (Shared) ◦ Memories tested sequentially. ◦ Routing b/w collars and the controller – significant for wider memories.

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Comparators within the Memory Collar/Interface (Local) ◦ Routing overhead is eliminated. ◦ Cannot be shared by memories – increase in area overhead.

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Checks the design for test compliance. Identifies insertion locations for testpoint and dedicated isolation cells. Two modes: ◦ Clock Extraction Mode:

Memory source clock traced back to a PI/to an output of a black box or an output of a register (Eg. Clock divider)

◦ Rule Check Mode:

Checks for compliance with Constraint / Scan / Consistency / Analysis / Clock & Verilog Rules.

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lv.Target -type Top/Block

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lv.EmbeddedTest -bscan On -memory On -logic Off

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lv.BlackBoxModule -name PLL

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lv.ClockDomainBase -pin "car.CK33" -frequency 33 -label CLK33MHz -polarity 1

etchecker car \ ../GATE/CAR/car.v \. ./GATE/DASHBOARD/dashboard.v \. ./GATE/ENGINE/engine.v \. ./GATE/NAVIGATION/navigation.v \

-y ../PLL \ -y ../MEM \ -y ../../Dolphin/tsmc13/lvision \ -y ../../Dolphin/tsmc13/verilog \ -v ../../Dolphin/tsmc13/verilog/pads.v \ -memLib ../MEM/*.lvlib \

-mode clockInfo \ -padLib ../../Dolphin/tsmc13/lvision/pad.library \ -batch off

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Plans the embedded test solution for the entire chip.

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Generates the automated work environment.

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Creates .etplan & ETSummary files.

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Can make a trade-off b/w test quality, test time, power and area at this stage. Ensure all memories in the design are BISTed. Mirafra Technologies

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etplanner car \ -mode genPlan \ -etCheckerInfoFile\ ../DESIGN/ETChecker/etcHandoff/car.etCheckerInfo \ -CADEnvFile ./CentralFiles/HWLib.CADEnv \ -ICTechFile ./CentralFiles/Dolphin_tsmc13.LVICTech \ -etDefFile ./CentralFiles/HWLib.ETDefaults \ -etplanFile car.etplan \ -physicalInfoFile car.physicalInfo \ -memLib ../DESIGN/MEM/*.lvlib \ -outDir outDir \ -log etplanner.log_genPlan

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Frequency

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Clock domains

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Prog/Non-Prog memories

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Test time – number of memories per controller

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Power – number of memories per controller

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Proximity of memories Mirafra Technologies

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Implements the solution generated by etchecker and etplanner. Steps involved ◦ ◦ ◦ ◦ ◦ ◦

Embedded test –JTAP, WTAP, MBIST Controllers, Memory collars/interfaces. Config etsignoff –Testbenches for early verification of embedded features. Designe – Looks for hierarchies and BIST hook up. Synth – Synthesises the tessent generated RTL based embedded test structures. Concatenated netlist – Post-tessent netlist generation. Lvdb_prelayout/testbench/sim – Signoff database generation and simulation.

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Performs DFT verification. Generates testbenches based on .etsignoff file. Run simulation – UD / SDF sims. Performs formal verification b/w DC netlist and post-tessent netlist.

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That’s all folks!!

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