Sinowealth SH367008X 038XY AAD01 - C160914.zh CN - en [PDF]
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Translated from Chinese (Simplified) to English ‑ www.onlinedoctranslator.com
SH367005/SH367005S/SH367007/SH367008 Preliminary 1
Series Lithium Battery Pack Protection chip
characteristic
‑
Voltage detection function:
‑
Overcharge protection voltage V OV : 3.6V~4.5V( Gear 10mV) ；
Discharge high temperature protection temperature: 70°C ; Discharge high temperature protection temperature accuracy: ±4°C (Max) ; Balance function:
Overcharge protection voltage accuracy: ±25mV ；
‑
Overcharge protection release voltage V OVR
1 : 3.3V~4.5V( Gear 10mV) ；
‑
‑ ‑
Balance turn‑on threshold voltage: 3.3V‑4.45V (10mV First gear) Threshold voltage accuracy: ± 25mV
Overcharge protection release voltage accuracy: ±50mV ；
Over discharge protection voltage V UV : 2.0V~3.1V( Gear 100mV) ；
The external capacitor sets the over‑discharge protection delay and discharge over‑current 1 Protection delay and
Over‑discharge protection voltage accuracy: ±50mV ；
discharge overcurrent 2 Protection delay
Over discharge protection release voltage V UVR
Overcharge protection and release delay, charge overcurrent protection and release delay, short circuit protection
2 : 2.0V~3.6V( Gear 100mV) ；
Over‑discharge protection release voltage accuracy: ±100mV ；
delay, undervoltage release delay, discharge overcurrent release delay, short circuit release
Discharge overcurrent detection function:
Time delay, temperature protection and release time delay are fixed;
‑
Overcurrent 1 Protection voltage V DOC1 : 0.025V~0.25V( Gear 25mV) ；
CTLC/CTLD Pin control CHG/DSG Pin output;
‑
Overcurrent 2 Protection voltage V DOC2 : 0.05V~0.5V( Gear 50mV) ；
‑ 3V ~ 26V ( SH367005 );
Overcurrent 2 Protection voltage accuracy: ±20mV ;
‑ 3V ~ 26V ( SH367005S );
Overcurrent 1 Protection voltage accuracy: ±10mV ；
Operating voltage range:
Short circuit detection function:
‑
‑ 6V ~ 52V ( SH367007 );
Short circuit protection voltage V SC : 0.1V~1V( Gear 100mV) ；
‑ 9V ~ 78V ( SH367008 );
Short circuit protection voltage accuracy: ±50mV ；
range of working temperature:‑ 40°C ~ 85°C ；
Charging overcurrent detection function:
‑
integrated N‑MOSFET drive;
Overcurrent protection voltage V COC : (‑ 10mV ,‑ 20mV ,‑ 50mV ,without);
Normal working power consumption: 15μA (Max.) ；
Overcurrent protection voltage accuracy: ± 5mV (‑ 10mV );
Package form:
Overcurrent protection voltage accuracy: ± 10mV (‑ 20mV ,‑ 50mV );
‑ TSSOP 20L(SH367005) ；
Temperature detection function:
‑ TSSOP 20L(SH367005S) ；
‑
Charging high temperature protection temperature: 50°C ; Temperature
‑ TSSOP 28L(SH367007) ；
accuracy of charging high temperature protection: ±4°C (Max) ；
‑
‑ TSSOP 38L(SH367008) ；
Charging low temperature protection temperature: 0 ℃; Accuracy of charging low temperature protection temperature: ±4°C (Max) ；
Note 1: Overcharge hysteresis voltage n(n = 1~15) Is equal to 0V~0.5V Between 10mV Is a selected value of the interval; ( Overcharge hysteresis voltage = overcharge protection threshold voltage‑overcharge protection release voltage) Note 2: Overdischarge hysteresis voltage n(n = 1~15) Is equal to 0V~0.7V Between 100mV Is a selected value of the interval; ( Over‑discharge hysteresis voltage = over‑discharge protection release voltage‑over‑discharge protection threshold voltage) Note 3: The difference between the over‑charge protection voltage and the balance turn‑on voltage is ( 0~400mV );
1
V 0.4
Preliminary 2
SH367005/005S/007/008 series lithium battery PACK protection chip
Overview
SH36700X 4 Built‑in high‑precision voltage detection circuit and delay circuit to monitor voltage, current and temperature to ensure Pack Safety. At the same time, the series of chips also have
Balance function to extend battery life. SH367005 Suitable for protection 4~5 String lithium battery Pack ； SH367005S Suitable for protection 3~5 String lithium battery Pack ； SH367007 Suitable for protection 6~10 Lithium battery
Pack ； SH367008 Suitable for protection 11~15 String lithium battery Pack .
Note 4: All in the text SH36700X Both represent SH367005/SH367005S/SH367007/SH367008 ；
2
Pool
Preliminary 3
SH367005/005S/007/008 series lithium battery PACK protection chip
System Block Diagram
VDD
Load/charger
VC1
Detection module
VM CHSE
balance
switch
VC2 Temperature check
balance
Test module
switch
VC3
TS
Overvoltage/undervoltage balance
switch
DS
/balance Comparator module
VC4
Logic module Protection extension balance
Time module
switch
DSD CDC
VC5 CTLC
balance
switch
GND
CTLD
SEL0 MOSFET Drive module
Overcurrent protection Protection module
RS1
CHG
RS2
figure 1 SH367005 System Block Diagram
3
DSG
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
figure 2 SH367005S System Block Diagram
4
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
image 3 SH367007 System Block Diagram
5
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
Figure 4 SH367008 System Block Diagram
6
Preliminary 4
SH367005/005S/007/008 series lithium battery PACK
Pin diagram
Figure 5 SH367005/SH367005S/SH367007/SH367008 Pin diagram
7
Protection chip
Preliminary 5
SH367005/005S/007/008 series lithium battery PACK protection chip
Pin definition
5.1 SH367005 Pin definition surface 1. SH367005 Pin description Pin number
Pin name
I/O
1
CTLC
I
Function description
CHG Output control pin (the priority is higher than the internal protection circuit of the chip);
2
CTLD
I
DSG Output control pin (higher priority than the internal protection circuit of the chip);
3
CHSE
I
Charger detection pin;
4
VM
I
Load detection pin;
5
CHG
O
Charge MOSFET Drive pin
6
DSG
O
Discharge MOSFET Drive pin
7
DSD
I/O
Over‑discharge delay control pin;
8
CDC
I/O
Discharge overcurrent 1/2 Delay control pin;
9
RS2
I
Current detection positive terminal;
10
RS1
I
Current detection negative terminal (close to GND);
11
TS
I
Temperature detection pin;
12
DS
I
The delay time shortens the terminal;
13
SEL0
I
14
GND
P
15
VC5
I
16
VC4
I
17
VC3
I
18
VC2
I
19
VC1
I
20
VDD
P
SEL0 = GND : SH367005 monitor 5 String cell SEL0 = VDD : SH367005 monitor 4 String cell The fifth section of the battery negative terminal connection pin (chip ground terminal); The fifth section (lowest section) the positive end of the battery is connected to the pin;
The positive end of the fourth battery core is connected to the pin;
The positive end of the third battery core is connected to the pin;
The positive end of the second battery core is connected to the pin;
The first section (the highest section) of the positive end of the battery is connected to the pin;
The positive end of the power supply is connected to the pin;
8
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
5.2 SH367005S Pin definition surface 2. SH367005S Pin description Pin number
Pin name
I/O
1
SEL1
I
Number of cell strings configuration terminal 1
2
CTLD
I
DSG Output control pin (higher priority than the internal protection circuit of the chip);
3
CHSE
I
Charger detection pin;
4
VM
I
Load detection pin;
5
CHG
O
Charge MOSFET Drive pin
6
DSG
O
Discharge MOSFET Drive pin
7
DSD
I/O
Over‑discharge delay control pin;
8
CDC
I/O
Discharge overcurrent 1/2 Delay control pin;
9
RS2
I
Current detection positive terminal;
10
RS1
I
Current detection negative terminal (close to GND);
11
TS
I
Temperature detection pin;
12
DS
I
The delay time shortens the terminal;
13
SEL0
I
14
GND
P
15
VC5
I
16
VC4
I
17
VC3
I
18
VC2
I
19
VC1
I
20
VDD
P
Function description
Number of cell strings configuration terminal 0
The fifth section of the battery negative terminal connection pin (chip ground terminal); The fifth section (lowest section) the positive end of the battery is connected to the pin;
The positive end of the fourth battery core is connected to the pin;
The positive end of the third battery core is connected to the pin;
The positive end of the second battery core is connected to the pin;
The first section (the highest section) of the positive end of the battery is connected to the pin;
The positive end of the power supply is connected to the pin;
9
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
5.3 SH367007 Pin definition surface 3. SH367007 Pin description Pin number
Pin name
I/O
1
VDD1
P
Power supply positive terminal connection pin 1 ；
2
SEL2
I
Number of cell strings configuration terminal 2 ；
3
Number of cell strings configuration terminal 1 ；
Function description
SEL1
I
4
CTLD
I
DSG Output control pin (higher priority than the internal protection circuit of the chip);
5
CHSE
I
Charger detection pin;
6
VM
I
Load detection pin;
7
CHG
O
Charge MOSFET Drive pin
8
DSG
O
Discharge MOSFET Drive pin
9
DSD
I/O
Over‑discharge delay control pin;
10
CDC
I/O
Discharge overcurrent 1/2 Delay control pin;
11
RS2
I
Current detection positive terminal;
12
RS1
I
Current detection negative terminal (close to GND);
13
TS
I
Temperature detection pin;
14
DS
I
The delay time shortens the terminal;
15
SEL0
I
Number of cell strings configuration terminal 0 ；
16
GND
P
17
VC10
I
18
VC9
I
19
VC8
I
20
VC7
I
The seventh section of the battery core is connected to the pin;
The positive end of the sixth battery core is connected to the pin;
twenty one
VC6
I
twenty two
VDD
P
twenty three
VC5A
I
twenty four
VC5
I
25
VC4
I
26
VC3
I
27
VC2
I
28
VC1
I
The tenth section of the battery core negative terminal connection pin (chip ground terminal);
The tenth section (the lowest section) the positive end of the battery is connected to the pin;
The positive end of the ninth section of the battery is connected to the pin;
The positive end of the eighth battery core is connected to the pin;
The positive end of the power supply is connected to the pin;
The negative terminal of the fifth section of the battery is connected to the pin;
The positive end of the fifth section of the battery is connected to the pin;
The positive end of the fourth battery core is connected to the pin;
The positive end of the third battery core is connected to the pin;
The positive end of the second battery core is connected to the pin;
The first section (the highest section) of the positive end of the battery is connected to the pin;
10
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
5.4 SH367008 Pin definition surface 4. SH367008 Pin description Pin number
Pin name
I/O
Function description
1
VC1
I
2
VDD2
P
3
NC
‑
No Connect ；
4
SEL3
I
Number of cell strings configuration terminal 3 ；
5
NC
‑
6
SEL2
I
Number of cell strings configuration terminal 2 ；
7
SEL1
I
Number of cell strings configuration terminal 1 ；
8
CTLD
I
The first section (the highest section) of the positive end of the battery is connected to the pin;
Power supply positive terminal connection pin 2 ；
No Connect ；
DSG Output control pin (higher priority than the internal protection circuit of the chip);
9
CHSE
I
Charger detection pin;
10
VM
I
Load detection pin;
11
CHG
O
Charge MOSFET Drive pin
12
DSG
O
Discharge MOSFET Drive pin
13
DSD
I/O
Over‑discharge delay control pin;
14
CDC
I/O
Discharge overcurrent 1/2 Delay control pin;
15
RS2
I
Current detection positive terminal;
16
RS1
I
Current detection negative terminal (close to GND);
17
TS
I
Temperature detection pin;
18
DS
I
The delay time shortens the terminal;
19
SEL0
I
Number of cell strings configuration terminal 0 ；
20
GND
P
twenty one
VC15
I
The fifteenth section (the lowest section) the positive end of the battery is connected to the pin;
twenty two
VC14
I
The fourteenth battery core positive terminal connection pin;
twenty three
VC13
I
twenty four
VC12
I
25
VC11
I
26
VDD
P
27
VC10A
I
28
VC10
I
29
VC9
I
30
VC8
I
31
VC7
I
The seventh section of the battery core is connected to the pin;
32
VC6
I
The positive end of the sixth battery core is connected to the pin;
33
VDD1
P
34
VC5A
I
35
VC5
I
36
VC4
I
37
VC3
I
38
VC2
I
The fifteenth section of the battery negative terminal connection pin (chip ground terminal);
The thirteenth section of the positive end of the battery is connected to the pin;
The twelfth section of the positive end of the battery is connected to the pin;
The eleventh section of the positive end of the battery is connected to the pin;
The positive end of the power supply is connected to the pin;
The negative terminal of the tenth battery core is connected to the pin;
The positive end of the tenth battery core is connected to the pin;
The positive end of the ninth section of the battery is connected to the pin;
The positive end of the eighth battery core is connected to the pin;
Power supply positive terminal connection pin 1 ；
The negative terminal of the fifth section of the battery is connected to the pin;
The positive end of the fifth section of the battery is connected to the pin;
The positive end of the fourth battery core is connected to the pin;
The positive end of the third battery core is connected to the pin;
The positive end of the second battery core is connected to the pin;
11
Preliminary 6
SH367005/005S/007/008 series lithium battery PACK protection chip
Function description
6.1 Normal mode When all the following conditions are met, SH36700X In normal mode: 1. All cell voltages are at the overcharge protection voltage ( V OV) And over‑discharge protection voltage ( V UV) between; 2. RS2‑RS1 The voltage is at the charging overcurrent protection voltage V COC And discharge overcurrent 1 Protection voltage V DOC1 between; 3. TS The pin detection temperature is at the charging high temperature protection temperature T COT Low temperature protection with charging T CUT between;
4. No balance occurs 5. CHG Output V CHG Level, DSG Output V DSG Level, Discharge MOS Are in the normal open state . 6.2 Overcharge protection status When all the following conditions are met, SH36700X Enter the overcharge protection state:
1. Any cell voltage is higher than the overcharge protection voltage V OV ； 2. state( 1) Duration exceeds overcharge protection delay t OV ; When in the overcharge protection state, CHG The pin outputs a high‑impedance state. When the following conditions are all met, the overcharge protection status is released:
1. All cell voltages are lower than the overcharge protection release voltage V OVR ； 2. state( 1) The duration exceeds the overcharge protection release delay; Note 5: Withdraw the overcharge hysteresis function, that is, in the overcharge protection state, when CHSE Level is higher than V CHSE2 At the same time, the voltage of all cells is less than the overcharge protection voltage V OV , Then charge MOS Turn it on again, and the overcharge protection status is released.
Figure 6 Overcharge protection state transition diagram
12
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
6.3 Over‑discharge protection status: When all the following conditions are met, SH36700X Enter the over‑discharge protection state: 1. Any cell voltage is lower than the over‑discharge protection voltage V UV ；
2. state( 1) The duration exceeds the over‑discharge protection delay t UV ; When in the over‑discharge protection state, DSG The pin outputs a low level. When the following conditions are met, the over‑discharge protection state is released:
1. All cell voltages are higher than the over‑discharge protection release voltage V UVR ； twenty one) The duration of the medium state exceeds the over‑discharge protection release delay; Note 6: If the chip has an over‑discharge load lock function, when it is in the over‑discharge protection state, CHG The pin outputs a high‑impedance state, DSG The pin outputs a low level. When the following conditions are met at the same time, The over‑discharge status is released, retreat Overdischarge The load lock delay is 64mS :
1 , Connect the charger or unplug the load (judgment conditions for unplugging the load: VM Pin voltage is lower than V VM ; Judgment conditions when the charger is connected: CHSE Pin voltage is lower than V CHSE1) ； 2 , The voltage of all cells is higher than the over‑discharge protection release voltage ( V UVR ); 3 , ( 2 ) The duration of the medium state exceeds the over‑discharge protection release delay.
6.4 Discharge overcurrent protection status SH36700X Built‑in two‑level discharge overcurrent protection, discharge overcurrent 1 Protection voltage V DOC1 Less than discharge overcurrent 2 Protection voltage V DOC2 , Discharge overcurrent 1 Protection delay T DOC1
Over discharge 2 Protection delay T DOC2 . When all the following conditions are met, SH36700X Enter the discharge overcurrent protection state: 1. RS2‑RS1 Voltage is higher than discharge overcurrent 1 Protection voltage V DOC1( Discharge overcurrent 2 Protection voltage V DOC2) ； twenty one) Medium state duration exceeds discharge overcurrent 1 Protection delay t DOC1( Discharge overcurrent 2 Protection delay t DOC2) ; When in the discharge overcurrent protection state, CHG The pin outputs a high‑impedance state, DSG The pin outputs a low level. When the following conditions are met, the discharge overcurrent protection status is released:
1. Load pull out (judgment conditions for load pull out: VM Pin voltage is lower than V VM) ； twenty one) The duration of the medium state exceeds the discharge overcurrent protection release delay t DOCR ； Note 7: Discharge overcurrent 1/2 After protection, at this time SH36700X Turn on VM The internal resistance is pulled down to GND To determine whether the load is unplugged.
( Discharge current>Overcurrent 1 Protection current)&
( Discharge current>Overcurrent 2 Protection current)&
( Delay time>Overcurrent 1 Protection delay)
( Delay time>Overcurrent 2 Protection delay)
Overcurrent 1 Save
Overcurrent 2 Save
Normal mode
State of care
State of care
( Load pull out)&
( Load pull out)&
( Delay time>overcurrent release delay)
( Delay time>overcurrent release delay)
Figure 7 State transition diagram of discharge overcurrent protection
13
Big
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
6.5 Short circuit protection status When all the following conditions are met, SH36700X Enter the short‑circuit protection state: 1. RS2‑RS1 The voltage is higher than the short‑circuit protection voltage V SC ； twenty one) The duration of the medium state exceeds the short‑circuit protection delay t SC ; When in the short‑circuit protection state, CHG The pin outputs a high‑impedance state, DSG The pin outputs a low level. When the following conditions are all met, the short‑circuit protection status is released:
1. Load pull out (judgment conditions for load pull out: VM Pin voltage is lower than V VM) ； twenty one) The duration of the medium state exceeds the short‑circuit protection release delay t SCR ； Note 8: After short circuit protection, at this time SH36700X Turn on VM The internal resistance is pulled down to GND To determine whether the load is unplugged.
Figure 8 Short‑circuit protection state transition diagram
6.6 Charge overcurrent protection status SH36700X Built‑in charging overcurrent protection, when the following conditions are met, SH36700X Enter the charging overcurrent protection state: 1. RS2‑RS1 The voltage is less than the charging overcurrent protection voltage V COC ； twenty one) The duration of the medium state exceeds the delay of charging overcurrent protection t COC;
When in the charging overcurrent protection state, CHG The pin outputs a high‑impedance state, DSG The pin outputs a low level. When the following conditions are met, the charging overcurrent protection state is released:
1. Charger unplugging (judgment conditions for charger unplugging: CHSE Pin voltage is higher than V CHSE1) ； twenty one) The duration of the medium state exceeds the charge overcurrent protection release delay t COCR ；
Note 9: After charging overcurrent protection, SH36700X Turn on the charger detection circuit to determine whether the charger is unplugged.
( (Charging current>charging overcurrent protection current)
&( Delay time>Charge overcurrent protection delay)
Charging overcurrent
Normal mode
Protection status
( Unplug the charger) & ( Delay time> charge overcurrent release delay)
Figure 9 State transition diagram of charging overcurrent protection
14
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
6.7 Temperature protection when TS Pin external temperature resistance (temperature resistance adopts NTC , It is recommended to use 103AT) Hour, SH36700X Can carry out temperature protection, including: charging high temperature protection, charging Low temperature protection and discharge high temperature protection.
When temperature resistance is used 103AT(β=3435) When, the temperature protection rules are as follows:
6.7.1 Charging high temperature protection status
When all the following conditions are met, SH36700X Enter the charging high temperature protection state:
1. The temperature is higher than the charging high temperature protection temperature T COT ；
2. state( 1) Duration exceeds the temperature protection delay t T ; When in the charging high temperature protection state, if it is detected as a charging state, then CHG The pin outputs a high‑impedance state. When the following conditions are met, the charging high temperature protection state is released:
1. The temperature is lower than the charging high temperature protection recovery temperature T COTR ；
2. state( 1) The duration exceeds the temperature protection release delay t TR ；
Note 10:
In the charging high temperature protection state, if the discharging state is detected, the charging MOS Turn it back on.
6.7.2 Charging low temperature protection status
When all the following conditions are met, SH36700X Enter the charging low temperature protection state:
1. The temperature is lower than the charging low temperature protection temperature T CUT ；
2. state( 1) Duration exceeds the temperature protection delay t T ; When in the charging low‑temperature protection state, if it is detected as a charging state, then CHG The pin outputs a high‑impedance state. When the following conditions are all met, the charging low‑temperature protection state is released:
1. The temperature is higher than the charging low temperature protection recovery temperature T CUTR ；
2. state( 1) The duration exceeds the temperature protection release delay t TR ；
Note 11:
In the charging low temperature protection state, if the discharging state is detected, the charging MOS Turn it back on.
6.7.3 Discharge high temperature protection state
When all the following conditions are met, SH36700X Enter the discharge high temperature protection state:
1. The temperature is higher than the discharge high temperature protection temperature T DOT ；
2. state( 1) Duration exceeds the temperature protection delay t T ; When in the discharge high temperature protection state, CHG The pin outputs a high‑impedance state, DSG The pin outputs a low level. When the following conditions are all met, the high‑temperature discharge protection state is released:
1. The temperature is lower than the discharge high temperature protection recovery temperature T DOTR ；
2. state( 1) The duration exceeds the temperature protection release delay t TR ；
15
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
Discharge high temperature protection state
CHG Pin output high impedance state
DSG Pin output low level
(The system is in a discharge state) &
) &
CHG Pin
( Temperature>Discharge high temperature protection temperature
(Delay Time>Temperature Protection Delay)
High output
( TemperatureTemperature protection release delay)
High output
flat
flat
(RS2‑RS1 level>VDCH) &
(RS2‑RS1 level>VDCH) & (Delay time> charge and discharge state switch
Change delay)
(Delay time> charge and discharge state switch
) &
( Temperature>charging high temperature protection temperature)&
( temperature
(Delay Time>Temperature Protection Delay)
Charging high temperature protection status
Charging low temperature protection status
Normal mode
CHG Pin output high impedance state
( Temperature Charging low temperature protection recovery temperature)&
(Delay time>Temperature protection release delay)
(Delay time>Temperature protection release delay)
Figure 10 Temperature protection state transition diagram
SH36700X Recommended temperature resistance 103AT(β=3435) , Its corresponding resistance at different temperatures is shown in the following table: surface 5. 103AT(β=3435) Relation table of resistance value and temperature
103AT resistance( KΩ)
Resistance variation range ( KΩ)
‑20
67.77
72.72~63.20
‑15
53.41
57.11~49.98
‑10
42.47
45.27~39.86
‑5
33.90
36.02~31.92
0
27.28
28.90~25.76
5
22.05
23.29~20.88
Temperature point ( °C)
25
10
9.700~10.30
45
4.911
5.094~4.735
47
4.554
4.691~4.417
50
4.16
4.306~4.018
55
3.536
3.654~3.421
60
3.02
3.115~2.927
65
2.588
2.665~2.513
70
2.228
2.291~2.167
16
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
6.8 Balance function SH36700X In the monitoring system, when the voltage of any cell exceeds the balanced opening voltage V OB , And the duration exceeds the balance opening delay t BL , SH36700X The series chips will turn on the internal balance circuit to balance the cell. The above function is called the balance function. SH36700X Series chip balance function adopts odd‑even balance method, that is, phase Adjacent cells will not be balanced at the same time, the balance period is 250mS . When any of the following conditions are met, the system exits the balance sequence:
(1) Cell voltage is lower than V OB ； (2) A temperature protection occurs.
6.9 Judgment of charging and discharging state
SH36700X Depend on RS2‑RS1 Voltage to judge the charging and discharging status of the system . when RS2‑RS1 The pin voltage is higher than the discharge state detection voltage V DCH , Then it is determined that the system is in a discharge state . Except for the discharge state , The system is charging . SH36700X The delay time to determine the switching of the charge and discharge state is t STATUS .
7
Function setting
7.1 CTLC/CTLD Pin setting SH36700X In the series of chips, CTLD Pins are used to control DSG The output of the pin has a higher priority than the internal protection circuit of the chip. SH367005 In the chip, CTLC Pin control CHG The output of the pin has a higher priority than the internal protection circuit of the chip. The specific operation method is as follows:
surface 6. CTLC/CTLD Pin function
CTLC Pin
GND Hang in the air
VDD
CHG Pin
CTLD Pin
DSG Pin
GND
High impedance
High impedance
GND Level GND Level
Hang in the air
VDD
Depends on internal protection circuit
Depends on internal protection circuit
7.2 DS Pin setting SH36700X In the series of chips, under normal circumstances DS Pull up to internal by internal resistor 5V Level when DS Pin voltage is lower than V DS When entering the mass production mode, the delay time will be shortened after entering the mass production mode. Please refer to the table for the delay time in the mass production mode. 9 .
7.3 String setting SH367005 middle, SEL0 Pins are used for configuration 4/5 For string applications, the specific operation methods are shown in the following table:
surface 7. 4~5 String configuration
SEL0
Chip function
VDD
4 String battery protection
GND
5 String battery protection
Cell input terminal
4 string
5 string
VC1~VC2
CELL1
CELL1
VC2~VC3
CELL2
CELL2
VC3~VC4
CELL3
CELL3
VC4~VC5
CELL4
CELL4
VC5~GND
SHORT
CELL5
17
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
SH367005S middle, SEL0/SEL1 Pins are used for configuration 3/4/5 For string applications, the specific operation methods are shown in the following table:
surface 8. 3~5 String configuration
SEL1
SEL0
GND
GND
3 String battery protection
VDD
VDD
4 String battery protection
VDD
GND
5 String battery protection
Cell input terminal
Chip function
4 string
3 string
5 string
VC1~VC2
SHORT
CELL1
CELL1
VC2~VC3
SHORT
CELL2
CELL2
VC3~VC4
CELL3
CELL3
CELL3
VC4~VC5
CELL4
CELL4
CELL4
VC5~GND
CELL5
SHORT
CELL5
SH367007 middle, SEL0/SEL1/SEL2 Pins are used for configuration 6~10 For string applications, the specific operation methods are shown in the following table: surface 9. 6~10 String configuration
Cell input terminal
SEL2
SEL1
SEL0
VDD1
GND
GND
6 String battery protection
VDD1
VDD
VDD
7 String battery protection
VDD1
VDD
GND
8 String battery protection
VC5A
VDD
VDD
VC5A
VDD
GND
6 string
Chip function
9 String battery protection
10 String battery protection
7 string
8 string
9 string
CELL1
10 string
VC1~VC2
SHORT
SHORT
SHORT
CELL1
VC2~VC3
SHORT
SHORT
SHORT
CELL2
CELL2
VC3~VC4
CELL1
CELL1
CELL1
CELL3
CELL3
VC4~VC5
CELL2
CELL2
CELL2
CELL4
CELL4
VC5~VC5A
CELL3
CELL3
CELL3
CELL5
CELL5
VC6~VC7
SHORT
CELL4
CELL4
CELL6
CELL6
VC7~VC8
SHORT
CELL5
CELL5
CELL7
CELL7
VC8~VC9
CELL4
CELL6
CELL6
CELL8
CELL8
VC9~VC10
CELL5
CELL7
CELL7
CELL9
CELL9
VC10~GND
CELL6
SHORT
CELL8
SHORT
CELL10
SH367008 middle, SEL0/SEL1/SEL2/SEL3 Pins are used for configuration 11~15 For string applications, the specific operation methods are shown in the following table: surface 10. 11~15 String configuration
SEL3
SEL2
SEL1
SEL0
Chip function
VDD2
VDD1
VDD
GND
11 String battery protection
VDD2
VC10A
VDD
VDD
12 String battery protection
VDD2
VC10A
VDD
GND
13 String battery protection
VC5A
VC10A
VDD
VDD
14 String battery protection
VC5A
VC10A
VDD
GND
15 String battery protection
18
Preliminary Cell input terminal
SH367005/005S/007/008 series lithium battery PACK protection chip
11 string
12 string
13 string
14 string
15 string
VC1~VC2
SHORT
SHORT
SHORT
CELL1
CELL1
VC2~VC3
SHORT
SHORT
SHORT
CELL2
CELL2
VC3~VC4
CELL1
CELL1
CELL1
CELL3
CELL3
VC4~VC5
CELL2
CELL2
CELL2
CELL4
CELL4
VC5~VC5A
CELL3
CELL3
CELL3
CELL5
CELL5
VC6~VC7
SHORT
CELL4
CELL4
CELL6
CELL6
VC7~VC8
SHORT
CELL5
CELL5
CELL7
CELL7
VC8~VC9
CELL4
CELL6
CELL6
CELL8
CELL8
VC9~VC10
CELL5
CELL7
CELL7
CELL9
CELL9
VC10~VC10A
CELL6
CELL8
CELL8
CELL10
CELL10
VC11~VC12
CELL7
CELL9
CELL9
CELL11
CELL11
VC12~VC13
CELL8
CELL10
CELL10
CELL12
CELL12
VC13~VC14
CELL9
CELL11
CELL11
CELL13
CELL13
VC14~VC15
CELL10
CELL12
CELL12
CELL14
CELL14
VC15~GND
CELL11
SHORT
CELL13
SHORT
CELL15
7.4 Delay time setting SH36700X In, partial protection delay and protection release delay can be set. The details of the delay time setting are shown in the following table: surface 11. Delay summary content
Label
Overcharge protection delay
t OV
Fixed inside the chip
1S
Over‑discharge protection delay
t UV
DSD Pin external capacitor C DSD
1S×C DSD/ 0.1uF
1/64*t UV
Overcurrent 1 Protection delay
t DOC1
CDC Pin external capacitor C CDC
1S×C CDC/ 0.1uF
1/64*t DOC1
Overcurrent 2 Protection delay
t DOC2
CDC Pin external capacitor C CDC
0.1S×C CDC/ 0.1uF
1/10*t DOC2
t DOCR
Fixed inside the chip
125mS
1mS
t SC
Fixed inside the chip
250uS
t SC
Short circuit protection release delay
t SCR
Fixed inside the chip
125mS
1mS
Charge overcurrent protection delay
t COC
Fixed inside the chip
1S
1/64*t COC
t COCR
Fixed inside the chip
125mS
1mS
t T
Fixed inside the chip
3S
‑
t TR
Fixed inside the chip
3S
‑
t BL
Fixed inside the chip
100mS
‑
Overcurrent protection release delay
Short circuit protection delay
Charge overcurrent protection release delay
Temperature protection delay
Temperature protection release delay
Balance opening delay
Delay
Association settings
19
Mass production mode
15.625mS~140.625mS
SH367005/005S/007/008 series lithium battery PACK protection chip
Preliminary 8
Typical application diagram
8.1 SH367005 5
Serial application
1
1 B+
P+/C+
R1
100
R2
1K
D1
Schottky
Q1 R3
510R
R5
1K
R6
510R
R11
1K
R14
510R
PNP R4
51R
Q2
PNP R8
PNP R15
104/25V
104/25V
104/25V
104/25V
225/25V
Zener
C3
C4
C5
C6
C7
D3
103/25V C1
1K
1K
6 5 4 3 2 1
51R
1K
CELL
Q4 R17
510R
R21
1K
PNP R18
R22
R24
R23
104/25V C9
104/25V 10M
C8 1
51R
510R PNP R25
GND
51R
G S
D
D
CHGNMOS
P‑/C‑
J3
Q5
GND
R27
1M R26
S
G
Q7
1K
R16
SH367005
Q6
51R
Q3 GND
104/25V
VDD VC1 VC2 VC3 VC4 VC5 GND SEL0 DS TS
VDD
C2
CTLC CTLD CHSE VM CHG DSG DSD CDC RS2 RS1
20 19 18 17 16 15 14 13 12 11
103AT
3M 1K 1K 1K
U1
R20
R9 R10 R12 R13
1 2 3 4 5 6 7 8 9 10
R19
1K
D2
FWD
VDD
R7
R28 0.003
1
DSGNMOS GND
B‑
Picture 11 SH367005 Typical application diagram ( 5 (Same port)
8.2 SH367005 5
Serial and semi‑port application
1
1 B+
P+/C+
R1
100
R2
1K
D1
Schottky
Q1 R3
510R
R5
1K
R6
510R
R11
1K
PNP R4
51R
Q2 1K
R9 R10 R12 R13
3M 1K 1K 1K
1 2 3 4 5 6 7 8 9 10
D2
FWD
VDD
R7
U1 CTLC CTLD CHSE VM CHG DSG DSD CDC RS2 RS1
VDD VC1 VC2 VC3 VC4 VC5 GND SEL0 DS TS
20 19 18 17 16 15 14 13 12 11
VDD
PNP R8
R14
GND
104/25V
104/25V
104/25V
104/25V
104/25V
225/25V
Zener
C3
C4
C5
C6
C7
D3
1K R20
C2
103AT
103/25V C1
R19
1K R24
104/25V C9
1K
104/25V C8
R16
1K
R17
510R
R21
1K
R22
510R
Q4
PNP R18
CELL
51R
Q5 R23
10M
6 5 4 3 2 1
51R
GND
GND
PNP R25
51R
R27
G
CHGNMOS
D
G D
S
R26
1 C‑
S
1M
Q7
J3
510R PNP R15
SH367005
Q6
51R
Q3
R28 0.003
1
DSGNMOS GND
1 P‑
Picture 12 SH367005 Typical application diagram ( 5 (Serial half split)
20
B‑
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
8.3 SH367005S 3 Serial application J1
J2 1
1
P+/C+
B+
GND
R4 R5 R6 R8 R9 R11
1 2 3 4 5 6 7 8 9 10
1K 1K 3M 1K 1K 1K
D2
FWD
VDD
U1 SEL1 CTLD CHSE VM CHG DSG DSD CDC RS2 RS1
VDD VC1 VC2 VC3 VC4 VC5 GND SEL0 DS TS
20 19 18 17 16 15 14 13 12 11
VDD
GND
1K
R3
510R
R10
1K
R12
510R
Zener
225/25V
104/25V
104/25V
104/25V
C1
C2
C3
C4
1K
D3
103AT
R14
1K
R15
510R
Schottky
Q1 PNP 51R
J3
Q2 PNP
1 2 3 4
51R
CELL Q3 PNP R16
51R
R18
R17
R20
R19
10M
103/25V C5
1K
1K
104/25V
104/25V C7
C6 CHGNMOS
P‑/C‑
R2
D1
R13
GND
G
GND R22
D
D
G 1
S
R21
J4
S
1M
Q5
100R
R7
SH367005S
Q4
R1
J5
R23 0.003
1
DSGNMOS GND
B‑
Figure 13 SH367005S Type application diagram ( 3 (Same port)
8.4 SH367007 10 Serial application J1
J2 1
1
P+/C+
B+ R1 R2
100R 1K
R3
510R
D1
Q1 PNP R4
R5
1K
R6
510R
R9
510R
R11
1K
R12
510R
Q3 PNP
S
GND
G
104/25V
104/25V
104/25V
104/25V
C3
C4
C5
C6
104/25V
ZENER
C2
20 19 18 17 16 15
225/25V
twenty one
C1
twenty two
VDD D2
twenty three
VC7
VC5A
225/25V
104/25V
104/25V
104/25V
104/25V
104/25V
C12
C13
C14
C15
C16
C17
C11 GND
ZENER
103/25V
SH367007
C9
103AT R29
104/25V
104/25V C8
C7
1K
1K VC7 C10
R31
R30
104/25V
twenty four
GND
Q8
D NMOS
R15
1K
R19
510R
R22
100R
R23 R24
100R 1K
R25
510R
D4
1K 510R
1K
R35
510R
1K
1K
1M
DIODE
R39
510R
R43
1K
R42
R41
1 P‑/C‑
CHGNMOS
10M
510R
R48
51R
51R
51R
Q11 PNP R45
R47
D
D
S
R46
J3
R44
CELL
51R
Q10 PNP R40
G
Q13
G
Q12
S
1M
R38
D6
1K
51R
Schottky
Q9 PNP R36
R37
11 10 9 8 7 6 5 4 3 2 1
Q7 PNP R33
R34
JP1
Q6 PNP R26
R32
51R
Q5 PNP R21
R27
51R
Q4 PNP R13
225/50V
1K 3M 1K 1K
28 27 26 25
D5
1K
R16 R17 R18 R20
VC1 VC2 VC3 VC4 VC5 VC5A VDD VC6 VC7 VC8 VC9 VC10 GND SEL0
1K
R14
D3
FWD
VDD
VDD1 SEL2 SEL1 CTLD CHSE VM CHG DSG DSD CDC RS2 RS1 TS DS
R28
VC5A
U1
51R
1K
R10
1 2 3 4 5 6 7 8 9 10 11 12 13 14
51R
Q2 PNP R7
R8
Schottky
51R J4
0.003
1
DSGNMOS GND
Figure 14 SH367007 Typical application diagram ( 10 (Same port)
twenty one
B‑
Preliminary 8.5 SH367008 15
SH367005/ 005S/007/0 08 series lithium battery PACK protection chip
Serial application
J1
J2
1
1
P+/C+
R1 R2
100R 1K
R3
510R
R5
1K
D1 Q1 PNP R4
R6
510R
51R
Q2 PNP R7
R8
51R
1K
R9
510R
R11
1K
Q3 PNP R10
R12
510R
R14
1K
R15
510R
R17
100R
R18 R19
100R 1K
R20
510R
R22
1K
51R
Q4 PNP R13
51R
Q5
C6 104/25V
C5 104/25V
104/25V
104/25V
ZENER
C1 104/25V
C4
C3
C2
D3
20
510R
R29
1K
R33
510R
R35
1K
104/25V
104/25V C12
C11
104/25V C8
104/25V
104/25V
R36
C10
103AT
1K R43
R24
twenty one
C13
103/25V C17
104/25V
104/25V
Q6
GND
NMOS
510R
51R
51R
CELL
Q9
R39
510R
R44
100R
R45 R46
100R 1K
R47
510R
R49
1K
Q10 PNP R41
104/25V
104/25V C24
C23
104/25V C22
104/25V
104/25V C21
C20
225/25V C19
225/50V
ZENER D7
R55
R53
R54
C18
1K
1K
1M
DIODE D8
R50
510R
R52
1K
D6
R56
510R
R58
1K
Q12
510R
R61
1K
10M
51R
Q15
51R
Q16 PNP R63
G S
D
D
CHGNMOS
R65
1M S
G 1 P‑/C‑
R64
J3
510R
51R
Q14
PNP R60
R62
51R
Q13
PNP R57
R59
51R
Schottky
PNP R51
GND
Q18
51R
1K
PNP R48
Q17
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Q8
PNP R37 R38
JP1
51R
Q7
PNP R34
twenty two
VC10A
Q11
51R
Schottky
PNP R26
twenty three
GND
D2
PNP R21
twenty four VC12
GND
G
D
R42
C16
S
C14
R40
104/25V
C15
1K
VC12
SH367008
VC5A
C9
1K 3M 1K 1K 1K
ZENER
1K
R27 R28 R30 R31 R32
225/25V
R25
38 37 36 35 34 33 32 31 30 29 28 27 26 VDD 25
C7
D4
VDD
1K
VC2 VC3 VC4 VC5 VC5A VDD1 VC6 VC7 VC8 VC9 VC10 VC10A VDD VC11 VC12 VC13 VC14 VC15 GND
225/50V
FWD
VC10A
R23
VC1 VDD2 NC SEL3 NC SEL2 SEL1 CTLD CHSE VM CHG DSG DSD CDC RS2 RS1 TS DS SEL0
D5
VC5A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
225/25V
PNP R16
U1
B+
Schottky
51R J4
R66 0.003
1
DSGNMOS GND
Figure 15 SH367008 Typical application diagram ( 15 (Same port)
twenty two
B‑
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
8.6 SH367005 Power consumption test chart
VDD
20 19 18 17 16 15 14 13 12 11
100R 1K 1K 1K 1K 1K
Schottky
D1
J1 1 2 3 4 5 6
GND
R14 0.003
104/25V
104/25V
104/25V
104/25V
104/25V
C6
C7
C8
C9
C4
C5
Zener
225/25V
D2
CELL
C1 103/25V
SH367005
R2 R3 R5 R7 R8 R9
1K
VDD VC1 VC2 VC3 VC4 VC5 GND SEL0 DS TS
103AT
CTLC CTLD CHSE VM CHG DSG DSD CDC RS2 RS1
R13
U1
R12
1K
1 2 3 4 5 6 7 8 9 10
R11
R10
1K
3M 1K
104/25V
R4 R6
104/25V
1K
C3
R1
C2
VDD
U2
GND
CURRENT
GND Figure 16 SH367005 Power consumption test circuit diagram
8.7 SH367005S Power consumption test chart
R2 R3 R5 R7 R8 R9
100R 1K 1K 1K 1K 1K
GND
Schottky
D1
J1 1 2 3 4 5 6
104/25V
104/25V
104/25V
104/25V
104/25V
C5
C6
C7
C8
C9
225/25V
Zener
GND
C4
D2
1K
CELL 103AT
SH367005S
VDD
20 19 18 17 16 15 14 13 12 11
R13
VDD VC1 VC2 VC3 VC4 VC5 GND SEL0 DS TS
103/25V
SEL1 CTLD CHSE VM CHG DSG DSD CDC RS2 RS1
R12
R14 0.003
U1
C1
1K
1 2 3 4 5 6 7 8 9 10
R11
R10
1K
3M 1K
104/25V
R4 R6
104/25V
1K
C3
R1
C2
VDD
U2
GND Figure 17 SH367005S Power consumption test circuit diagram
twenty three
CURRENT
Preliminary
SH367005/005S/007/008 series lithium battery PACK protection chip
8.8 SH367007 Power consumption test chart
twenty three twenty two
104/25V
104/25V
104/25V
104/25V
104/25V
C3
C4
C5
C6
VDD
twenty one
R8
100R
R12 R13 R14 R15 R16 R17
100R 1K 1K 1K 1K 1K
D1
J1
Schottky
D3
225/25V
104/25V
104/25V
104/25V
104/25V
104/25V
C10
C11
C12
C13
C14
GND
C9
20 19 18 17 16 15
Schottky
100R 1K 1K 1K 1K 1K
VC5A
twenty four
Zener
SH367007
C2
D2
28 27 26 25
D4
VC1 VC2 VC3 VC4 VC5 VC5A VDD VC6 VC7 VC8 VC9 VC10 GND SEL0
225/25V
Zener R21
R20
U1 VDD1 SEL2 SEL1 CTLD CHSE VM CHG DSG DSD CDC RS2 RS1 TS DS
1K
104/25V
1 2 3 4 5 6 7 8 9 10 11 12 13 14
R19
C8
103/25V
104/25V
1K
C7
C15
1K 3M 1M
1K
GND
R9 R10 R11
103AT
VDD
1K
R18
VC5A
R7
C1
R1 R2 R3 R4 R5 R6
11 10 9 8 7 6 5 4 3 2 1 CELL
U2
R22 0.003
CURRENT
GND Figure 18 SH367007 Power consumption test circuit diagram
Zener
225/25V
104/25V
104/25V
104/25V
104/25V
104/25V
C1
C2
C3
C4
C5
C6
104/25V
104/25V
104/25V
104/25V
C11
C12
C13
C14
225/25V
104/25V
twenty one
100R D1 1K 1K 1K 1K 1K
R7
100R
Schottky
J1
R10 R12 R13 R15 R17 R18
100R 1K 1K 1K 1K 1K
R19
100R
D3
Schottky
GND
104/25V
104/25V
104/25V C20
R20 R21 R22 R23 R24 R25
100R 1K 1K 1K 1K 1K
D5
Schottky
U2
R30 0.003
CURRENT
GND
Figure 19 SH3 67008 power consumption test circuit diagram
twenty four
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CELL
VC10A
C19
1K R29
twenty two
20
C18
103AT R28
twenty three
104/25V
103/25V C21
twenty four
C17
1K R27
R26
1K
SH367008
VDD
C10
104/25V
C9
104/25V
C8
104/25V
C7
225/25V
3M 1M
C16
R14 R16
C15
1K 1K
R1 R2 R3 R4 R5 R6
VC5A
Zener
R9 R11
38 37 36 35 34 33 32 31 30 29 28 27 26 25
D4
GND
1K
VC2 VC3 VC4 VC5 VC5A VDD1 VC6 VC7 VC8 VC9 VC10 VC10A VDD VC11 VC12 VC13 VC14 VC15 GND
Zener
VC10A VDD
R8
U1 V C1 VDD2 NC SEL3 NC SEL2 SEL1 CTLD CHSE VM CHG DSG DSD CDC RS2 RS1 TS DS SEL0
D6
VC5A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
D2
8.9 SH367008 Power consumption test chart
Preliminary 9
SH367005/
005S/007/008 series lithium battery PACK protection chip
Electrical characteristics
9.1 Limit parameters 9.1.1 SH367005 Limit parameter table Signal name
Limit range
Pin name
VDD
High voltage input
Low voltage input
DSG/VC1~VC5/CTL/SEL0 /CHSE VM/CHG RS1/ RS2/CDC/DSD/TS/DS
unit
GND‑0.3 to GND+26
V
GND‑0.3 to VDD+0.3
V
VDD‑26 to VDD+0.3 GND‑0.3 to 5.5
V V
Operating temperature
‑
‑40 to 85
° C
storage temperature
‑
‑40 to 125
° C
9.1.2 SH367005S Limit parameter table Signal name
Limit range
Pin name
VDD
High voltage input
Low voltage input
DSG/VC1~VC5/CTLD/SEL0 /SEL1/CHSE VM/CHG RS1/ RS2/CDC/DSD/TS/DS
unit
GND‑0.3 to GND+26
V
GND‑0.3 to VDD+0.3
V
VDD‑26 to VDD+0.3 GND‑0.3 to 5.5
V V
Operating temperature
‑
‑40 to 85
° C
storage temperature
‑
‑40 to 125
° C
9.1.3 SH367007 Limit parameter table Signal name
Limit range
Pin name
VDD1 VC5A VDD
High voltage input
Low voltage input
VC1~VC5/SEL2 DSG/VC6~VC10/CTLD/SEL0 /SEL1/CHSE VM/CHG RS1/ RS2/CDC/DSD/TS/DS
unit
VC5A‑0.3 to VC5A+26 GND‑0.3 to GND+26 GND‑0.3 to GND+26 VC5A‑0.3 to VDD1+0.3
V V V V
GND‑0.3 to VDD+0.3
V
VDD‑26 to VDD+0.3 GND‑0.3 to 5.5
V V
Operating temperature
‑
‑40 to 85
° C
storage temperature
‑
‑40 to 125
° C
9.1.4 SH367008 Limit parameter table Signal name
Limit range
Pin name
VDD2 VC5A VDD1
VC10A High voltage input
Low voltage input
VDD
VC1~VC5/SEL3 VC6~VC10/SEL2 DSG/VC11~VC15/CTL/SEL0 /SEL1/CHSE VM/CHG RS1/ RS2/CDC/DSD/TS/DS
unit
VC5A‑0.3 to VC10A+26 VC10A‑0..3 to VC10A+26 VC10A‑0..3 to VC10A+26 GND‑0.3 to GND+26 GND‑0.3 to GND+26 VC10A‑0.3 to VDD2+0.3 VC5A‑0.3 to VDD1+0.3
V V V V V V V
GND‑0.3 to VDD+0.3
V
VDD‑26 to VDD+0.3 GND‑0.3 to 5.5
V V
Operating temperature
‑
‑40 to 85
° C
storage temperature
‑
‑40 to 125
° C
Note 12: If the working condition of the device exceeds
pass " Limit parameters " The range will cause permanent damage to the device. The function of the device can only be guaranteed if it works within the scope specified in the manual.
Note 13:‑ 0.3V=11V, DSG catch 10nF capacitance
V DSG‑2
DSG Pin high level output
VDD‑2
VDD‑1
‑
V
VDD=11V, CHG catch 1M resistance
V CHG‑2
CHG Pin high level output
VDD‑2
VDD‑1
‑
V
VDD=11V, DSG catch 10nF capacitance
VDD‑2
VDD‑1
‑
V
VDD=11V, CHG catch 1M resistance
VDD‑2
VDD‑1
‑
V
VDD