Schematics Foxcom H61MD - HW-20130125 [PDF]
3 1 Block Diagram 2 Clock Distribution 3 Power Delivery Map 4 Power On Sequence 5 Reset/power good 6 STRAP
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3
1
Block Diagram
2
Clock Distribution
3
Power Delivery Map
4
Power On Sequence
5
Reset/power good
6
STRAP
7
CPU 1-6
8-13
DDR3-1:CHA
14
DDR3-2:CHB
15
PCIE X16
16
PCH 1-7
17-24
VGA
25
HDMI blank
26
PCIE 1X
27
AUDIO-1:ALC662-VD0-GR
28
AUDIO-2:CONNECTOR
29
LAN RTL8111F/RTL8105E
30
LAN/USB Connector4-5
31
Front USB2.0 Header
32
Super I/O IT8772
33
PS2/FAN
34
TPM/debug
35
H61M09
CPU: Supports LGA1155 for Intel Ivy/Sandybridge series CPU System Chipset: PCH Main Memory: Dual Channel / DDR-III * 2 On Board Device: SIO: IT8772E/FX LAN: Realtek, RTL8111F/RTL8105E
1D5V_STR
39
CPU_VCCIO blank
40
VCORE/AXG PWM
41
rC H61MD
with GigaLan
H61MD-V
with 10/100 Lan
H61MD G3
with GigaLan/com header, G3 BIOS
B
42
VCORE/AXG DRIVER
43
THROUGH HOLE
44
CM
S
USB3 blank USB PORT blank
te
38
Expansion Slots: PCI EXPRESS 16X SLOT *1 PCI EXPRESS 1X SLOT * 2
pu
5V_DUAL/3.3V_SB/3.3V_DUAL
C
HDA Codec: Realtek, ALC662-VD0-GR BIOS:SPI Flash ROM 4Mbyte
m
37
D
Co
B
36
1D05/1D8V/VCCSA
FAB A mATX form factor 7.5 inch x 6.7 inch
C
ATX CONN/FP PANEL/RSMRST
1
Lt d.
Cover Sheet
2
ny
D
4
om pa
5
45
A
A
FOXCONN PCEG Title
Cover Sheet Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
1
of
45
5
4
3
2
1
BLOCK DIAGRAM
D
D
CHANNEL A DDR3 SDRAM (800/1066/1333)
POWER SUPPLY CONNECTOR
VREG VRD12
DDR3 SDRAM CONN x1
INTEL PROCESSOR Sandy Bridge LGA1155
CHANNEL B DDR3 SDRAM (800/1066/1333)
DDR3 SDRAM CONN x1 PCIE GEN2 x16
FDI
DMI
INTEL PCH
VGA
VGA
USB
LAN
RTL8111F/RTL8105E 10/100/1000
om pa
C
ny
PCI EXPRESS (lane 2)
PCI EXPRESS (lane 1)
PCIE X1
Lt d.
PCIE (GEN 2)
USB
C
REAR*4 / FRONT*4
HDA Link
LPC I/F
te
SPI I/F
ALC662
rC
SATA
AUDIOCODEC
SPI
m
pu
SATA 2.0 (4 PORTS)
COM
SIO IT8772E/FX
KB&MS B
CM
S
Co
B
A
A
FOXCONN PCEG Title
Block Diagram Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
2
of
45
5
4
REFCLK14IN
CLKIN_BCLK
CLKIN_DOT_96 (FOR USB)
CLKIN_SATA
PCH_CLK_DMI
D
3
2
1
CPU CLKOUT_DMI_P/N
BCLK_P/N D
CLKOUT_ITPXDP_P/N
LAN PCIE 100M
CLKOUT_PCIE3_P/N
PCIE X1
PCIE 100M
CLK_P/N
om pa
C
PCICLKIN
CLKOUT_PEG_A_P/N
PCH
PCICLK2
ny
CLKOUT_PCIE4_P/N
CLKOUT_PCIE5_P/N
REFCLK_P/N
Lt d.
CLKOUT_PCIE0_P/N
C
PCIE X16
PCIE 100M
CLK_P/N
48M
rC
CLKOUTFLEX3 Buffer Through Mode FCI Mode
te
25MHZ X'TAL
m
pu
CLKOUT_PCI0
CM
SIO
33M
PCICLK
TPM
33M CLKOUT_PCI4
PCICLK B
REFCLK14IN
GND
CLKIN_DMI_P/N
GND
CLKIN_DOT_96P/N
GND
CLKIN_SATA_P/N
GND
S
Co
B
SIO_48M
32.768KHZ X'TAL
A
A
FOXCONN PCEG Title
Clock Distribution Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
3
of
45
5
4
3
SYS/CPU
POWER DELIVERY MAP
2.4A
2
1
FAN
434969
12V 1.2A*2
Sandy-Bridge(65W) CPU POWER
ATX -12V_SYS12V_SYS 3D3V_SYS 5V_SYS 5VSB_SYS D
+/- 5%
+/- 5%
+/- 5%
+/- 5%
75A
RT8876A Icc=55A Max=75A
35A
SWITCHING Icc=25A Max=35A
+12V_CPU
+/- 5%
V_CPU_CORE
V_CPU_CORE(CPU Vcore) Voltage=1.1V Icc(Max)=55A Max=75A 2-Phases Swithing
+/- 5%
V_1D1V_AXG
DDR3(2 DIMM) V_SM=1.5V to 3D3V_SB AZ1084D
V_SM(DDR III) VDDQ Voltage=1.5V Icc=4.75A
4A
SWITCHING 3D3V_DUAL
1.326A
V_VCCSA(0.925/0.85V VCCSA IccMax=8.8A
V_SM_VTT=0.75V 1A 0.903A
SWITCHING V_SM 5.2A
0.5A
om pa
SWITCHING V_1D05V_CPU
C
SWITCHING V_1D8V_SFR
1.859A
VCCCORE(V_1D05V_PCH) Voltage=1.05V Icc(Max)=6.2A C
SWITCHING V_1D05V_PCH
VCCIO Voltage=1.05V Icc(Max)=1.8A
8.2A 1.5A
VccADPLL 0.2A
0.359A
VCCDMI
VCCVRM=1.8V
0.153A
0.123A 0.477A
0.003A
RTC Battery
0.04A
5.5A
0.05A
0.5A
0.375A
+12V_SYS=5.5A
A
3D3V_SYS
PCI Express X1
3A
VCCRTC
0.0022A
5A
SIO IT8772
0.2A
3D3V_SB Icc=50mA(S0)
+3V_PCIAUX(3D3V_DUAL) Icc(Max)=0.375A(S0) Icc(Max)=0.02A(S3~S5)
3D3V_SB Icc=38mA(S3)
3D3V_SYS Icc=3A
HDA Codec 5V_DUAL Voltage=5V Icc=200mA
3D3V_SYS Icc=50mA
+12V_SYS Icc=0.5A
3D3V_DUAL Icc(Max)=0.375A(wake) Icc(Max)=0.02A(no wake)
VccSPI=3.3V 0.02A
0.375A
0.05A
PCI Express X16
VccDSW3_3=3.3V 0.003A
S
3A
CM
3A
VccSusHDA=3.3V 0.01A B
0.02A
Co
0.42A
0.01A
m
B
0.409A
VccADAC=3.3V 0.068A
0.75A
6A
0.159A
VCCSUS3_3 0.123A 3D3V_SYS
pu
0.477A 6.09A
0.0655A
VccDFTERM=1.8V 0.2A
te
6.567A
1.5A
Cougar_Point(5.5W) 17.3655A
rC
1.859A
V_1D8V_SFR(1.8V VCCPLL)
SWITCHING V_SM_VTT
ny
1A
VGA 5V_SYS
V_1D05V_CPU(1.1/1.05V VCCIO) IccMax=8.5A
8.75A
35.3155A
0.5A
Lt d.
0.423A
SWITCHING 5V_DUAL
D
V_1D1V_AXG(VCCAXG) Voltage=1.1V Icc=25A Max=35A
0.37A
RTL8111F GbE Lan / RTL8105E 100M
PS2
5V_DUAL=500mA(S0, S1) 5V_DUAL=2mA(S3)
3D3V_SB 370mA
3D3V_SYS Voltage=3.3V Icc=40mA
USB2.0
A
8 Ports
5V_DUAL=4A(S0, S1) 5V_DUAL=0.1A(S3)
FOXCONN PCEG Title
Power Delivery Map Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
4
of
45
5
4
3
2
1
POWER ON SEQUENCE
D
om pa
ny
Lt d.
D
C
pu
te
rC
C
B
CM
S
Co
m
B
A
A
FOXCONN PCEG Title
Power On Sequence Size Document Number Custom Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
1
Rev 2.0
H61M09
Friday, January 25, 2013
Sheet
5
of
45
4
3
(2) (3) D
(4) (5) (6) (7) (8) (9) (10) (11) (12)
O_PWRBTN#IN S_SLP_S4# S_SLP_S3# S_SLP_M# O_PSON# B_ATX_PWROK PCH_MEPWRGD S_PCH_SYSPWROK P_VR_READY PWRGD_3V H_DRAMPWRGD D3_RESET# H_PWRGD S_PLTRST# H_RESET#_R S_PLTRST#_R X_PLTRST_PCIE_SLOT# K_PCIRST#_SLOT A_Z_RST#
1
SM_DRAMRST*
(1)
RESET*
Sequence Signal Name:
SM_DRAMPWROK
RESET / Power Good MAP
2
CPU-Sandy Bridge
UNCOREPWRGOOD
5
D
(10) (8) Buffer (UH2)
Front Panel
DDRIII Slots D3_RESET#
FR_RST PWRBTN# 5V_SB
Lt d.
3D3V_SB
(8)
SLP_S4#
C
SLP_S3#
PCH
PLTRST#
HDA_RST#
(A2)
PWRBTN#
(2)
PCIRST3#
PCI-E 16x Slot
(11)
C
PWRGD
PCI-E 1x Slot1
(11)
PWRGD
PWR_GOOD_3V
ATX Power (4)
PS_ON# PWRON
ATXPWRGD
(5)
PSON PWROK
PWR_GOOD_3V
m
PWROK
> 1ms
PWRGD_PS
B
100~120ms
CM
S
Co
B
PERST#
SIO-IT8772F/EX
RSMRST#
(6)
APWROK
PROCPWRGD
LRESET#
te
SYS_PWROK
PCIRST1#
LAN
(11)
SLP_S3#
(9)
pu
VR_RDY
SLP_S4_S5#
(3)
PWROK (9)
PCIRST#
VRD 12
PANSWH#
PCIRST0#
(3)
RSMRST#
ny
DRAMPWROK
(1) (7)
om pa
RESET#
(12)
3VSB
SYS_RESET#
rC
HD Audio
PROCPWRGD
(A1)
A
A
FOXCONN PCEG Title
Reset/power good Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
6
of
45
5
4
3
2
1
IRQ Routing Table INTA#
INTB#
A
B
INTA#
INTB#
Slot1
INTC# C
INTD# D
IDSEL 16
REQn#
GNTn#
0
0
REQn#
GNTn#
2
2
D
D
Slot2
B
C
INTC#
INTD#
D
A
IDSEL 17
STRAPPING Table CFG[17:0]
Lt d.
CPU side Description
[2]
PCI Express static x16 lane numbering reversal
[6:5]
PCI Express Bifurcation
1: normal Default 0: lane numbers reversed
ny
00: 1x8, 2x4 PCI Express 01: reserved
om pa
10: 2x8 PCI Express 11: 1x16 PCI Express Default
C
m
pu
te
rC
C
B
CM
S
Co
B
A
A
FOXCONN PCEG Title
STRAP Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
7
of
45
5
4
3
2
1
D
D
?
Place R216 & R213 near CPU
SKT_H2
U1E
R213 *R216 110Ohm *75
AJ33 K32
TP37
PROC_SEL DMI/FDI TERMINATION VOLTAGE DC COUPLED: TX/RX TO VCC ISF SAMPLED HIGH DC COUPLED: TX/RX TO VSS IF SAMPLED LOW AC COUPLED: TX SET TO VCC/2, RX SET TO VSS REGARDLESS OF THIS STRAP
AJ22
PRO_DDR_VREF
V_NAND_IO
CFG0 CFG1 CFG2 CFG3 CFG4 SWITCH_SEL_CPU CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 TPEV_SNB_PCUSTB_0 TPEV_SNB_PCUSTB_1
TP1 TP2 TP3 TP4 TP5
C
*R559 2.2KOhm *
+/-1% Reserved r0402h4 R560 r0402h4
4.7KOhm +/-1% Reserved
NVR_CLE
TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP25 TP26
21
For future processor compatibility
H36 J36 J37 K36 L36 N35 L37 M36 J38 L35 M38 N36 N38 N39 N37 N40 G37 G36 AT14
H7 H8
V_SM
V_NAND_IO
m
V_1D8V_SFR
+/-1% Reserved PRO_DDR_VREF
*R382 100 Ohm * +/-1% Reserved
C437 0.1uF 16V, X7R, +/-10% Reserved
Co
B
TDO TDI TCK TMS TRST# PRDY# PREQ# DBR# BCLK_ITP BCLK_ITP#
SKTOCC# FC_K32 SM_VREF
CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]
BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]
RSVD34 RSVD35 RSVD36 RSVD37 RSVD38
S
V_1D05V_CPU
PLACE TDO TERMINATION NEAR XDP CONNECTOR
*R211 1K
*R212 1K
+/-1% r0402h4 DummyPCH_THERMTRIP_N H_CATERR_N
+/-1% r0402h4
+/-1% r0402h4
+/-1% r0402h4
Dummy
Dummy
Dummy
DEFENSIVE SITE
CM
*R215 1K
PCH_PECI H_PWRGD
R212应为51欧(CRB1.1)
RSVD41 RSVD42
RSVD31
RSVD43 RSVD44 RSVD45
RSVD32 RSVD33
AB4 AB3
VCCP_SENSE VSSP_SENSE
L32 M32
VCCAXG_SENSE VSSAXG_SENSE
L39 L40 M40 L38 J39 K38 K40 E39 C40 D40
H_TDO H_TDI H_TCK H_TMS H_TRST_N H_PRDY_N
H_VCC_SENSE H_VSS_SENSE
37
41 41
H_VCCIO_SENSE H_VSSIO_SENSE
37 37
H_VCCAGX_SENSE H_VSSAGX_SENSE
41 41
H_DBR_N
TP42
H40 H38 G38 G40 G39 F38 E40 F40
C
B39 J33 L34 L33 K34
N33 M34
AV1 AW2 L9 J9 K9
L31 RSVD46 J31 VCC_VALIDATION_SENSE K31 VSSU_VALIDATION_SENSE V_1D05V_PCH 3D3V_DUAL
AD34 VCCAXG_VALIDATION_SENSE AD35 VSSGT_VALIDATION_SENSE
3D3V_SYS
RN59拆分成单颗电阻 H61MD 1128 R1225电由V_1D05V_CPU改为V_1D05V_PCH,方便layout 1207
MISC
*R1225
5 OF 11 CPU_SKT_H2
*R1226 *R1227
10K +/-5% r0402h4 Reserved
? V_1D05V_CPU
10K +/-5% r0402h4 Reserved
B
10K +/-5% r0402h4 Reserved VCCIO_SELECT
RN39
*1
H_TDI H_TDO H_TMS H_TCK
51 8p4r0402h6
PLACE TRST* TERMINATION ANYWHERE ON ROUTE.
*1 3 5 7
51 8p4r0402h6
4.7KOhm +/-1% Reserved
Q42
G
+/-5% Reserved
Q40
RN40
H_TRST_N H_PROCHOT_N H_PRDY_N
R300 r0402h4
CPU_RST_N
2 4 6 8
3 5 7
TERMINATION IDEALLY TO BE PLACED PLACE CLOSE TO EACH OTHER TO REDUCE STUB NEXT TO IT OR WITHIN 1.5 OF CPU.
*R234 51
RSVD39 RSVD40
RSVD30
pu
PLACE R381, R382,C437 IN SOCKET CAVITY
*R381 100 Ohm
PM_SYNC PECI CATERR# PROCHOT# THERMTRIP#
te
AY3
VSSAXG_SENSE VSSAXG_SENSE
VCC_SENSE VSS_SENSE
*
H_PROCHOT_N PCH_THERMTRIP_N
41 H_PROCHOT_N PCH_THERMTRIP_N
E38 J35 E37 H34 G35
VCCIO_SENSE VSSIO_SENSE
UNCOREPWRGOOD SM_DRAMPWROK RESET#
TP40 TP41 H_VCCSA_SENSE
A36 B36
D
H_CATERR_N
VCC_SENSE VSS_SENSE
P33 VCCIO_SELECT P34 VCCSA_VIO_0 T2 VCCSA_SENSE
S
19
PROC_SEL
H_PM_SYNC_0
H_PM_SYNC_0
PCH_PECI
VCCIO_SELECT VCCSA_VID_0 VCCSA_SENSE
VIDSCLK VIDSOUT VIDALERT#
D
19 19,33
J40 124 +/-1% Reserved AJ19 F36 CPU_RST_N
H_PWRGD R666
20 H_PWRGD H_DRAMPWRGD
20
*
MINIMIZE STUB BETWEEN THESE AND RESISTORS AT SINAI PAGE PLACE IN CRB AREA
BCLK[0] BCLK#[0]
20,33
2 4 6 8
PLTRST_N
2N7002 Reserved sot23_gsdh11
G S
VIDALERT_N
C37 B37 A37
Lt d.
W2 W1
C_CPU_CLK_DP C_CPU_CLK_DN
om pa
+/-1% 22 r0402h4 22 Reserved
41 H_VIDSCK_VR 41 H_VIDSOUT_VR 41 H_VIDALERT_N_VR
rC
+/-1% r0402h4 Reserved
REV = 4 BALLMAP_REV = 1.6
ny
V_1D05V_CPU
2N7002 Reserved sot23_gsdh11
+/-5% Reserved
H61M09 1127
Need to be double checked.
A
A
V_1D05V_CPU
*R296 10K r0402h4 Dummy Need check the power and the value of R221 according to the latest CPU datasheet
FOXCONN PCEG Title
CPU1-MSIC
SWITCH_SEL_CPU Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
8
of
45
5
4
3
2
1
D
D
?
SKT_H2
V_CPU_VCCIO
R194 r0402h4
*
24.9 +/-1% Reserved
GRCOM
B5 C4 B4
PEG_ICOMPO PEG_RCOMPO PEG_ICOMPI CPU_SKT_H2
?
Short B4 & C4 together, route as a single 4 mil trace 3 to R2 OF 11 Route B5 to R2 as a aeperate 10 mil trace
Lt d. ny
H_FDI_FSYNC1_1 H_FDI_LSYNC1_1
V_CPU_VCCIO
21
AE5 AE4
AG3
H_FDI_INT_1
*
om pa V_1D05V_CPU
18 18 18 18 18 18 18 18
21 21
AC5 AC4
R374 r0402h4
AE2 AE1
24.9 +/-1% Reserved
SKT_H2
REV = 4 BALLMAP_REV = 1.6
FDI_FSYNC_0 FDI_LSYNC_0
FDI_TX[0]
AC8 AC7 AC2 AC3 AD2 AD1 AD4 AD3
FDI_TX[0] FDI_TX#[0] FDI_TX[1] FDI_TX#[1] FDI_TX[2] FDI_TX#[2] FDI_TX[3] FDI_TX#[3]
AD7 AD6 AE7 AE8 AF3 AF2 AG2 AG1
FDI_TX[4] FDI_TX#[4] FDI_TX[5] FDI_TX#[5] FDI_TX[6] FDI_TX#[6] FDI_TX[7] FDI_TX#[7]
FDI_LSYNC_1 FDI_FSYNC_1
FDI_INT
H_FDI_TX_DP0 H_FDI_TX_DN0 H_FDI_TX_DP1 H_FDI_TX_DN1 H_FDI_TX_DP2 H_FDI_TX_DN2 H_FDI_TX_DP3 H_FDI_TX_DN3
21 21 21 21 21 21 21 21
H_FDI_TX_DP4 H_FDI_TX_DN4 H_FDI_TX_DP5 H_FDI_TX_DN5 H_FDI_TX_DP6 H_FDI_TX_DN6 H_FDI_TX_DP7 H_FDI_TX_DN7
21 21 21 21 21 21 21 21
C
FDI LINK
FDI_COMPIO FDI_ICOMPO 4 OF 11 CPU_SKT_H2
?
DESIGN NOTE: N/T: PCIE X4 LANES ARE NOT SUPPORTED ON DESKTOP CPU SKUS
B
CM
S
Co
B
P8 P7 T7 T8 R6 R5 U5 U6
PE_TX[0] PE_TX#[0] PE_TX[1] PE_TX#[1] PE_TX[2] PE_TX#[2] PE_TX[3] PE_TX#[3]
H_DMI_TX_DP0 H_DMI_TX_DN0 H_DMI_TX_DP1 H_DMI_TX_DN1 H_DMI_TX_DP2 H_DMI_TX_DN2 H_DMI_TX_DP3 H_DMI_TX_DN3
H_FDI_FSYNC0_1 H_FDI_LSYNC0_1
rC
V_1D05V_CPU
PE_RX[0] PE_RX#[0] PE_RX[1] PE_RX#[1] PE_RX[2] PE_RX#[2] PE_RX[3] PE_RX#[3]
V7 V6 W7 W8 Y6 Y7 AA7 AA8
DMI_TX[0] DMI_TX#[0] DMI_TX[1] DMI_TX#[1] DMI_TX[2] DMI_TX#[2] DMI_TX[3] DMI_TX#[3]
21 21
?
U1D
te
P3 P4 R2 R1 T4 T3 U2 U1
DMI_RX[0] DMI_RX#[0] DMI_RX[1] DMI_RX#[1] DMI_RX[2] DMI_RX#[2] DMI_RX_3 DMI_RX#[3]
X_1X16_TXP0 16 X_1X16_TXN0 16 X_1X16_TXP1 16 X_1X16_TXN1 16 X_1X16_TXP2 16 X_1X16_TXN2 16 X_1X16_TXP3 16 X_1X16_TXN3 16 X_1X16_TXP4 16 X_1X16_TXN4 16 X_1X16_TXP5 16 X_1X16_TXN5 16 X_1X16_TXP6 16 X_1X16_TXN6 16 X_1X16_TXP7 16 X_1X16_TXN7 16 X_1X16_TXP8 16 X_1X16_TXN8 16 X_1X16_TXP9 16 X_1X16_TXN9 16 X_1X16_TXP10 16 X_1X16_TXN10 16 X_1X16_TXP11 16 X_1X16_TXN11 16 X_1X16_TXP12 16 X_1X16_TXN12 16 X_1X16_TXP13 16 X_1X16_TXN13 16 X_1X16_TXP14 16 X_1X16_TXN14 16 X_1X16_TXP15 16 X_1X16_TXN15 16
pu
W5 W4 V3 V4 Y3 Y4 AA4 AA5
H_DMI_RX_DP0 H_DMI_RX_DN0 H_DMI_RX_DP1 H_DMI_RX_DN1 H_DMI_RX_DP2 H_DMI_RX_DN2 H_DMI_RX_DP3 H_DMI_RX_DN3
C13 X_1X16_TXP0 C14 X_1X16_TXN0 E14 X_1X16_TXP1 E13 X_1X16_TXN1 G14 X_1X16_TXP2 G13 X_1X16_TXN2 F12 X_1X16_TXP3 F11 X_1X16_TXN3 J14 X_1X16_TXP4 J13 X_1X16_TXN4 D8 X_1X16_TXP5 D7 X_1X16_TXN5 D3 X_1X16_TXP6 C3 X_1X16_TXN6 E6 X_1X16_TXP7 E5 X_1X16_TXN7 F8 X_1X16_TXP8 F7 X_1X16_TXN8 G10 X_1X16_TXP9 G9 X_1X16_TXN9 G5 X_1X16_TXP10 G6 X_1X16_TXN10 K7 X_1X16_TXP11 K8 X_1X16_TXN11 J5 X_1X16_TXP12 J6 X_1X16_TXN12 M8 X_1X16_TXP13 M7 X_1X16_TXN13 L6 X_1X16_TXP14 L5 X_1X16_TXN14 N5 X_1X16_TXP15 N6 X_1X16_TXN15
PEG_TX[0] PEG_TX#[0] PEG_TX[1] PEG_TX#[1] PEG_TX[2] PEG_TX#[2] PEG_TX[3] PEG_TX#[3] PEG_TX[4] PEG_TX#[4] PEG_TX[5] PEG_TX#[5] PEG_TX[6] PEG_TX#[6] PEG_TX[7] PEG_TX#[7] PEG_TX[8] PEG_TX#[8] PEG_TX[9] PEG_TX#[9] PEG_TX[10] PEG_TX#[10] PEG_TX[11] PEG_TX#[11] PEG_TX[12] PEG_TX#[12] PEG_TX[13] PEG_TX#[13] PEG_TX[14] PEG_TX#[14] PEG_TX[15] PEG_TX#[15]
m
18 18 18 18 18 18 18 18
PEG_RX[0] PEG_RX#[0] PEG_RX[1] PEG_RX#[1] PEG_RX[2] PEG_RX#[2] PEG_RX[3] PEG_RX#[3] PEG_RX[4] PEG_RX#[4] PEG_RX[5] PEG_RX#[5] PEG_RX[6] PEG_RX#[6] PEG_RX[7] PEG_RX#[7] PEG_RX[8] PEG_RX#[8] PEG_RX[9] PEG_RX#[9] PEG_RX[10] PEG_RX#[10] PEG_RX[11] PEG_RX#[11] PEG_RX[12] PEG_RX#[12] PEG_RX[13] PEG_RX#[13] PEG_RX[14] PEG_RX#[14] PEG_RX[15] PEG_RX#[15]
DMI
C
X_1X16_RXP0 X_1X16_RXN0 X_1X16_RXP1 X_1X16_RXN1 X_1X16_RXP2 X_1X16_RXN2 X_1X16_RXP3 X_1X16_RXN3 X_1X16_RXP4 X_1X16_RXN4 X_1X16_RXP5 X_1X16_RXN5 X_1X16_RXP6 X_1X16_RXN6 X_1X16_RXP7 X_1X16_RXN7 X_1X16_RXP8 X_1X16_RXN8 X_1X16_RXP9 X_1X16_RXN9 X_1X16_RXP10 X_1X16_RXN10 X_1X16_RXP11 X_1X16_RXN11 X_1X16_RXP12 X_1X16_RXN12 X_1X16_RXP13 X_1X16_RXN13 X_1X16_RXP14 X_1X16_RXN14 X_1X16_RXP15 X_1X16_RXN15
GEN
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
REV = 4 BALLMAP_REV = 1.6
PEG
U1C X_1X16_RXP0 B11 X_1X16_RXN0 B12 X_1X16_RXP1 D12 X_1X16_RXN1 D11 X_1X16_RXP2 C10 X_1X16_RXN2 C9 X_1X16_RXP3 E10 X_1X16_RXN3 E9 X_1X16_RXP4 B8 X_1X16_RXN4 B7 X_1X16_RXP5 C6 X_1X16_RXN5 C5 X_1X16_RXP6 A5 X_1X16_RXN6 A6 X_1X16_RXP7 E2 X_1X16_RXN7 E1 X_1X16_RXP8 F4 X_1X16_RXN8 F3 X_1X16_RXP9 G2 X_1X16_RXN9 G1 X_1X16_RXP10 H3 X_1X16_RXN10 H4 X_1X16_RXP11 J1 X_1X16_RXN11 J2 X_1X16_RXP12 K3 X_1X16_RXN12 K4 X_1X16_RXP13 L1 X_1X16_RXN13 L2 X_1X16_RXP14 M3 X_1X16_RXN14 M4 X_1X16_RXP15 N1 X_1X16_RXN15 N2
A
A
FOXCONN PCEG Title
CPU2-PEG/DMI/FDI Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
9
of
45
5
4
3
2
1
D
D
14
D3_DATA_A[63..0]
? SKT_H2
14 14 14 14 14 14 14 14
D3_DQS_A_DN0 D3_DQS_A_DN1 D3_DQS_A_DN2 D3_DQS_A_DN3 D3_DQS_A_DN4 D3_DQS_A_DN5 D3_DQS_A_DN6 D3_DQS_A_DN7
AK3 AP3 AW4 AV8 AV37 AP38 AK38 AF38
Co
D3_DQS_A_DP0 D3_DQS_A_DP1 D3_DQS_A_DP2 D3_DQS_A_DP3 D3_DQS_A_DP4 D3_DQS_A_DP5 D3_DQS_A_DP6 D3_DQS_A_DP7
S
14 14 14 14 14 14 14 14
CM
B
U1A
SA_WE# SA_CAS# SA_RAS# SA_BS_0 SA_BS[1] SA_BS[2]
D3_MAA_A0 D3_MAA_A1 D3_MAA_A2 D3_MAA_A3 D3_MAA_A4 D3_MAA_A5 D3_MAA_A6 D3_MAA_A7 D3_MAA_A8 D3_MAA_A9 D3_MAA_A10 D3_MAA_A11 D3_MAA_A12 D3_MAA_A13 D3_MAA_A14 D3_MAA_A15
AW29 AV30 AU28
SA_CKE[0] SA_CKE[1] SA_CKE[3] SA_CKE[2]
rC
SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3]
SA_CK[0] SA_CK#[0] SA_CK[1] SA_CK#[1] SA_CK[2] SA_CK#[2] SA_CK[3] SA_CK#[3]
SM_DRAMRST#
D3_MAA_A[15..0]
AY29 AW28 AV20
D3_SBS_A0 D3_SBS_A1 D3_SBS_A2
AU29 AV32 AW30 AU33
D3_SCS_A_#0 D3_SCS_A_#1
AV19 AT19 AU18 AV18
D3_SCKE_A0 D3_SCKE_A1
AV31 AU32 AU30 AW33
D3_ODT_A0 D3_ODT_A1
AY25 AW25 AU24 AU25 AW27 AY27 AV26 AW26
14
D3_WE_A# 14 D3_CAS_A# 14 D3_RAS_A# 14
om pa
SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3]
AV27 AY24 AW24 AW23 AV23 AT24 AT23 AU22 AV22 AT22 AV28 AU21 AT21 AW32 AU20 AT20
Lt d.
SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]
D3_SBS_A[2..0]
ny
REV = 4 BALLMAP_REV = 1.6
te
SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]
m
C
AJ3 AJ4 AL3 AL4 AJ2 AJ1 AL2 AL1 AN1 AN4 AR3 AR4 AN2 AN3 AR2 AR1 AV2 AW3 AV5 AW5 AU2 AU3 AU5 AY5 AY7 AU7 AV9 AU9 AV7 AW7 AW9 AY9 AU35 AW37 AU39 AU36 AW35 AY36 AU38 AU37 AR40 AR37 AN38 AN37 AR39 AR38 AN39 AN40 AL40 AL37 AJ38 AJ37 AL39 AL38 AJ39 AJ40 AG40 AG37 AE38 AE37 AG39 AG38 AE39 AE40
D3_SCS_A_#0 D3_SCS_A_#1
14 14
D3_SCKE_A0 D3_SCKE_A1
14 14
D3_ODT_A0 D3_ODT_A1
14 14
D3_CK_DDR_A_DP0 D3_CK_DDR_A_DN0 D3_CK_DDR_A_DP1 D3_CK_DDR_A_DN1
AW18
14
C
14 14 14 14
D3_DRAMRST#
14,15
pu
D3_DATA_A0 D3_DATA_A1 D3_DATA_A2 D3_DATA_A3 D3_DATA_A4 D3_DATA_A5 D3_DATA_A6 D3_DATA_A7 D3_DATA_A8 D3_DATA_A9 D3_DATA_A10 D3_DATA_A11 D3_DATA_A12 D3_DATA_A13 D3_DATA_A14 D3_DATA_A15 D3_DATA_A16 D3_DATA_A17 D3_DATA_A18 D3_DATA_A19 D3_DATA_A20 D3_DATA_A21 D3_DATA_A22 D3_DATA_A23 D3_DATA_A24 D3_DATA_A25 D3_DATA_A26 D3_DATA_A27 D3_DATA_A28 D3_DATA_A29 D3_DATA_A30 D3_DATA_A31 D3_DATA_A32 D3_DATA_A33 D3_DATA_A34 D3_DATA_A35 D3_DATA_A36 D3_DATA_A37 D3_DATA_A38 D3_DATA_A39 D3_DATA_A40 D3_DATA_A41 D3_DATA_A42 D3_DATA_A43 D3_DATA_A44 D3_DATA_A45 D3_DATA_A46 D3_DATA_A47 D3_DATA_A48 D3_DATA_A49 D3_DATA_A50 D3_DATA_A51 D3_DATA_A52 D3_DATA_A53 D3_DATA_A54 D3_DATA_A55 D3_DATA_A56 D3_DATA_A57 D3_DATA_A58 D3_DATA_A59 D3_DATA_A60 D3_DATA_A61 D3_DATA_A62 D3_DATA_A63
AK2 AP2 AV4 AW8 AV36 AP39 AK39 AF39
SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]
SA_DQS[8] SA_DQS#[8] SA_ECC_CB[0] SA_ECC_CB[1] SA_ECC_CB[2] SA_ECC_CB[3] SA_ECC_CB[4] SA_ECC_CB[5] SA_ECC_CB[6] SA_ECC_CB[7]
SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]
AV13 AV12 AU12 AU14 AW13 AY13 AU13 AU11 AY12 AW12
B
DDR ECC IS NOT SUPPORTED ON DESKTOP SKUS ECC TRACES ARE FOR ENGINEERING FUNCTION ONLY DESIGN NOTE:
DDR_A
1 OF 11 CPU_SKT_H2
?
A
A
FOXCONN PCEG Title
CPU3-DDR3_CHA Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
10
of
45
5
4
3
2
1
D
D
15
D3_DATA_B[63..0] ?
SKT_H2
D3_DQS_B_DN0 D3_DQS_B_DN1 D3_DQS_B_DN2 D3_DQS_B_DN3 D3_DQS_B_DN4 D3_DQS_B_DN5 D3_DQS_B_DN6 D3_DQS_B_DN7
AH6 AL8 AP8 AN12 AN28 AR33 AM33 AG34
SB_WE# SB_CAS# SB_RAS# SB_BS[0] SB_BS[1] SB_BS[2]
AR25 AK25 AP24 AP23 AM24 AW17
SB_CKE[0] SB_CKE[1] SB_CKE[2] SB_CKE[3]
SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3]
D3_MAA_B[15..0]
D3_MAA_B0 D3_MAA_B1 D3_MAA_B2 D3_MAA_B3 D3_MAA_B4 D3_MAA_B5 D3_MAA_B6 D3_MAA_B7 D3_MAA_B8 D3_MAA_B9 D3_MAA_B10 D3_MAA_B11 D3_MAA_B12 D3_MAA_B13 D3_MAA_B14 D3_MAA_B15
15 15
AU16 AY15 AW15 AV15
D3_SCKE_B0 D3_SCKE_B1
15 15
AL26 AP26 AM26 AK26
D3_ODT_B0 D3_ODT_B1
AN25 AN26 AL25 AT26
15
D3_WE_B# 15 D3_CAS_B# 15 D3_RAS_B# 15 D3_SBS_B[2..0] 15
D3_SBS_B0 D3_SBS_B1 D3_SBS_B2 D3_SCS_B_#0 D3_SCS_B_#1
om pa
SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3]
AK24 AM20 AM19 AK18 AP19 AP18 AM18 AL18 AN18 AY17 AN23 AU17 AT18 AR26 AY16 AV16
Lt d.
SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]
ny
REV = 4 BALLMAP_REV = 1.6
D3_SCS_B_#0 D3_SCS_B_#1
D3_SCKE_B0 D3_SCKE_B1
D3_ODT_B0 D3_ODT_B1
15 15
C
rC
SB_CK[0]
SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]
SB_CK[0] SB_CK#[0] SB_CK[1] SB_CK#[1] SB_CK[2] SB_CK#[2] SB_CK[3] SB_CK#[3]
SB_DIMM_DQVREF SA_DIMM_DQVREF
D3_CK_DDR_B_DP0 D3_CK_DDR_B_DN0 D3_CK_DDR_B_DP1 D3_CK_DDR_B_DN1
AH1 AH4
15 15 15 15
DIMM_DQ_CPU_VREF_B DIMM_DQ_CPU_VREF_A
16V, +/-10% c0402h6 Reserved
SB_ECC_CB[0] SB_ECC_CB[1] SB_ECC_CB[2] SB_ECC_CB[3] SB_ECC_CB[4] SB_ECC_CB[5] SB_ECC_CB[6] SB_ECC_CB[7]
SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#7]
AL21 AL22 AL20 AK20 AL23 AM22 AP21 AN21
*C541 0.1uF
SB_DQS[8] SB_DQS#[8]
m
15 15 15 15 15 15 15 15
AH7 AM8 AR8 AN13 AN29 AP33 AL33 AG35
Co
D3_DQS_B_DP0 D3_DQS_B_DP1 D3_DQS_B_DP2 D3_DQS_B_DP3 D3_DQS_B_DP4 D3_DQS_B_DP5 D3_DQS_B_DP6 D3_DQS_B_DP7
S
15 15 15 15 15 15 15 15
CM
B
SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]
te
C
AG7 AG8 AJ9 AJ8 AG5 AG6 AJ6 AJ7 AL7 AM7 AM10 AL10 AL6 AM6 AL9 AM9 AP7 AR7 AP10 AR10 AP6 AR6 AP9 AR9 AM12 AM13 AR13 AP13 AL12 AL13 AR12 AP12 AR28 AR29 AL28 AL29 AP28 AP29 AM28 AM29 AP32 AP31 AP35 AP34 AR32 AR31 AR35 AR34 AM32 AM31 AL35 AL32 AM34 AL31 AM35 AL34 AH35 AH34 AE34 AE35 AJ35 AJ34 AF33 AF35
pu
D3_DATA_B0 D3_DATA_B1 D3_DATA_B2 D3_DATA_B3 D3_DATA_B4 D3_DATA_B5 D3_DATA_B6 D3_DATA_B7 D3_DATA_B8 D3_DATA_B9 D3_DATA_B10 D3_DATA_B11 D3_DATA_B12 D3_DATA_B13 D3_DATA_B14 D3_DATA_B15 D3_DATA_B16 D3_DATA_B17 D3_DATA_B18 D3_DATA_B19 D3_DATA_B20 D3_DATA_B21 D3_DATA_B22 D3_DATA_B23 D3_DATA_B24 D3_DATA_B25 D3_DATA_B26 D3_DATA_B27 D3_DATA_B28 D3_DATA_B29 D3_DATA_B30 D3_DATA_B31 D3_DATA_B32 D3_DATA_B33 D3_DATA_B34 D3_DATA_B35 D3_DATA_B36 D3_DATA_B37 D3_DATA_B38 D3_DATA_B39 D3_DATA_B40 D3_DATA_B41 D3_DATA_B42 D3_DATA_B43 D3_DATA_B44 D3_DATA_B45 D3_DATA_B46 D3_DATA_B47 D3_DATA_B48 D3_DATA_B49 D3_DATA_B50 D3_DATA_B51 D3_DATA_B52 D3_DATA_B53 D3_DATA_B54 D3_DATA_B55 D3_DATA_B56 D3_DATA_B57 D3_DATA_B58 D3_DATA_B59 D3_DATA_B60 D3_DATA_B61 D3_DATA_B62 D3_DATA_B63
U1B
AN16 AN15 AL16 AM16 AP16 AR16 AL15 AM15 AR15 AP15
15 14
*C540 0.1uF 16V, +/-10% c0402h6 Reserved
width 10mil
0.1uf 由Y5V改为X7R
spacing
12mil,near CPU
H61M09 20121121 B
DDR ECC IS NOT SUPPORTED ON DESKTOP SKUS ECC TRACES ARE FOR ENGINEERING FUNCTION ONLY DESIGN NOTE:
DDR_B
2 OF 11
CPU_SKT_H2
?
A
A
FOXCONN PCEG Title
CPU4-DDR3_CHB Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
11
of
45
5
4
3
2
1
V_CPU_CORE
? U1F SKT_H2 REV = 1.6
B
CPU POWER
6 OF 11 CPU_SKT_H2
V_SM D
?
SKT_H2
U1H
REV = 4 BALLMAP_REV = 1.6
M13 V_1D1V_AXG
U1G
SKT_H2?
REV = 4 BALLMAP_REV = 1.6
om pa
ny
Lt d.
VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG VCCAXG
te
rC
AB33 AB34 AB35 AB36 AB37 AB38 AB39 AB40 AC33 AC34 AC35 AC36 AC37 AC38 AC39 AC40 T33 T34 T35 T36 T37 T38 T39 T40 U33 U34 U35 U36 U37 U38 U39 U40 W33 W34 W35 W36 W37 W38 Y33 Y34 Y35 Y36 Y37 Y38
H10 H11 H12 J10 K10 K11 L11 L12 M10 M11 M12
V_VCCSA
GFX POWER
7 OF 11 CPU_SKT_H2
A11 A7 AA3 AB8 AF8 AG33 AJ16 AJ17 AJ26 AJ28 AJ32 AK15 AK17 AK19 AK21 AK23 AK27 AK29 AK30 B9 D10 D6 E3 E4 G3 G4 J3 J4 J7 J8 L3 L4 L7 N3 N4 N7 R3 R4 R7 U3 U4 U7 V8 W3
?
AK11 AK12
V_1D8V_SFR
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
VDDQ
AJ13 AJ14 AJ23 AJ24 AR20 AR21 AR22 AR23 AR24 AU19 AU23 AU27 AU31 AV21 AV24 AV25 AV29 AV33 AW31 AY23 AY26 AY28
AJ20
C
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCPLL VCCPLL IO/SA/PLL POWER
8 OF 11 CPU_SKT_H2
?
B
CM
S
?
V_1D05V_CPU
pu
C
F32 F33 F34 G15 G16 G18 G19 G21 G22 G24 G25 G27 G28 G30 G31 G32 G33 H13 H14 H15 H16 H18 H19 H21 H22 H24 H25 H27 H28 H30 H31 H32 J12 J15 J16 J18 J19 J21 J22 J24 J25 J27 J28 J30 K15 K16 K18 K19 K21 K22 K24 K25 K27 K28 K30 L13 L14 L15 L16 L18 L19 L21 L22 L24 L25 L27 L28 L30 M14 M15 M16 M18 M19 M21 M22 M24 M25 M27 M28 M30
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
m
D
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
Co
A12 A13 A14 A15 A16 A18 A24 A25 A27 A28 B15 B16 B18 B24 B25 B27 B28 B30 B31 B33 B34 C15 C16 C18 C19 C21 C22 C24 C25 C27 C28 C30 C31 C33 C34 C36 D13 D14 D15 D16 D18 D19 D21 D22 D24 D25 D27 D28 D30 D31 D33 D34 D35 D36 E15 E16 E18 E19 E21 E22 E24 E25 E27 E28 E30 E31 E33 E34 E35 F15 F16 F18 F19 F21 F22 F24 F25 F27 F28 F30 F31
A
A
FOXCONN PCEG Title
CPU5-POWER Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
12
of
45
5
4
3
2
1
Fab 1.0
B
G8 H1 H17 H2 H20 H23 H26 H29 H33 H35 H37 H39 H5 H6 H9 J11 J17 J20 J23 J26 J29 J32 K1 K12 K13 K14 K17 K2 K20 K23 K26 K29 K33 K35 K37 K39 K5 K6 L10 L17 L20 L23 L26 L29 L8 M1 M17 M2 M20 M23 M26 M29 M33 M35 M37 M39 M5 M6 M9 N8 P1 P2 P36 P38 P40 P5 P6 R33 R35 R37 R39 R8 T1 T5 T6 U8 V1 V2 V33 V34 V35 V36 V37 V38 V39 V40 V5 W6 Y5 Y8
D
U1_1
Lt d.
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
ny
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF VSS_NCTF
rC te
SKT_H2?
U1J
REV = 4 BALLMAP_REV = 1.6
AB7 AD37 AG4 AJ29 AJ30 AJ31 AV34 AW34 P35 P37 P39 R34 R36 R38 R40
A38 AU40 AW38 C2 D1
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
AT11 AP20 AN20 AU10 AY10
RSVD16 RSVD17 RSVD18 RSVD19 RSVD20
RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15
C
AF4 AB6 AE6 AJ11
RSVD21 RSVD22 RSVD23 RSVD24
NCTF1 NCTF2 NCTF3 NCTF4 NCTF5
D38 C39 C38 J34 N34
RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 SPARES
10 OF 11 CPU_SKT_H2
?
B
S
9 OF 11 ?
CM
CPU_SKT_H2
AV11 AV14 AV17 AV3 AV35 AV38 AV6 AW10 AW11 AW14 AW16 AW36 AW6 AY11 AY14 AY18 AY35 AY4 AY6 AY8 B10 B13 B14 B17 B23 B26 B29 B32 B35 B38 B6 C11 C12 C17 C20 C23 C26 C29 C32 C35 C7 C8 D17 D2 D20 D23 D26 D29 D32 D37 D39 D4 D5 D9 E11 E12 E17 E20 E23 E26 E29 E32 E36 E7 E8 F1 F10 F13 F14 F17 F2 F20 F23 F26 F29 F35 F37 F39 F5 F6 F9 G11 G12 G17 G20 G23 G26 G29 G34 G7 AY37 B3
CPU_SKT_H2
om pa
BALLMAP_REV = 1.6 AM27 AM3 AM30 AM36 AM37 AM38 AM39 AM4 AM40 AM5 AN10 AN11 AN14 AN17 AN19 AN22 AN24 AN27 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN5 AN6 AN7 AN8 AN9 AP1 AP11 AP14 AP17 AP22 AP25 AP27 AP30 AP36 AP37 AP4 AP40 AP5 AR11 AR14 AR17 AR18 AR19 AR27 AR30 AR36 AR5 AT1 AT10 AT12 AT13 AT15 AT16 AT17 AT2 AT25 AT27 AT28 AT29 AT3 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AT4 AT40 AT5 AT6 AT7 AT8 AT9 AU1 AU15 AU26 AU34 AU4 AU6 AU8 AV10
pu
C
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
REV = 4
m
D
SKT_H2
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_AK10 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_NCTF VSS_NCTF
Co
U1I
A17 A23 A26 A29 A35 AA33 AA34 AA35 AA36 AA37 AA38 AA6 AB5 AC1 AC6 AD33 AD36 AD38 AD39 AD40 AD5 AD8 AE3 AE33 AE36 AF1 AF34 AF36 AF37 AF40 AF5 AF6 AF7 AG36 AH2 AH3 AH33 AH36 AH37 AH38 AH39 AH40 AH5 AH8 AJ12 AJ15 AJ18 AJ21 AJ25 AJ27 AJ36 AJ5 AK1 AK10 AK13 AK14 AK16 AK22 AK28 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK4 AK40 AK5 AK6 AK7 AK8 AK9 AL11 AL14 AL17 AL19 AL24 AL27 AL30 AL36 AL5 AM1 AM11 AM14 AM17 AM2 AM21 AM23 AM25 A4 AV39
U1K
?
A
A
FOXCONN PCEG Title
CPU6-GND Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
13
of
45
A
R512 r0402h4
* 1K +/-1% Reserved
C534 0.1uF 16V, X7R, +/-10% c0402h6
*1K +/-1%
Dummy r0402h4 Reserved
5
0.1uf 由Y5V改为X7R
*
R501
* C538 1uF 6.3V,+/-10% c0402h6 Reserved
*
C539 0.1uF 16V, +/-10% c0402h6 Reserved
B
C606 0.1uF 16V, +/-10% c0402h6 Reserved
*
0.1uf 由Y5V改为X7R
*
CLOSE TO DIMM POWER PIN
V_SM 15,16,20,27 SMB_CLK_MAIN 15,16,20,27 SMB_DATA_MAIN 10 D3_SBS_A[2..0]
V_SM_VTT V_SM
PLACE BETWEEN DIMM1 AND CPU
V_SM_VTT V_SM
EC47 820uF ECAP,+/-20%,2.5V ce25d63h90 Reserved
H61M09 20121121
V_SM
C545 0.1uF 16V, X7R, +/-10% c0402h6 Reserved
4
11
D3_CA_VREF_A
* R499 r0402h4 C563 0.1uF 16V, X7R, +/-10% c0402h6
Dummy
3D3V_SYS
10
197 194 191 189 186 183 182 179 176 173 170 78 75 72 69 66 65 62 60 57 54 51 236
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VTT VTT
10 10 10 10 D3_MAA_A[15..0]
1K +/-1% Reserved
*1K +/-1% R509
r0402h4 Reserved
*
10 10
D3_SCKE_A1 D3_SCKE_A0
10 10
D3_SCS_A_#1 D3_SCS_A_#0
3
Foxconn Confidential Document,please keep it secret.A3 2
168 74 192 73
188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171
64 63 185 184
RESET* CAS* RAS* WE*
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15
CK1/NU* CK1/NU CK0* CK0
S1* S0*
CKE1 CKE0
BA2 BA1 BA0
BLUE
D3_DQS_A_DP4 D3_DQS_A_DN4 D3_DQS_A_DP5 D3_DQS_A_DN5 D3_DQS_A_DP6 D3_DQS_A_DN6 D3_DQS_A_DP7 D3_DQS_A_DN7
85 84 94 93 103 102 112 111
D3_DM_A2 D3_DM_A3 D3_DM_A4 D3_DM_A5 D3_DM_A6 D3_DM_A7
143 144 152 153 203 204 212 213 221 222 230 231
Lt d.
3 4 9 10 122 123 128 129 12 13 18 19 131 132 137 138 21 22 27 28 140 141 146 147 30 31 36 37 149 150 155 156 81 82 87 88 200 201 206 207 90 91 96 97 209 210 215 216 99 100 105 106 218 219 224 225 108 109 114 115 227 228 233 234
D3_DATA_A0 D3_DATA_A1 D3_DATA_A2 D3_DATA_A3 D3_DATA_A4 D3_DATA_A5 D3_DATA_A6 D3_DATA_A7 D3_DATA_A8 D3_DATA_A9 D3_DATA_A10 D3_DATA_A11 D3_DATA_A12 D3_DATA_A13 D3_DATA_A14 D3_DATA_A15 D3_DATA_A16 D3_DATA_A17 D3_DATA_A18 D3_DATA_A19 D3_DATA_A20 D3_DATA_A21 D3_DATA_A22 D3_DATA_A23 D3_DATA_A24 D3_DATA_A25 D3_DATA_A26 D3_DATA_A27 D3_DATA_A28 D3_DATA_A29 D3_DATA_A30 D3_DATA_A31 D3_DATA_A32 D3_DATA_A33 D3_DATA_A34 D3_DATA_A35 D3_DATA_A36 D3_DATA_A37 D3_DATA_A38 D3_DATA_A39 D3_DATA_A40 D3_DATA_A41 D3_DATA_A42 D3_DATA_A43 D3_DATA_A44 D3_DATA_A45 D3_DATA_A46 D3_DATA_A47 D3_DATA_A48 D3_DATA_A49 D3_DATA_A50 D3_DATA_A51 D3_DATA_A52 D3_DATA_A53 D3_DATA_A54 D3_DATA_A55 D3_DATA_A56 D3_DATA_A57 D3_DATA_A58 D3_DATA_A59 D3_DATA_A60 D3_DATA_A61 D3_DATA_A62 D3_DATA_A63
D3_DM_A1
134 135
161 162
D3_DM_A0
125 126
3
76 193
169 50
52 190 71
ny
D3_DQS_A_DP3 D3_DQS_A_DN3
34 33
10
VREFCA VREFDQ SCL SDA SA1 SA0
D3_DQS_A_DP2 D3_DQS_A_DN2
25 24
D
10
D3_DQS_A_DN[7..0]
DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ
D3_DQS_A_DP1 D3_DQS_A_DN1
16 15
43 42
D3_DQS_A_DP0 D3_DQS_A_DN0
7 6
39 40 45 46 158 159 164 165
68 53 167
79 77 195
D
D3_DQS_A_DP[7..0]
DM8/DQS17 DQS17*
DM7/DQS16 NC/DQS16*
DM6/DQS15 DQS15*
DM5/DQS14 DQS14*
DM4/DQS13 DQS13*
DM3/DQS12 DQS12*
DM2/DQS11 DQS11*
DM1/DQS10 DQS10*
DM0/DQS9 DQS9*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
CB CB CB CB CB CB CB CB
NC/PAR_IN NC/ERR_OUT NC/TEST4
RSVD ODT1 ODT0
4
67 1 118 238 237 117
om pa
rC
C550 0.1uF 16V, +/-10% c0402h6 Reserved
te
H61M09 20121121
pu
C536 1uF 6.3V,+/-10% c0402h6 Reserved
m
*
Co
C535 1uF 6.3V,+/-10% c0402h6 Reserved
*
* 239 235 232 229 226 223 220 217 214 211 208 205 202 199 166 163 160 157 154 151 148 145 142 139 136 133 130 127 124 121 119 116 113 110 107 104 101 98 95 92 89 86 83 80 47 44 41 38 35 32 29 26 23 20 17 14 11 8 5 2
FREE1 FREE2 FREE3 FREE4
D3_ODT_A1 D3_ODT_A0
S
CM
* 240 120
198 187 49 48
C
DDRIII
* 5 2 1
CHANNEL A DIMM 1 SMB ADDRESS:000
10 10 D3_DATA_A[63..0]
PLACE RESISTORS CLOSE TO CH_A DIMMS ON DIMM_VREF_A
Size C
Date:
Document Number Friday, January 25, 2013 1
10
DIMM1 DDR III
C
D3_WE_A# 10 D3_RAS_A# 10 D3_CAS_A# 10 D3_DRAMRST# 10,15
D3_CA_VREF_A D3_DQ_VREF_A
D3_SBS_A2 D3_SBS_A1 D3_SBS_A0
D3_CK_DDR_A_DN1 D3_CK_DDR_A_DP1 D3_CK_DDR_A_DN0 D3_CK_DDR_A_DP0 D3_MAA_A0 D3_MAA_A1 D3_MAA_A2 D3_MAA_A3 D3_MAA_A4 D3_MAA_A5 D3_MAA_A6 D3_MAA_A7 D3_MAA_A8 D3_MAA_A9 D3_MAA_A10 D3_MAA_A11 D3_MAA_A12 D3_MAA_A13 D3_MAA_A14 D3_MAA_A15 B
DIMM_DQ_CPU_VREF_A
V_SM
C543 0.1uF 16V, X7R, +/-10% c0402h6 Reserved D3_DQ_VREF_A
A
Title
DDR3-1:CHA
FOXCONN PCEG
H61M09 Sheet 14 of 45 Rev 2.0
B
A
*
5
C589 1uF 6.3V,X5R c0402h6 Reserved
R646 r0402h4 C607 0.1uF 16V, X7R, +/-10% c0402h6 Dummy
*
C546 4.7uF 6.3V,+/-10% c0603h9 Reserved C592 0.1uF 16V, X7R c0402h6 Reserved
* *
1K +/-1% Reserved R645 1K +/-1% r0402h4 Reserved C593 1uF 6.3V,X5R c0402h6 Reserved
* C603 1uF 6.3V,X5R c0402h6 Reserved
*
* C595 1uF 6.3V,X5R c0402h6 Reserved
C592,C596由Y5Z改为X7R电阻
*
V_SM_VTT
H61MD 1128
C588 0.1uF 16V, X7R, +/-10% c0402h6 Reserved
4
CLOSE TO DIMM POWER PIN
V_SM 14,16,20,27 SMB_CLK_MAIN 14,16,20,27 SMB_DATA_MAIN 11 D3_SBS_B[2..0]
V_SM_VTT V_SM
11
D3_CA_VREF_B
* R506 r0402h4 C562 0.1uF 16V, X7R, +/-10% c0402h6
Dummy
3D3V_SYS
11
197 194 191 189 186 183 182 179 176 173 170 78 75 72 69 66 65 62 60 57 54 51 236
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDSPD
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 11 11 11 11 D3_MAA_B[15..0]
1K +/-1% Reserved
*1K +/-1%
r0402h4 Reserved
11 11
D3_SCKE_B1 D3_SCKE_B0
11 11
D3_SCS_B_#1 D3_SCS_B_#0
R496
*
3
Foxconn Confidential Document,please keep it secret.A3 2
168 74 192 73
188 181 61 180 59 58 178 56 177 175 70 55 174 196 172 171
RESET* CAS* RAS* WE*
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15
CK1/NU* CK1/NU CK0* CK0
S1* S0*
CKE1 CKE0
BA2 BA1 BA0
D3_DQS_B_DP4 D3_DQS_B_DN4 D3_DQS_B_DP5 D3_DQS_B_DN5 D3_DQS_B_DP6 D3_DQS_B_DN6 D3_DQS_B_DP7 D3_DQS_B_DN7
85 84 94 93 103 102 112 111
D3_DM_B2 D3_DM_B3 D3_DM_B4 D3_DM_B5 D3_DM_B6 D3_DM_B7
143 144 152 153 203 204 212 213 221 222 230 231
Lt d.
3 4 9 10 122 123 128 129 12 13 18 19 131 132 137 138 21 22 27 28 140 141 146 147 30 31 36 37 149 150 155 156 81 82 87 88 200 201 206 207 90 91 96 97 209 210 215 216 99 100 105 106 218 219 224 225 108 109 114 115 227 228 233 234
D3_DATA_B0 D3_DATA_B1 D3_DATA_B2 D3_DATA_B3 D3_DATA_B4 D3_DATA_B5 D3_DATA_B6 D3_DATA_B7 D3_DATA_B8 D3_DATA_B9 D3_DATA_B10 D3_DATA_B11 D3_DATA_B12 D3_DATA_B13 D3_DATA_B14 D3_DATA_B15 D3_DATA_B16 D3_DATA_B17 D3_DATA_B18 D3_DATA_B19 D3_DATA_B20 D3_DATA_B21 D3_DATA_B22 D3_DATA_B23 D3_DATA_B24 D3_DATA_B25 D3_DATA_B26 D3_DATA_B27 D3_DATA_B28 D3_DATA_B29 D3_DATA_B30 D3_DATA_B31 D3_DATA_B32 D3_DATA_B33 D3_DATA_B34 D3_DATA_B35 D3_DATA_B36 D3_DATA_B37 D3_DATA_B38 D3_DATA_B39 D3_DATA_B40 D3_DATA_B41 D3_DATA_B42 D3_DATA_B43 D3_DATA_B44 D3_DATA_B45 D3_DATA_B46 D3_DATA_B47 D3_DATA_B48 D3_DATA_B49 D3_DATA_B50 D3_DATA_B51 D3_DATA_B52 D3_DATA_B53 D3_DATA_B54 D3_DATA_B55 D3_DATA_B56 D3_DATA_B57 D3_DATA_B58 D3_DATA_B59 D3_DATA_B60 D3_DATA_B61 D3_DATA_B62 D3_DATA_B63
D3_DM_B1
134 135
161 162
D3_DM_B0
125 126
3
64 63 185 184
76 193
169 50
52 190 71
ny
D3_DQS_B_DP3 D3_DQS_B_DN3
34 33
11
VREFCA VREFDQ SCL SDA SA1 SA0
D3_DQS_B_DP2 D3_DQS_B_DN2
25 24
11
D3_DQS_B_DN[7..0]
DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ
D3_DQS_B_DP1 D3_DQS_B_DN1
16 15
43 42
D3_DQS_B_DP0 D3_DQS_B_DN0
7 6
39 40 45 46 158 159 164 165
68 53 167
D3_DQS_B_DP[7..0]
DM8/DQS17 DQS17*
DM7/DQS16 NC/DQS16*
DM6/DQS15 DQS15*
DM5/DQS14 DQS14*
DM4/DQS13 DQS13*
DM3/DQS12 DQS12*
DM2/DQS11 DQS11*
DM1/DQS10 DQS10*
DM0/DQS9 DQS9*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
DQS DQS*
CB CB CB CB CB CB CB CB
NC/PAR_IN NC/ERR_OUT NC/TEST4
79 77 195
4
67 1 118 238 237 117
om pa
rC
C596 0.1uF 16V, X7R c0402h6 Reserved
te
pu
m
Co
* VTT VTT
RSVD ODT1 ODT0
D3_ODT_B1 D3_ODT_B0
*
S
CM
* 239 235 232 229 226 223 220 217 214 211 208 205 202 199 166 163 160 157 154 151 148 145 142 139 136 133 130 127 124 121 119 116 113 110 107 104 101 98 95 92 89 86 83 80 47 44 41 38 35 32 29 26 23 20 17 14 11 8 5 2
FREE1 FREE2 FREE3 FREE4
C
240 120
198 187 49 48
D
DDRIII
*
5 2 1
CHANNEL B DIMM 3 SMB ADDRESS:010 D
11 11 D3_DATA_B[63..0]
3D3V_SYS
Size C
Date:
Document Number Friday, January 25, 2013 1
11
DIMM2 DDR III
BLUE
C
D3_WE_B# 11 D3_RAS_B# 11 D3_CAS_B# 11 D3_DRAMRST# 10,14
D3_CA_VREF_B D3_DQ_VREF_B
D3_SBS_B2 D3_SBS_B1 D3_SBS_B0
D3_CK_DDR_B_DN1 D3_CK_DDR_B_DP1 D3_CK_DDR_B_DN0 D3_CK_DDR_B_DP0 D3_MAA_B0 D3_MAA_B1 D3_MAA_B2 D3_MAA_B3 D3_MAA_B4 D3_MAA_B5 D3_MAA_B6 D3_MAA_B7 D3_MAA_B8 D3_MAA_B9 D3_MAA_B10 D3_MAA_B11 D3_MAA_B12 D3_MAA_B13 D3_MAA_B14 D3_MAA_B15 B
DIMM_DQ_CPU_VREF_B
V_SM V_SM
D3_DQ_VREF_B C542 0.1uF 16V, X7R, +/-10% c0402h6 Reserved A
PLACE RESISTORS CLOSE TO CH_B DIMMS ON DIMM_VREF_B
Title
DDR3-2:CHB
FOXCONN PCEG
H61M09 Sheet 15 of 45 Rev 2.0
5
4
3
3D3V_DUAL
2
3D3V_SYS 12V_SYS
12V_SYS
1
3D3V_SYS
PCI-E1_16X
14,15,20,27 14,15,20,27
D
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
SMB_CLK_RESUME SMB_DATA_RESUME
20,27
PCIE_WAKE#
12V 12V RSVD1 GND SMCLK SMDAT GND 3.3V JTAG1 3.3VAUX WAKE#
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
PRSNT1# 12V 12V GND JTAG2 JTAG3 JTAG4 JTAG5 3.3V 3.3V PWRGD
D
PCIE_SLOT_RST#
KEY
X_1X16_TXP5 X_1X16_TXN5
9 9
X_1X16_TXP6 X_1X16_TXN6
9 9
X_1X16_TXP7 X_1X16_TXN7
9 9
X_1X16_TXP8 X_1X16_TXN8
9 9
X_1X16_TXP9 X_1X16_TXN9
9 9
X_1X16_TXP10 X_1X16_TXN10
9 9
X_1X16_TXP11 X_1X16_TXN11
9 9
X_1X16_TXP12 X_1X16_TXN12
9 9
X_1X16_TXP13 X_1X16_TXN13
9 9
X_1X16_TXP14 X_1X16_TXN14
B
9 9
X_1X16_TXP15 X_1X16_TXN15
2 220nF 2 220nF
+/-10% +/-10%
X_1X16_TXP3_C X_1X16_TXN3_C
C288 1 C289 1
2 220nF 2 220nF
+/-10% +/-10%
X_1X16_TXP4_C X_1X16_TXN4_C
C294 1 C297 1
2 220nF 2 220nF
+/-10% +/-10%
X_1X16_TXP5_C X_1X16_TXN5_C
C314 1 C308 1
2 220nF 2 220nF
+/-10% +/-10%
X_1X16_TXP6_C X_1X16_TXN6_C
C328 1 C331 1
2 220nF 2 220nF
+/-10% +/-10%
X_1X16_TXP7_C X_1X16_TXN7_C
C348 1 C352 1
2 220nF 2 220nF
+/-10% +/-10%
X_1X16_TXP8_C X_1X16_TXN8_C
C365 1 C372 1
2 220nF 2 220nF
+/-10% +/-10%
X_1X16_TXP9_C X_1X16_TXN9_C
C396 1 C409 1 C432 1 C430 1 C444 1 C446 1 C450 1 C452 1 C456 1 C454 1 C462 1 C460 1
2 220nF 2 220nF 2 220nF 2 220nF 2 220nF 2 220nF 2 220nF 2 220nF 2 220nF 2 220nF 2 220nF 2 220nF
+/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10% +/-10%
B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
X_1X16_TXP10_C X_1X16_TXN10_C X_1X16_TXP11_C X_1X16_TXN11_C
+/-10% +/-10%
B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82
HSOP1 HSON1 GND GND HSOP2 HSON2 GND GND HSOP3 HSON3 GND RSVD3 PRSNT2_B31# GND
RSVD5 GND HSIP1 HSIN1 GND GND HSIP2 HSIN2 GND GND HSIP3 HSIN3 GND RSVD6
HSOP4 HSON4 GND GND HSOP5 HSON5 GND GND HSOP6 HSON6 GND GND HSOP7 HSON7 GND PRSNT2_B48# GND
RSVD7 GND HSIP4 HSIN4 GND GND HSIP5 HSIN5 GND GND HSIP6 HSIN6 GND GND HSIP7 HSIN7 GND
HSOP8 HSON8 GND GND HSOP9 HSON9 GND GND HSOP10 HSON10 GND GND HSOP11 HSON11 GND GND HSOP12 HSON12 GND GND HSOP13 HSON13 GND GND HSOP14 HSON14 GND GND HSOP15 HSON15 GND PRSNT2_B81# RSVD4
RSVD8 GND HSIP8 HSIN8 GND GND HSIP9 HSIN9 GND GND HSIP10 HSIN10 GND GND HSIP11 HSIN11 GND GND HSIP12 HSIN12 GND GND HSIP13 HSIN13 GND GND HSIP14 HSIN14 GND GND HSIP15 HSIN15 GND
X_1X16_TXP12_C X_1X16_TXN12_C X_1X16_TXP13_C X_1X16_TXN13_C X_1X16_TXP14_C X_1X16_TXN14_C X_1X16_TXP15_C X_1X16_TXN15_C
A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
X_1X16_RXP1 X_1X16_RXN1 X_1X16_RXP2 X_1X16_RXN2 X_1X16_RXP3 X_1X16_RXN3
A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
X_1X16_RXP4 X_1X16_RXN4
X_1X16_RXP0 9 X_1X16_RXN0 9
Lt d.
**
C273 1 C274 1
B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
22 22
27,33
C26 100pF 50V, NPO, +/-5% c0402h6 Reserved
X_1X16_RXP1 9 X_1X16_RXN1 9 X_1X16_RXP2 9 X_1X16_RXN2 9 X_1X16_RXP3 9 X_1X16_RXN3 9
ny
X_1X16_TXP4 X_1X16_TXN4
9 9
X_1X16_TXP2_C X_1X16_TXN2_C
C_PCH_100M_X16_DP C_PCH_100M_X16_DN X_1X16_RXP0 X_1X16_RXN0
X_1X16_RXP5 X_1X16_RXN5 X_1X16_RXP6 X_1X16_RXN6 X_1X16_RXP7 X_1X16_RXN7
A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82
rC
9 9
X_1X16_TXP1_C X_1X16_TXN1_C
+/-10% +/-10%
GND REFCLK+ REFCLKGND HSIP0 HSIN0 GND
*
A12 A13 A14 A15 A16 A17 A18
te
X_1X16_TXP3 X_1X16_TXN3
+/-10% +/-10%
2 220nF 2 220nF
RSVD2 GND HSOP0 HSON0 GND PRSNT2_B17# GND
pu
9 9
2 220nF 2 220nF
C262 1 C265 1
m
X_1X16_TXP2 X_1X16_TXN2
C252 1 C253 1
** ** **
9 9
2 220nF +/-10% Reserved X_1X16_TXP0_C 2 220nF +/-10% X_1X16_TXN0_C
Co
C
X_1X16_TXP1 X_1X16_TXN1
C248 1 C247 1
** ** ** **
9 9
X_1X16_TXP0 X_1X16_TXN0
** ** ** ** ** ** ** **
9 9
B12 B13 B14 B15 B16 B17 B18
X_1X16_RXP4 9 X_1X16_RXN4 9
om pa
All AC Coupling caps. should be placed within 250 mils of the connector
X_1X16_RXP8 X_1X16_RXN8 X_1X16_RXP9 X_1X16_RXN9 X_1X16_RXP10 X_1X16_RXN10 X_1X16_RXP11 X_1X16_RXN11 X_1X16_RXP12 X_1X16_RXN12 X_1X16_RXP13 X_1X16_RXN13 X_1X16_RXP14 X_1X16_RXN14 X_1X16_RXP15 X_1X16_RXN15
C
X_1X16_RXP5 9 X_1X16_RXN5 9 X_1X16_RXP6 9 X_1X16_RXN6 9 X_1X16_RXP7 9 X_1X16_RXN7 9
X_1X16_RXP8 9 X_1X16_RXN8 9 X_1X16_RXP9 9 X_1X16_RXN9 9 X_1X16_RXP10 9 X_1X16_RXN10 9 X_1X16_RXP11 9 X_1X16_RXN11 9 X_1X16_RXP12 9 X_1X16_RXN12 9 X_1X16_RXP13 9 X_1X16_RXN13 9
B
X_1X16_RXP14 9 X_1X16_RXN14 9 X_1X16_RXP15 9 X_1X16_RXN15 9
CM
S
Slot-PCIE-16X
12V_SYS 3D3V_SYS
*
EC63 470uF ECAP,16V, +/-20% ce35d80h130 Dummy
*
C23 1uF +/-10% c0603h9 Reserved
*
C237 0.1uF 16V, +/-10% c0402h6 Reserved
A
A
0.1uf 由Y5V改为X7R
H61M09 20121121
change C23 from 4.7uf to 1uf add 470uf DIP CAP(预留) ,靠近DIMM H61MD 20121120 Dummy EC63 1213 near slot
FOXCONN PCEG Title
PCIE X16/X1 Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
16
of
45
5
4
3
2
1
D
D
PCI_PME_N
3D3V_DUAL
?
3D3V_SYS
CPT_CRB
U3A
RN17
TP52
TP53
BA15 AV8 BU12 BE2
TP54
C
PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3
BG5 BT5 BK8 AV11
PCI_INT_A# PCI_INT_B# PCI_INT_C# PCI_INT_D# PCI_INT_E# PCI_INT_F# PCI_INT_G# PCI_INT_H#
BK10 BJ5 BM15 BP5 BN9 AV9 BT15 BR4
GNT0# GNT1#_GPIO51 GNT2#_GPIO53 GNT3#_GPIO55
REQ0# REQ1#_GPIO50 REQ2#_GPIO52 REQ3#_GPIO54
PIRQA# PIRQB# PIRQC# PIRQD# PIRQE#_GPIO2 PIRQF#_GPIO3 PIRQG#_GPIO4 PIRQH#_GPIO5
C_BE0# C_BE1# C_BE2# C_BE3#
PCI
1 OF 10 CPT_CRB/BGA
PCI_INT_G# PCI_INT_C# PCI_INT_E# PCI_INT_A#
*1
PCI_TRDY# PCI_DEVSEL# PCI_INT_F# PCI_REQ#3
*1
3 5 7
2 4 6 8
Lt d.
去掉R437，PME#改为TP H61MD 1128 去掉R445,R454，PCI_GNT#0,PCI_GNT#2改为TP
BF15 BF17 BT7 BT13 BG12 BN11 BJ12 BU9 BR12 BJ3 BR9 BJ10 BM8 BF3 BN2 BE4 BE6 BG15 BC6 BT11 BA14 BL2 BC4 BL4 BC2 BM13 BA9 BF9 BA8 BF8 AV17 BK12
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
8.2KOhm RN16
3 5 7
PCI_REQ#2 PCI_SERR# PCI_REQ#1 PCI_INT_D#
PCI_IRDY# PCI_FRAME# PCI_STOP# PCI_PLOCK#
BN4 BP7 BG2 BP13
PCI_INT_H# PCI_PERR# PCI_INT_B# PCI_REQ#0
+/-5%
2 4 6 8
8.2KOhm
ny
PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3
C_PCH_PCI_FB
om pa
22
REV 1.0 PAR DEVSEL# CLKIN_PCILOOPBACK PCIRST# IRDY# PME# SERR# STOP# PLOCK# TRDY# PERR# FRAME#
rC
PCI_IRDY# PCI_PME_N PCI_SERR# PCI_STOP# PCI_PLOCK# PCI_TRDY# PCI_PERR# PCI_FRAME#
BH8 BH9 BD15 AV14 BF11 AV15 BR6 BC12 BA17 BC8 BM3 BC11
PCI_DEVSEL#
+/-5%
RN19
*1 3 5 7
2 4 6 8
8.2KOhm
+/-5%
C
RN15
*1 3 5 7
2 4 6 8
8.2KOhm RN18
*1 3 5 7
+/-5%
2 4 6 8
8.2KOhm
+/-5%
m
pu
te
?
STRAP: Boot BIOSselect
0
PCI_GNT#3
SATA1GP 0
0
1
PCI
1
0
SPI
1
PCI_GNT#1
S
NAND
R438 r0402h4
Internal pull-up
CM
1
R446 r0402h4
B
1
4.7KOhm +/-1% Dummy
PCI_GNT#0
*
GNT1
LPC
Co
BOOT DEVICE
PCH_HS
1
R446由1K改为4.7K 1129
check whether GNT1 or SATA1GP(GPIO19)
*
B
PCI_GNT#2 1K Dummy
DG 0.7 GNT3 is top block swap mode: connect to ground with 4.7k ohm weak pull down resistor for top block swap mode
Heatsink
2
2
GNT2#/GPIO53:ESI strap for server platform ONLY,Do not pull low.
A
A
FOXCONN PCEG Title
PCH1-PCI Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
17
of
45
5
4
3
2
1
D
? CPT_CRB
H_DMI_TX_DN2 H_DMI_TX_DP2
9 9
H_DMI_TX_DN3 H_DMI_TX_DP3
H_DMI_RX_DN3 H_DMI_RX_DP3 DMICOMP C_100M_DMI_PCH_DN C_100M_DMI_PCH_DP
4: SLOT1
2: LAN
C514 C512 C509 C511
0.1uF 16V, X7R, +/-10% 0.1uF 16V, X7R, +/-10%
X_PE_TX_DN1_C X_PE_TX_DP1_C
0.1uF 16V, X7R, +/-10% 0.1uF 16V, X7R, +/-10%
X_PE_TX_DN2_C X_PE_TX_DP2_C
J20 L20 F25 F23 P20 R20 C22 A22 H17 J17 E21 B21 P17 M17 F18 E17 N15 M15 B17 C16 J15 L15 A16 B15 J12 H12 F15 F13 H10 J10 B13 D13
CLKIN_DMI_N CLKIN_DMI_P PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 PERN6 PERP6 PETN6 PETP6 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8
U_USB_DN8 U_USB_DP8 U_USB_DN9 U_USB_DP9 U_USB_DN10 U_USB_DP10 U_USB_DN11 U_USB_DP11
BM43 BD41 BG41 BK43 BP43 BJ41 BT45 BM45
OC0#_GPIO59 OC1#_GPIO40 OC2#_GPIO41 OC3#_GPIO42 OC4#_GPIO43 OC5#_GPIO9 OC6#_GPIO10 OC7#_GPIO14
BP25 BM25
USBRBIAS# USBRBIAS
更改：将0,1,2,3用于front panel，使用OC0,1 将8,9,10,11用于back panel，使用OC4，5 H61MD 20121120
U_USB_OC#01
32
U_USB_OC#45
31
OC6# OC7#
3D3V_DUAL
USBRBIAS R483 r0402h4
A32 DMIRBIAS
USBRBIAS (R631): TIE TRACES TOGETHER CLOSE TO PINS, WITH LENGTH NO LONGER THAN 450 MILS TO RESISTOR
22.6 +/-1% Reserved
C_96M_DREF_DN C_96M_DREF_DP R488 r0402h4
750 +/-1% Reserved
RN107
OC2# OC3# OC6# OC7#
*1 3 5 7
2 4 6 8
10K Ohm +/-5% 8p4r0402h6 Reserved
DMIRBIAS(R108): TIE TRACES TOGETHER CLOSE TO PINS, WITH LENGTH NO LONGER THAN 450 MILS TO RESISTOR
m
DMI2RBIAS
C
31 31 31 31 31 31 31 31
OC2# OC3#
BD38 BF38
CLKIN_DOT_96N CLKIN_DOT_96P
pu
去掉USB3.0 for H61MD 20121120
P33 R33
PCI-E
27 X_PE_RX_DN1 27 X_PE_RX_DP1 27 X_PE_TX_DN1 27 X_PE_TX_DP1 30 X_PE_RX_DN2 30 X_PE_RX_DP2 30 X_PE_TX_DN2 30 X_PE_TX_DP2
** **
BIOS:PCIE change to port 1 for H61M09 20121122
32 32 32 32 32 32 32 32
ny
9 9
9 9
*
H_DMI_RX_DN2 H_DMI_RX_DP2
U_USB_DN0 U_USB_DP0 U_USB_DN1 U_USB_DP1 U_USB_DN2 U_USB_DP2 U_USB_DN3 U_USB_DP3
om pa
H_DMI_RX_DN1 H_DMI_RX_DP1
9 9
USB
* C
9 9
BF36 BD36 BC33 BA33 BM33 BM35 BT33 BU32 BR32 BT31 BN29 BM30 BK33 BJ33 BF31 BD31 BN27 BR29 BR26 BT27 BK25 BJ25 BJ31 BK31 BD27 BF27 BK27 BJ27
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12P USBP12N USBP13P USBP13N
rC
R486 49.9 +/-1% r0402h4 Reserved
H_DMI_TX_DN1 H_DMI_TX_DP1
REV 1.0
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_IRCOMP DMI_ZCOMP
DMI
V_1D05V_PCH
9 9
H_DMI_RX_DN0 H_DMI_RX_DP0
D33 B33 J36 H36 A36 B35 P38 R38 B37 C36 H38 J38 E37 F38 M41 P41 B31 E31
te
9 9
H_DMI_TX_DN0 H_DMI_TX_DP0
*
U3B 9 9
Lt d.
D
B
2 OF 10 CPT_CRB/BGA
?
* * * *
CM
S
Co
B
C_100M_DMI_PCH_DN R238 r0402h4
10K +/-1% Reserved
C_100M_DMI_PCH_DP R240 r0402h4
10K +/-1% Reserved
C_96M_DREF_DN
R243 r0402h4
10K +/-1% Reserved
C_96M_DREF_DP
R244 r0402h4
10K +/-1% Reserved
Stub is as short as possible
A
A
FOXCONN PCEG Title
PCH2-DMI/PCIE/USB Size C Date: 5
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
18
of
45
5
4
BA53 BE54 BF55 AW53
SATALED# SATAICOMPI SATAICOMPO
AY20
SATA0GP_GPIO21 SATA1GP_GPIO19 SATA2GP_GPIO36 SATA3GP_GPIO37 SATA4GP_GPIO16 SATA5GP_GPIO49
NC
SATA3COMPI SATA3RCOMPO C
C_SATA_PCH_DN C_SATA_PCH_DP
SATA3RBIAS
A20GATE INIT3_3V# RCIN# SERIRQ THRMTRIP# PECI PMSYNCH
BF57 AJ55 AJ53
SATA_LED#
BC54 AY52 BB55 BG53 AU56 BA56
SATA0GP SATA1GP SATA2GP SATA3GP SATA4GP SATA5GP
AE54 AE52
SATA3_COMP
SATA_LED#
AC52
SATA3_RBIAS
BB57 BN56 BG56 AV52 E56 H48 F55
A20GATE INT3V3 KBRST_N SERIRQ PCH_THERMTRIP_N R539 0 +/-5% r0402h4 Dummy
A20GATE 33 TP55 KBRST_N 33 SERIRQ 33,35 PCH_THERMTRIP_N PCH_PECI 8,33 H_PM_SYNC_0 8
T_SATA_TX_DP5 C670 T_SATA_TX_DN5 C671 T_SATA_RX_DN5 C672 T_SATA_RX_DP5 C673
8
10K +/-1% r0402h4 Reserved
Stub is as short as possible
*
SATARBAS SATA3_COMP SATA3_RBIAS
10nF 10nF
25V, X7R, +/-10% T_SATA_RX_C_DN1 25V, X7R, +/-10% T_SATA_RX_C_DP1
SATA_3
10nF 10nF
25V, X7R, +/-10% 25V, X7R, +/-10%
T_SATA_TX_C_DP4 T_SATA_TX_C_DN4
10nF 10nF
25V, X7R, +/-10% 25V, X7R, +/-10%
T_SATA_RX_C_DN4 T_SATA_RX_C_DP4
10nF 10nF
25V, X7R, +/-10% 25V, X7R, +/-10%
T_SATA_TX_C_DP5 T_SATA_TX_C_DN5
10nF 10nF
25V, X7R, +/-10% 25V, X7R, +/-10%
T_SATA_RX_C_DN5 T_SATA_RX_C_DP5
1 2 3 4 5 6 7
8 9 C
CONN-SATA SATA_4 1 2 3 8 4 5 9 6 7 CONN-SATA
Need double check
RN108
*1
PCH_GPIO1 PCH_GPIO6 PCH_GPIO7 PCH_GPIO70
m
2 4 6 8
3 5 7
10K Ohm +/-5% 8p4r0402h6 Reserved
B
GPIO1,GPIO6,GPIO7,GPIO70,GPIO71加10K上拉电阻1129 RN41
*1
GPIO38 SATA_LED# PCH_GPIO71 KBRST_N
*R543 49.9
2 4 6 8
3 5 7
+/-1% r0402h4 Reserved
10K Ohm +/-5% 8p4r0402h6 Reserved
S
CM
*1
SATA4GP SERIRQ GPIO48 SATA5GP
3D3V_SYS
10K Ohm +/-5% 8p4r0402h6 Reserved
+/-1% r0402h4 Reserved R471 10K +/-1% r0402h4 @ID1_H
*
R470 10K +/-1% r0402h4 @ID0_H
*
R460 10K +/-1% r0402h4 @ID2_H
*
将R605改为10K1129 RN44
*1
SCLOCK A20GATE SATA0GP GPIO39
BOARD_ID0 BOARD_ID2
3 5 7
1
0
H61MD G3
0
1
1
+/-1% r0402h4
@ID1_L
@ID0_L
@ID2_L
BOARD ID
SATA2GP
R550
SATA3GP
R552
**
0
+/-1% r0402h4
SATA1GP
R572
*
H61MD-V
+/-1% r0402h4
去掉R605,将SCLOCK直接连到RN44
2 4 6 8
10K +/-1% r0402h4 Reserved A
10K +/-1% r0402h4 Reserved
1K+/-5% r0402h4 Dummy
R572由10K上拉改为1K下拉 H61MD 1128 SATA2GP,SATA3GP由上拉改为下拉
FOXCONN PCEG Title
PCH3-SATA/HOST Size C Date:
5
20130109
10K Ohm +/-5% 8p4r0402h6 Reserved
*R472 *R478 *R461 10K 10K 10K
BOARD_ID2 BOARD_ID1 BOARD_ID0 0 0 1
2 4 6 8
3 5 7
*R544 750
BOARD_ID1
H61MD
9
CONN-SATA
RN42
SATA3_RBIAS (R76): TIE TRACES TOGETHER CLOSE TO PINS, WITH LENGTH NO LONGER THAN 450 MILS TO RESISTOR
A
8
3D3V_SYS
Co
R595 37.4 Ohm SATA3_COMP (R122): TIE TRACES TOGETHER CLOSE TO PINS, +/-1% WITH LENGTH NO LONGER THAN 450 MILS TO RESISTOR r0402h4 Reserved
9
H61MD 1128
Resistor can change RN
V_1D05V_PCH
1 2 3 4 5 6 7
25V, X7R, +/-10% T_SATA_TX_C_DP1 25V, X7R, +/-10% T_SATA_TX_C_DN1
te
10K +/-1% r0402h4 Reserved
SATARRBIAS (R121): TIE TRACES TOGETHER CLOSE TO PINS, WITH LENGTH NO LONGER THAN 450 MILS TO RESISTOR
C649 C650
T_SATA_RX_DN4 C647 T_SATA_RX_DP4 C648
?
B
T_SATA_RX_DN1 T_SATA_RX_DP1
10nF 10nF
36
pu
R541
**
R542
C651 C652
T_SATA_TX_DP4 C641 T_SATA_TX_DN4 C642
INT3V3
C_SATA_PCH_DP
T_SATA_TX_DP1 T_SATA_TX_DN1
SATARBAS
去掉R528，INT3V3改为TP
C_SATA_PCH_DN
25V, X7R, +/-10% T_SATA_RX_C_DN0 25V, X7R, +/-10% T_SATA_RX_C_DP0
D
8
SATA_2
3 OF 10 CPT_CRB/BGA
10nF 10nF
1 2 3 4 5 6 7
CONN-SATA
AE50
TP16
HOST
AF55 AG56
** **
CLINK
CLKIN_SATA_N CLKIN_SATA_P
SCLOCK_GPIO22 SLOAD_GPIO38 SDATAOUT0_GPIO39 SDATAOUT1_GPIO48 GPIO
SCLOCK GPIO38 GPIO39 GPIO48
25V, X7R, +/-10% T_SATA_TX_C_DP0 25V, X7R, +/-10% T_SATA_TX_C_DN0
Lt d.
for H61MD 20121122
SST
T_SATA_RX_DN4 T_SATA_RX_DP4 T_SATA_TX_DN4 T_SATA_TX_DP4 T_SATA_RX_DN5 T_SATA_RX_DP5 T_SATA_TX_DN5 T_SATA_TX_DP5
C674 C675
** **
BIOS:board ID change
TACH0_GPIO17 TACH1_GPIO1 TACH2_GPIO6 TACH3_GPIO7 TACH4_GPIO68 TACH5_GPIO69 TACH6_GPIO70 TACH7_GPIO71
T_SATA_RX_DN0 T_SATA_RX_DP0
10nF 10nF
ny
BC43
SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP
C676 C677
** **
去掉USB3.0 for H61MD 20121120
BT17 BR19 BA22 BR16 BU16 BM18 BN17 BP15
BOARD_ID2 PCH_GPIO1 PCH_GPIO6 PCH_GPIO7 BOARD_ID0 BOARD_ID1 PCH_GPIO70 PCH_GPIO71
1
SATA_1 T_SATA_TX_DP0 T_SATA_TX_DN0
** **
Change Board ID and USB3.0 SMI Signal for Rev2.0
PWM0 PWM1 PWM2 PWM3
AL50 AL49 AL56 AL53 AN46 AN44 AN56 AM55 AN49 AN50 AT50 AT49 AT46 AT44 AV50 AV49
om pa
BN21 BT21 BM20 BN19
Non AMT
APWROK
rC
BC46
PWRGD_3V
T_SATA_RX_DN0 T_SATA_RX_DP0 T_SATA_TX_DN0 T_SATA_TX_DP0 T_SATA_RX_DN1 T_SATA_RX_DP1 T_SATA_TX_DN1 T_SATA_TX_DP1
*
PWRGD_3V
FAN
20,33
SATA2
D
CL_CLK1 CL_DATA1 CL_RST1#
AC56 AB55 AE46 AE44 AA53 AA56 AG49 AG47
SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP
SATA3
REV 1.0
BA50 BF50 BF49
2
CPT_CRB?
U3C
TP34 TP35 TP36
3
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09
Friday, January 25, 2013
Sheet 1
19
of
45
5
4
3
2
1
FAB 1.0
AU53 AT55 AT57 AR54 AR56
F_SPI_MOSI F_SPI_MISO F_SPI_CS0# F_SPI_CLK
H61MD 20121120
SPI_MOSI SPI_MISO SPI_CS0# SPI_CLK SPI_CS1#
RN46
A_HDA_SDO
A_HDA_SDO A_HDA_RST# A_HDA_BCLK A_HDA_SYNC
*1
19,33 33
PWRGD_3V PCH_RSMRST#
33
PCH_DPWROK
BR39 BN39 BT41 BN37 BM38 BJ38 BK38 BN41 BT37 BR42
RTCX1 RTCX2 RTCRST# SRTCRST# INTRUDER# PWROK RSMRST# INTVRMEN DPWROK DSWVRMEN
BIOS:PCIE wake pin change from WAKE# to GPIO11 for H61M09 20121122
SMLINK1_CLK SMLINK1_DATA
SMBALERT#_GPIO11 SMBCLK SMBDATA SML0ALERT#_GPIO60 SML0CLK SML0DATA SML1ALERT#_PCHHOT#_GPIO74 SML1CLK_GPIO58 SML1DATA_GPIO75
remove Q66,Q67,Q68,Q69,R636,R534,R565,R609 H61M09 1127 PWRGD_3V 4 OF 10 R1230 100KOhm +/-1% r0402h4 Dummy
CPT_CRB/BGA
SMB_DATA_RESUME
SMB_DATA_MAIN
PWRGD_3V预留一颗下拉电阻 1129
PCH_GPIO29
TP12 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS
BJ43
GPIO27
BG43 BD43 BT43
PCH_GPIO31
BE52 BE56
BC49 BA43 BC52 BF47 BC50
for PCI-E x16/ICH7/LAN/PCI/PCI-E x1/Riser Card/New Card
3D3V_DUAL
TP50 TP32
+/-5% r0402h4 Reserved
3D3V_SYS
+/-5% r0402h4 Dummy U38
+/-5% r0402h4 Dummy
Integrated TPM High to Enable Low to Disable Internal pull-down
GPIO27_WAKE#
S_SPKR_OUT
MX25L3205DPI-12G
COLAY
390K
r0603h6 Reserved
390K
r0603h6 Reserved
U52 1 2 3 4
S CM
VCCRTC
S_INTVRMEN R493
CS DO WP GND
CS# SO/SIO1 WP# GND
VCC HOLD# SCLK SI/SIO0
R551
LAN_WAKE#
R582
A_HDA_SDO_R
(2-3)
+/-1% Reserved
1K
+/-1% Dummy
R480
1K
+/-1% Dummy 3D3V_SB
R606
10K +/-1%Reserved
C
3D3V_SYS
SUSWARN#上拉电改为3D3V_SB,R606上件 3 1129 SUSWARN#上拉电改为3D3V_DUAL，预留3D3V_SB电 1203
Dummy
R626
Reserved R644 R649
PCH_GPIO34
R530
10K +/-1% r0402h4
BOARD_ID3
R633
10K +/-1% r0402h4
BOARD_ID4
R632
10K +/-1% r0402h4
BOARD_ID5
R652
A_HDA_SDO
10K +/-1% r0402h4 Reserved 10K +/-1% r0402h4 Dummy 10K +/-1% r0402h4 Reserved
JTAG CLK FILTER BYPASS WHEN LOW
PCH_GPIO46
*1K +/-5% JUMPER_ME(1-2)
10K +/-1% r0402h4 Reserved
0125
3D3V_DUAL
r0402h4 Reserved Header_1X3 3 2 3 1 2 1 R432 PCH_ME_ENABLE 1K +/-5% r0402h4 Reserved
R527 r0402h4
PCH_GPIO8
R485 r0402h4
1K +/-1% Dummy
1K +/-1% Dummy
*
If high disable ME Jumper_2P_Blu
GPIO8改为预留1K下拉电阻 1129 V_SM H_DRAMPWRGD
F_SPI_HOLD F_SPI_CLK F_SPI_MOSI
R630 r0402h4
B
200Ohm +/-5% Reserved
VCCRTC
Chassis Intruder Header
R586 1M *+/-5%
8 7 6 5
S_INTRUDER#
MX25L6406EM2I-12G Dummy
VCCRTC
r0402h4 Reserved INTR 1 2
Need double check
R489
Header_1X2
BIOS SMD 到时换成4M的料
1K
8
PCH_JTAG_RST# PCH_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
*
10K +/-1% Dummy
FAB 1.0
R5
Disable
+/-5% r0402h4 Reserved
OD PLL VR SUPPLY SEL(internal pull down) 1.8V SUPPLY WHEN SAMPLED LOW
FP_RST# 36 S_SPKR_OUT 36
H_PWRGD
1K
BIOS:LAN wake pin change from GPIO27 to WAKE# 1.5V SUPPLY WHEB SAMPLED HIGH for H61M09 20121122
GPIO27
H_PWRGD
C623 R670 1uF 1K 6.3V,X5R,+/-10% +/-5% c0402h6 r0402h4 Reserved Reserved
8 7 6 5
VCC HOLD CLK DIO
PCH_GPIO28
A_HDA_SYNC_R R473
30
Remove Thermal_Up signal for Rev2.0 SLP_SUS_N 38 S_PWRBTN# 33
ME (1-2)
10K +/-1% Reserved
FAB 1.0
ID4 from 1 to 0
Enable
2 4 6 8
3 5 7
H61MD 20121122
Dummy
Socket
F_SPI_MOSI
DSWVRMEN R494
*
Co
*R592 8.2K
1 2 3 4
F_SPI_CS0# F_SPI_MISO SPI_WP_GPIO57
U38_1
m
*R673 *R675 1K 1K B
TPM不需要此线，改为TP
PCH_SUSACK# 33 PCH_SUSWARN# 33,38 H_DRAMPWRGD 8
3D3V_DUAL
3D3V_DUAL
*1
H61MD 20121128
?
ME function
pu
SMB_CLK_RESUME
SMB_CLK_MAIN
39
去掉R614，改为TP
Change the SPI Power to 3D3V_DUAL for REV1.2 14,15,16,27
RN48 10K Ohm +/-5%
GPIO12 S_GP72_PU PCH_GPIO45 PCH_GPIO44
PCH_GPIO46 R481 P_VR_READY 41 PCH_RI 33 BIOS:PCIE wake pin change from WAKE# to GPIO11 PLTRST_N 8,33 LAN_WAKE# 30 LAN wake pin change from GPIO27 to WAKE# for H61M09 20121122 TP31 PCH_GPIO15 R482 S_SLP_S3# 33,37,41 S_SLP_S4# 33,39
PCH_RI PLTRST_N LAN_WAKE#
BH50 SLP_S5# TP51 BN54 LPCPD# BA47 AV46 S_GP72_PU BP45 SUSACK# BU46 SUSWARN# BG46 H_DRAMPWRGD
D53
D
FAB 1.0
Add SIO PME signal GPIO for Rev2.0
8p4r0402h6 Reserved
ME HEADER ME function
te
for Clock Generator/DIMMs/TPM/Clock Buffer
PROCPWRGD
rC
* 14,15,16,27
GPIO31 SLP_SUS# PWRBTN#
JTAG(SUS)
33 33
GPIO27
SYS_RESET# SPKR
BN49 BT47 BR49 BU49 BT51 BM50 BR46 BJ46 BK46
PCIE_WAKE# SMB_CLK_RESUME SMB_DATA_RESUME SML0_ALERT_N SMLINK0_CLK SMLINK0_DATA SML1_ALERT_N SMLINK1_CLK SMLINK1_DATA
16,27 PCIE_WAKE# SMB_CLK_RESUME SMB_DATA_RESUME
14,15,16,27 14,15,16,27
C
SLP_S5#_GPIO63 SUS_STAT#_GPIO61 SUSCLK_GPIO62 BATLOW#_GPIO72 SUSACK# SUSWARN#-SUS_PWR_DN_ACK-GPIO30 DRAMPWROK PM_GPIO(DSW)
22 Ohm +/-5% S_PCH_RTCX1 Reserved S_PCH_RTCX2 8p4r0402h6 S_RTCRST# S_SRTRST# S_INTRUDER# PWRGD_3V PCH_RSMRST# S_INTVRMEN PCH_DPWROK DSWVRMEN
1129
RN46应为33欧
A_HDA_SDO_R A_HDA_RST#_R A_HDA_BCLK_R A_HDA_SYNC_R
2 4 6 8
3 5 7
PCH_GPIO28 PCH_GPIO29 BOARD_ID3 PCH_GPIO44 PCH_GPIO45 PCH_GPIO46 SPI_WP_GPIO57
om pa
28 28 28 28
THERMAL# 33 PCH_GPIO13 39 SIO_PME# 33 TP56
PCH_GPIO15
*
OC67#线放在page 18
A_HDA_SDO_R A_HDA_SYNC_R
R1224
*
A_HDA_SDI0_R
HDA_BCLK HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDO HDA_SYNC
PCH_RI
Change Thermal shut down GPIO for Rev2.0
*
28
10K Ohm +/-5% 8p4r0402h6 Reserved
BU22 BC22 BD22 BF22 BK22 BJ22 BT23 BP23
PCH_GPIO8 GPIO12
10K +/-1% r0402h4 Reserved
SPI_WP_GPIO57
**
A_HDA_BCLK_R A_HDA_RST#_R
2 4 6 8
3 5 7
29
TP38
*
*1
BP51 BK50 BA25 BM55 BP53 BJ55 BH49 AV43 BL54 AV44 BP55 BT53 BJ53 BJ48 BK48 BC44 BC41 BM53 BN52
A_FP_AUDIO_PRESENCE#
BOARD_ID4 S_ME_ENABLE PCH_GPIO34 BOARD_ID5
*
3D3V_DUAL RN61
SML0_ALERT_N PCIE_WAKE# SML1_ALERT_N
GPIO8 LAN_PHY_PWR_CTRL_GPIO12 HDA_DOCK_RST#_GPIO13 GPIO15 GPIO24_MEM_LED GPIO28 SLP_LAN#_GPIO29 PCIECLKRQ2#_GPIO20 PCIECLKRQ5#_GPIO44 PCIECLKRQ6#_GPIO45 PCIECLKRQ7#_GPIO46 GPIO57 SYS_PWROK RI# PLTRST# WAKE# SLP_A# SLP_S3# SLP_S4#
AW55 BC56 BC25 BL56 BJ57
****
layout :Pls swap pin: SMLINK0_CLK RN45.7 SMLINK0_DATA RN45.5 SMLINK1_CLK RN45.3 SMLINK1_DATA RN45.1 1205
BMBUSY#_GPIO0 CLKRUN#_GPIO32 HDA_DOCK_EN#_GPIO33 STP_PCI#_GPIO34 GPIO35
REV 1.0
LDRQ1#_GPIO23 FWH0_LAD0 FWH1_LAD1 FWH2_LAD2 FWH3_LAD3 LDRQ0# FWH4_LFRAME#
3D3V_DUAL
10K +/-1% r0402h4 Reserved
*
10K Ohm +/-5% 8p4r0402h6 Reserved
BA20 BK15 BJ17 BJ20 BG20 BK17 BG17
L_AD0 L_AD1 L_AD2 L_AD3 L_DRQ0 L_FRAME_N
33,35 L_AD0 33,35 L_AD1 33,35 L_AD2 33,35 L_AD3 TP49 33,35 L_FRAME_N
R495
*
D
2 4 6 8
3 5 7
3D3V_SB
PCH_GPIO31
*
?
U3D RN45
*1
SMLINK1_DATA SMLINK1_CLK SMLINK0_DATA SMLINK0_CLK
将RN47换成两个电阻:R1223,R1224 H61M09 1127 SPI_WP_GPIO57接BIOS WP，去掉R1223 1128
*
H61MD 20121122
***
TPM不需要此线，改为TP
*
2.2K +/-5% r0402h4 Reserved 2.2K +/-5% r0402h4 Reserved
Lt d.
R32 R35
ny
SMB_CLK_RESUME SMB_DATA_RESUME
**
3D3V_DUAL
*20K +/-1% r0402h4 Reserved
H61MD 20121120 S_SRTRST#
BIOS socket colay SMD type for H61MD 20121120 3D3V_DUAL
10M +/-5% Reserved
+/-5% r0402h4 Reserved 3
Crystal Retainer
*
C524 18pF NPO,+/-5%,50V c0402h6 Reserved
PCH_TCK
***
51 Ohm +/-5% Reserved
*
3D3V_SUS 200 +/-1% Reserved 200 +/-1% Reserved 200 +/-1% Reserved
*R611 20K +/-1% r0402h4 Reserved
CLOSE TO PCH
A
sot23_123h11 Reserved
BAT54C sot23_123h11 Reserved
*R388 1K
BAT1_1
+/-5% r0402h4 Reserved
LITHIUM BATT
CR2032
BAT1 Battery Holder
Battery
*
C457 1uF 6.3V,X5R c0402h6 Reserved
R411 20K +/-1% r0402h4 Reserved
PCH_JTAG_RST#
* *
L465 1uF 6.3V,X5R c0402h6 Reserved
CLR_CMOS 1 2 1 3 2 3
S_RTCRST#
Header_1X3 R416 1K Change +/-5% r0402h4 Reserved
*
CLR_CMOS(1-2)
* Jumper_2P_Blu
C581 1uF 6.3V,X5R,+/-10% c0402h6 Dummy
*R623 10K +/-5% r0402h4 Reserved
FOXCONN PCEG
CLR_CMOS header and add a jumper Title
PCH4-LPC/SPI/SMB Size C Date:
5
C522 1uF 6.3V,X5R,+/-10% c0402h6 Reserved
2
-
C525 18pF NPO,+/-5%,50V c0402h6 Reserved
R634
PCH_JTAG_TDO R2 PCH_JTAG_TDI R4 PCH_JTAG_TMS R6
3 2 1
FOOTPRINT:0603 ONLY
*
VCCRTC
Q57 BAT54C
100 Ohm +/-1% Reserved 100 Ohm +/-1% Reserved 100 Ohm +/-1% Reserved
1
Q74
+
R492 r0603h6
R385 R387 R389
3D3V_SB
X4_1
4
3
VBAT_SIO
*R400 1K A
width 20 mils
VBAT
S_PCH_RTCX1
* ***
S_PCH_RTCX2 X4 XTAL-32.768kHz 1 2
4
3
Foxconn Confidential Document,please keep it secret.A3
2
Document Number
Rev 2.0
H61M09 Sheet
Friday, January 25, 2013 1
20
of
45
5
4
3
2
1
V_VGA_RED V_VGA_GREEN
?
CPT_CRB
U3F
V_VGA_BLUE REV 1.0 R452 150 +/ -1% r0402h4 Reserved
R451 150 +/ -1% r0402h4 Reserved
*
D
TP24 TP27 TP28 TP30 TP21 TP19
*
PORT B : HDMI
去掉HDMI port for H61MD 20121120
R8 R9 U14 U12 N6 R6 R14 R12 M11 M12 H8 K8 L5 M3 L2 J3 G2 G4 F3 F5 E4 E2 D5 B5 C6 D7 B7 C9 E11 B11
C
U2 T3 W3 U5 U8 U9
CRT_RED CRT_GREEN CRT_BLUE
DDPB_AUXP DDPB_AUXN DDPC_AUXP DDPC_AUXN DDPD_AUXP DDPD_AUXN
CRT_IRTN
DDPB_0P DDPB_0N DDPB_1P DDPB_1N DDPB_2P DDPB_2N DDPB_3P DDPB_3N DDPC_0P DDPC_0N DDPC_1P DDPC_1N DDPC_2P DDPC_2N DDPC_3P DDPC_3N DDPD_0P DDPD_0N DDPD_1P DDPD_1N DDPD_2P DDPD_2N DDPD_3P DDPD_3N
CRT_DDC_DATA CRT_DDC_CLK DAC_IREF
TP6 TP7 TP8 TP9
AN6 AN2 AM1
V_VGA_HSYNC V_VGA_VSYNC V_VGA_RED V_VGA_GREEN V_VGA_BLUE
R450 150 +/ -1% r0402h4 Reserved
*
*
D
CLOSE TO PCH: L