S-R Flip Flop Using Behavioural Modeling [PDF]

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S-R FLIP FLOP VHDL CODE USING BEHAVIOURAL MODELING 

Library ieee declaration.

library IEEE;  In “ieee” library std_logic_1164 package is declared for std_logic data types (predefined data types). use IEEE.STD_LOGIC_1164.ALL; -------------------------------------------------------------entity s_rff is  Entity describes circuit external ports. Port (s, r, clk, rst: in STD_LOGIC;  S, r, clk, rst: - input port to S-R flip flop.  q, qbar: - output port to S-R flip flop. q, qbar : inout STD_LOGIC);  q:- present state, qbar: - next state. end s_rff; -------------------------------------------------------------architecture Behavioral_srff of s_rff is ------------------------------------------------------------- signal temp: std_logic:='0';  -------------------------------------------------------------begin Architecture begins. -------------------------------------------------------------process(clk, rst, s,r) begin if (clk'event and clk='1') then  if (rst='0') then if (s='0' and r='0') then  temp