Assignment 2 [PDF]

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ECB1053 Digital Electronics 1 – September 2012 Semester Assignment 2 Due date: 5pm Friday, 23/11/2012. Please submit to Dr. Nasreen’s pigeon hole in Block 23, Level 3, by the deadline. LATE SUBMISSIONS WILL NOT BE ACCEPTED.

Q1.

The 7442 decoder with the truth table of Figure 1 does not have an ENABLE input. However, we can operate it as a 1-of-8 decoder by not using outputs O8 & O 9 and by using the D input as an ENABLE. This is illustrated in Figure 2. Describes how this arrangement works as an enabled 1-of-8 decoder, and state how the level on D either enables or disables the outputs.

Figure 1

Q2.

Figure 1

Consider the waveforms in Figure 3 (a). Apply these signals to the 74ALS138 (Figure 3 (b and (c) ) as follows:

A  A0 B  A1 C  A2 D  E3 Assume that E 1 and E 2 are tied LOW, and draw the waveforms for outputs O 0 , O 3 ,

O 6 and O 7 .

(a) 1

Q3.

The BCD-to-7-segment decoder/driver of Figure 4 contains the logic for activating each segment for the appropriate BCD inputs. Design the logic for activating the g segment.

Figure 2 Q4.

The timing diagram in Figure 5 is applied to the circuit in Figure 6. Draw the output waveform Z.

Figure 3

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Figure 4 Q5.

Show how a 16-input multiplexer such as the 74150 is used to generate the function

Z  ABCD  BCD  AB D  ABCD . Q6.

The circuit of Figure 7 shows how an eight-input MUX can be used to generate a fourvariable logic function, even though the MUX has only three SELECT inputs. Three of the logic variables A, B and C are connected to the SELECT inputs. The fourth variable D and its inverse D are connected to selected data inputs of the MUX as required by the desired logic function. The other MUX data inputs are tied to a LOW or a HIGH as required by the function. a) b)

Set up a truth table showing the output Z for the 16 possible combinations of input variables. Write the sum-of-products expression for Z and simplify it to verify that

Z  CB A  DC BA  DC B A

Figure 5 Q7.

Assuming that Q  0 initially, apply the x and y waveforms of Figure 8 to the SET and CLEAR inputs of a NAND latch, and determine the Q and Q waveforms.

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Figure 6

Q8.

Refer to the circuit of Figure 9. A technician tests the circuit operation by observing the output with a storage oscilloscope while the switch is moved from A to B, the scope display of XB appears as shown in Figure 10. What circuit fault could produce this result?

Figure 7

Figure 8 Q9.

The waveforms shown in Figure 11 are to be applied to the different FFs: a) positive-edge-triggered J-K b) negative-edge-triggered J-K Draw the Q waveform response for each of these FFs, assuming that Q=0 initially. Assume that each FF has a hold time of 0 seconds.

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Figure 9 Q10. An edge triggered D flip flop can be made to operate in the toggle mode by connecting it as shown in Figure 12. Assume that Q=0 initially, and determine the Q waveform.

Figure 10 Q11. Compare the operation of the D latch with a negative-edge-triggered D flip flop by applying the waveforms of Figure 13 to each and determining the Q waveforms.

Figure 11 Q12. Determine the Q waveform for the FF in Figure 14. Assume that Q=0 initially, and remember that the asynchronous inputs over ride all other inputs.

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Figure 12 Q13. In the circuit of Figure 15, inputs A, B and C are all initially LOW. Output Y is supposed to go HIGH only when A, B and C go HIGH in a certain sequence. a) Determine the sequence that will make Y go HIGH. b) Explain why the START pulse is needed. c) Modify this circuit to use D FFs.

Figure 13 Q14. A recirculating shift register is a shift register that keeps the binary information circulating through the register as clock pulses are applied. The shift register of Figure 16 can be made into a circulating register by connecting X0 to the DATA IN line. No external inputs are used. Assume that this circulating register starts out with 1011 stored in it (X3=1, X2=0, X1=1, and X0=1). List the sequence of states that the registers FFs go through as eight shift pulses (clock pulses) are applied.

Figure 14 Q15. In an adder circuit, an overflow occurs when the two numbers being added or subtracted produce a result that contains more bits than the capacity of the accumulator. For example, if the adder can only handle four bits, including a sign bit, numbers ranging from +7 to -8 (in 2’s complement) can be stored. Therefore, if the 6

result of an addition or subtraction exceeds +7 or -8, we would say that an overflow has occurred. When an overflow occurs, the results are useless because they cannot be stored correctly in the accumulator. To illustrate, add +5(0101) and +4(0100), which results in 1001. This 1001 would be interpreted incorrectly as a negative number because there is a 1 in the sign-bit position. In computers and calculators, there are usually circuits that are used to detect an overflow condition. There are several ways to do this. One method that can be used for the adder that operated in the 2’s complement system works as follows. 1. Examine the sign bits of the two numbers being added. 2. Examine the sign bit of the results. 3. Overflow occurs whenever the numbers being added are both positive and the sign bit of the result is 1 or when the numbers are both negative and the sign bit of the result is 0. Design this overflow circuit that will produce a 1 output whenever the overflow condition occurs for the adder in Figure 17. Next, verify the results for the following cases: (a) 5 + 4; (b) -4 + (-6); (c) 3 + 2. Cases (a) and (b) will produce and overflow, and case (c) will not.

Figure 17

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