Acer Aspire Z3-615 [PDF]
A 5 Madrid_SB Schematics Document HASWELL INTEL LYNX POINT D UMA SKU : U,N,O GPU SKU : U,N,O,G UMA SKU : S,A,L,O GPU
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Zitiervorschau
A
5
Madrid_SB Schematics Document HASWELL INTEL LYNX POINT
D
UMA SKU : U,N,O GPU SKU : U,N,O,G UMA SKU : S,A,L,O GPU SKU : S,A,L,G,O (unmount Q58)
.C O
195" 195" 23" 23"
AM
aMadrid aMadrid aMadrid aMadrid
M
Haswell LGA1150
OCP BOM manual control: R439,R440,R441,R862 [63.R0031.16L] Mount by BOM change list when w/o OCP
LA T
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
1
Project Name :PIM81L/aMadrid Size : 165x240mm
Project code :3PD00L010001 PCB No :13094 Revision :SB
Page
Run Power & Sequence DC to DC_12V(SY8246A) DC to DC_5V/3D3V(RT8243B) DC to DC_DDR3 1D5VS3 DC to DC_1D5V(Reserve) DC to DC_1D05V(APL5611) CPUCORE_ISL95825(1/2) CPUCORE_ISL95825(2/2) HDMI IN HDMI OUT HDD/ODD Mini PCIE Card WLAN and BT Mini PCIE Card TV Tuner Mini PCIE Card mSATA(res) PWRBTN / SIDE KEY / LED Debug connector GPU (1/5): PEG GPU (2/5): DIGITALOUT GPU (3/5): VRAM I/F GPU (4/5): GPIO/STRAP GPU (5/5): PWR/GND GPU VRAM1 (1/4) GPU VRAM3 (2/4) GPU VRAM2 (3/4) GPU VRAM4 (4/4) GPU PWR_NVVDD(NCP81172) GPU PWR_1D5V_VGA_S0 GPU PWR_1D05V/3D3V Stand off&EMI Cap&DUMMY BOM DUMMY PARTS SYSTEM & GPU POWER SEQUENCE SMBUS table THERMAL/AUDIO BLOCK DIAGRAM POWER BLOCK DIAGRAM
2
manual control (SB): 23U : SCA1,DCIN2 23G : SCA1,VGA1
New P/N for manual control (1A):
S: Scalar A: AMP L : AspireLINK G: GPU O: OCP N: non AMP U: UMA(NOT S) R: Unmount
VGA1 : 071.0N15S.0B0U SCA1 : 071.02586.000G SKT2 : 022.70001.0121 DCIN2 : 22.10261.661
C
B
.F
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Title
W
C
COVER PAGE BLACK DIAGRAM TABLE OF CONTENT CPU (DMI/FDI) CPU (DDR) CPU (Power) CPU (Thermal/JTAG) CPU(VSS) DDR3-SODIMM1 DDR3-SODIMM2 PCH (FDI/PCIE/DMI/USB) PCH (SATA/FAN/DP/VGA) PCH (AUDIO/GPIO/SPI) PCH CLOCK PCH ( POWER1) PCH ( STRAPS) PCH(VSS) Audio Codec_ALC269 Audio_ SW/ AMP/Con/DePop SIO ITE8732F_CX Scalar-RTD2586HD RTD2136 eDP to LVDS LCD/Inverter Connector Card reader_RTS5143 Aspire Link SideIO_USB30 Rear USB/TOU/Dongle/Web Cam LAN-RTL8111GA SPI/RTC Scalar Power USB 2.0 Power SW Battery Charger(Reserve) ADAPTER OCP / S3 reduction DCIN JACK
3
W
D
Page
W
Title
4
IX
5
4
GPU SKU: Hynix H5TC4G63AFR-11C KN.0040G.002 -> R619=4.99K(64.49915.6DL) Samsung K4W4G1646D-BC1A KN.0040B.005 -> R619=15K(64.15025.6DL)
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Cover Page Size Custom Date: 3
2
Document Number
Rev
SA
Madrid
Tuesday, January 21, 2014
Sheet 1
1
of
68
5
4
3
2
Project code PCB No Revision Project Name
Madrid Block Diagram (GPU)
1
:3PD00L010001 :13094 :SA :Madrid
SYSTEM DC/DC
DDRIII 1333/1600 Channel A
VRAM
Intel CPU
2GB
DDRIII 1333/1600 Channel B
Haswell
DDR3 900MHz
Intel pGA Core
Slot 1 DDRIII 1066/1333
ISL95832HRTZ
49 PCIe x 4(Gen3_8Gb/s) (Synergy)
CPU DC/DC
RTD2136
eDP
Scalar BD RTD2586
DMIx4
Intel
RGB CRT
Front side USB3.0
USB3.0 x 1
AZALIA
PCH Lynx Point H81
USB2.0 x 7
Web cam
LA T
Debug Port (Reserve)
Mic in
2 USB 3.0 / 8 USB 2.0/1.1 ports High Definition Audio
Flash ROM 8MB
SPI
DCBATOUT
1D05V_VTT
SYSTEM DC/DC
Amp
26
1D5V_S3 0D75V_S0 DDR_VREF_S3
LDO
37
RT9025-25PSP INPUTS
OUTPUTS
3D3V_S0
1D8V_S0
SPDIF
MDI
SYSTEM DC/DC
38
TPS51461RGER
RJ45 CONN
C
OUTPUTS
5V_S5
PCIE x 1,USB x 1
36
TPS51116RGER
INPUTS
OUTPUTS 0D85V_S0
PCB LAYER L1:Top L2:VCC L3:Signal
Mini-Card Wireless Lan+ Bluetooth
LPC I/F
L4:Signal L5:GND L6:Bottom
B
ACPI 1.1
KB,MS DON CONN
W
LPC Bus
W
Rear side USB2.0*3
Flash ROM 125KB
OUTPUTS
HDMI IN
25MHZ OSC
W
TOUCH
INPUTS
DCBATOUT
RTL8111GA
PCIE ports (6)
B
35
ISL95870BHRZ
LCD
PCIE x 1
.F
SATA ports (4)
VCC_GFXCORE
INPUTS SW
34
OUTPUTS
SYSTEM DC/DC
Int Digital MIC IN From Webcam
ETHERNET (10/100/1000Mb)
Front side Card Reader
VCC_CORE
DCBATOUT
LVDS
SW
ALC269
DCBATOUT
ISL95832HRTZ
Line out
IX
C
AM
FDIx2 (FDI Port for legacy VGA support on PCH)
OUTPUTS
INPUTS
D
32~33
INPUTS
SYSTEM DC/DC
LVDS
.C O
Nvidia N15S-GT
5V_AUX_S5 3D3V_AUX_S5 5V_Charger 3D3V_A
DCBATOUT
HDMI OUT DDIB
DDI
OUTPUTS
DDRIII Slot 0 1066/1333
M
D
31
RT8223MGQW INPUTS
SPI
SIO ITE8732
PCIE x 1
SATA x 2
LPC debug port
AspireLink
ODD
(SATA2_3Gb/s)
HDD
(SATA3_6Gb/s)
26
Temp Ctrl
A
A
Wistron Corporation Fan
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Scalar Ctrl Title 25 Size Custom Date:
5
4
3
2
BLOCK DIAGRAM
Document Number
Madrid
Tuesday, January 21, 2014
Rev
SA Sheet 1
2
of
68
A
PCH Strapping SPKR
4
Reboot option at power-up Default Mode: Internal weak Pull-down. No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ - 10-kΩ weak pull-up resistor. Weak internal pull-up. Leave as "No Connect".
GNT3#/GPIO55 GNT2#/GPIO53 GNT1#/GPIO51
GNT[3:0]# functionality is not available on Mobile. Mobile: Used as GPIO only Pull-up resistors are not required on these signals. If pull-ups are used, they should be tied to the Vcc3_3power rail. Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Disable Danbury:Left floating, no pull-down required.
NV_ALE
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm weak pull-up resistor [CRB has it pulled up with 1-kohm no-stuff resistor]
Processor Strapping
Disable Danbury:Leave floating (internal pull-down)
HDA_SDO
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
HDA_SYNC
Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
GPIO27
CFG[2]
PCI-Express Static Lane Reversal
1: 0:
.F
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with confidentiality Note : This is an un-muxed signal. This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. Sampled at rising edge of RSMRST#. CRB has a 1-kohm pull-up on this signal to +3.3VA rail.
CFG[4]
CFG[6:5]
CFG[7]
Normal Operation. Lane Numbers Reversed
3
Default Value
1
15 -> 0, 14 -> 1, ...
Disabled - No Physical Display Port attached to 1: Embedded DisplayPort.
0
Enabled - An external Display Port device is 0: connectd to the EMBEDDED display Port PCI-Express Port Bifurcation Straps
11 : x16 - Device 1 functions 1 and 2 disabled 10 : x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01 : Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00 : x8, x4, x4 - Device 1 functions 1 and 2 enabled
PEG DEFER TRAINING
1: PEG Train immediately following xxRESETB de assertion 1 0: PEG Wait for BIOS for training
11
2
W
GPIO8
Configuration (Default value for each bit is 1 unless specified otherwise)
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is enabled.
W
2
Strap Description
Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.
W
GPIO15
1
Low (0) - Flash Descriptor Security will be overridden. Also, when this signals is sampled on the rising edge of PWROK then it will also disable Intel ME and its features. High (1) - Security measure defined in the Flash Descriptor will be enabled. Platform design should provide appropriate pull-up or pull-down depending on the desired settings. If a jumper option is used to tie this signal to GND as required by the functional strap, the signal should be pulled low through a weak pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for strapping functions.
Huron River Schematic Checklist Rev.0_7
Pin Name
LA T
HAD_DOCK_EN# /GPIO[33]
DMI termination voltage. Weak internal pull-up. Do not pull low.
IX
NC_CLE
AM
3
E
Huron River Schematic Checklist Rev.0_7 Schematics Notes
INIT3_3V#
SPI_MOSI
D
M
Name
C
.C O
4
B
1
Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:
Table of Content
Document Number
Madrid
Tuesday, January 21, 2014
Rev
SA Sheet
3
of
68
5
4
3
2
1
DMI
20131010 Madrid SA Charles checked
3 OF 10 HASWELL
D
FDI 11 11
11 FDI_CSYNC 11 FDI_INT FDI_TX_DN[0..1] FDI_TX_DP[0..1] 14 14
CK_DP_DP CK_DP_DN
PEG_RXP0 PEG_RXN0
51 51
PEG_RXP1 PEG_RXN1
51 51
PEG_RXP2 PEG_RXN2
51 51
PEG_RXP3 PEG_RXN3
E15 F15 D14 E14 E13 F13 D12 E12 E11 F11
HDMIOUT
F10 G10 E9 F9 F8 G8 D3 D4 E4 E5 F5 F6 G4 G5 H5 H6 J4 J5 K5 K6 L4 L5
20131014 Madrid SA Charles need HDMIOUT 44 44 44 44 44 44 44 44
C
DDSP_B_TX_DATA0 DDSP_B_TX_DATA0# DDSP_B_TX_DATA1 DDSP_B_TX_DATA1# DDSP_B_TX_DATA2 DDSP_B_TX_DATA2# DDSP_B_TX_DATA3 DDSP_B_TX_DATA3#
1
V_VCCIOA_LOAD
B
EDP
R76 24D9R2F-L-GP
21 21 21 21
2
To SCALAR & 2136 Colay DPD_LANE0N_S DPD_LANE0P_S DPD_LANE1N_S DPD_LANE1P_S
TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U
TP37 TP35 TP34 TP38
1 1 1 1
DMI_IT_MR_DP0 DMI_IT_MR_DN0 DMI_IT_MR_DP1 DMI_IT_MR_DN1
U3 T3 U1 V1
DMI_IT_MR_DP2 DMI_IT_MR_DN2 DMI_IT_MR_DP3 DMI_IT_MR_DN3
W2 V2 Y3 W3
TP_PEG_D1 TP_PEG_C2 TP_PEG_B3 TP_PEG_A4 PEG_COMP
D1 C2 B3 A4 P3
PEG_RX0 PEG_RX#0
PEG_TX0 PEG_TX#0 PEG_TX1 PEG_TX#1
PEG_RX1 PEG_RX#1
PEG_TX2 PEG_TX#2
PEG_RX2 PEG_RX#2
PEG_TX3 PEG_TX#3
PEG_RX3 PEG_RX#3
PEG_TX4 PEG_TX#4
PEG_RX4 PEG_RX#4
PEG_TX5 PEG_TX#5
PEG_RX5 PEG_RX#5 PEG_RX6 PEG_RX#6 PEG_RX7 PEG_RX#7 PEG_RX8 PEG_RX#8 PEG_RX9 PEG_RX#9 PEG_RX10 PEG_RX#10 PEG_RX11 PEG_RX#11 PEG_RX12 PEG_RX#12 PEG_RX13 PEG_RX#13 PEG_RX14 PEG_RX#14 PEG_RX15 PEG_RX#15
PEG_TX6 PEG_TX#6 PEG_TX7 PEG_TX#7 PEG_TX8 PEG_TX#8 PEG_TX9 PEG_TX#9 PEG_TX10 PEG_TX#10 PEG_TX11 PEG_TX#11 PEG_TX12 PEG_TX#12 PEG_TX13 PEG_TX#13 PEG_TX14 PEG_TX#14 PEG_TX15 PEG_TX#15
DMI_RX0 DMI_RX#0 DMI_RX1 DMI_RX#1 DMI_RX2 DMI_RX#2 DMI_RX3 DMI_RX#3
DMI
DMI_TX0 DMI_TX#0 DMI_TX1 DMI_TX#1
RSVD_TP_D1 RSVD_TP_C2 RSVD_TP_B3 RSVD_TP_A4
DMI_TX2 DMI_TX#2
PEG_RCOMP
DMI_TX3 DMI_TX#3
A12 B12
PEG_TXP0_C C23 PEG_TXN0_C C24
(G) 1 (G) 1
2 SCD22U10V2KX-1GP 2 SCD22U10V2KX-1GP
B11 C11
PEG_TXP1_C C21 PEG_TXN1_C C22
(G) 1 (G) 1
2 SCD22U10V2KX-1GP 2 SCD22U10V2KX-1GP
C10 D10
PEG_TXP2_C C19 PEG_TXN2_C C20
(G) 1 (G) 1
2 SCD22U10V2KX-1GP 2 SCD22U10V2KX-1GP
B9 C9
PEG_TXP3_C C17 PEG_TXN3_C C18
(G) 1 (G) 1
2 SCD22U10V2KX-1GP 2 SCD22U10V2KX-1GP
51 51
PEG_TXP2 PEG_TXN2
51 51
PEG_TXP3 PEG_TXN3
51 51
TPAD28-1-GP-U TP54 TPAD28-1-GP-U TP60
D16 D18
FDI_COMP
R4
CK_DP_DN CK_DP_DP
U5 U6
1
DISP_UTIL_CPU
E16
1 1
TP_DISP_K11 TP_DISP_J12
K11 J12
FDI_TX_DN0 FDI_TX_DP0
B14 A14
FDI_TX_DN1 FDI_TX_DP1
C13 B13
TPAD28-1-GP-U TP40
A6 B6 B5 C5
DDIB_TXB0 DDIB_TXB#0 DDIB_TXB1 DDIB_TXB#1
FDI_CSYNC FDI_INT
DDIB_TXB2 DDIB_TXB#2 DDIB_TXB3 DDIB_TXB#3
DP_COMP SSC_DPLL_REF_CLK# SSC_DPLL_REF_CLK EDP_DISP_UTIL
DDIC_TXC0 DDIC_TXC#0 DDIC_TXC1 DDIC_TXC#1
FDI
RSVD_TP_K11 RSVD_TP_J12
DDIC_TXC2 DDIC_TXC#2 DDIC_TXC3 DDIC_TXC#3
FDI0_TX0#0 FDI0_TX00
DDID_TXD0 DDID_TXD#0 DDID_TXD1 DDID_TXD#1
FDI0_TX0#1 FDI0_TX01
DDID_TXD2 DDID_TXD#2 DDID_TXD3 DDID_TXD#3
20131010 Madrid SA Charles checked Connect to PCH 16,17
E1 E2 F2 F3 G1 G2 H2 H3 J1 J2 K2 K3 M2 M3 L1 L2 AA4 AA5
DMI_MT_IR_DP0 DMI_MT_IR_DN0
AB3 AB4
DMI_MT_IR_DP1 DMI_MT_IR_DN1
AC5 AC4
DMI_MT_IR_DP2 DMI_MT_IR_DN2
AC1 AC2
DMI_MT_IR_DP3 DMI_MT_IR_DN3
E17 F17 F18 G18
DDSP_B_TX_DATA0 DDSP_B_TX_DATA0# DDSP_B_TX_DATA1 DDSP_B_TX_DATA1#
G19 H19 F20 G20
DDSP_B_TX_DATA2 DDSP_B_TX_DATA2# DDSP_B_TX_DATA3 DDSP_B_TX_DATA3#
HDMIOUT
D19 E19 C20 D20 D21 E21 C22 D22 B15 C15 A16 B16 B17 C17 A18 B18
DP
20131010 Madrid SA Charles Madrid has no DP
eDP Scalar & LVDS Transmiter DPD_LANE0P_S DPD_LANE0N_S DPD_LANE1P_S DPD_LANE1N_S C
20131007 Madrid SA Charles canncel 3&4 pairs
20131027 CM B
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Date:
3
D
HASWE1NFU (62.10055.761)
IX .F
4
PEG_TXP1 PEG_TXN1
B7 C7
W
5
W
20131007 Madrid SA Charles change Net to follow Pisa2 eDP Net Colay in Sheet 31,32,47
W
A
51 51
C8 D8
HASWE1NFU (62.10055.761)
20131010 Madrid SA Charles checked Connect to PCH 16,17
PEG_TXP0 PEG_TXN0
FDI_CSYNC R77 24D9R2F-L-GP FDI_INT
M
CPU1C
51 51
HASWELL 1
GPU PEG BUS
4 OF 10
CPU1D
V_VCCIOA_LOAD
2
DMI_MT_IR_DP[0..3] DMI_MT_IR_DN[0..3]
20131010 Madrid SA Charles checked p73
.C O
11 11
2013/04/03 Rossi delete PCIEX16 signal
AM
DMI_IT_MR_DP[0..3] DMI_IT_MR_DN[0..3]
LA T
11 11
2
CPU uLGA (DMI/FDI)
Document Number
Rev
SA
Madrid
Tuesday, January 21, 2014
Sheet 1
4
of
68
A
5
4
3
2
1
DDR DATA 9 10
M_A_DQ[0..63] M_B_DQ[0..63]
9 9
M_A_DQS[0..7] M_A_DQS#[0..7]
10 10
M_B_DQS[0..7] M_B_DQS#[0..7]
2013/04/10 Rossi Change DIMM Net name reference swift
D
DDR CMD/ADD M_A_A[0..15] M_B_A[0..15]
9 9 9 9
M_A_DIM0_CLK_DDR0 M_A_DIM0_CLK_DDR#0 M_A_DIM0_CLK_DDR1 M_A_DIM0_CLK_DDR#1
10 10 10 10
B
M_B_DIM0_CLK_DDR0 M_B_DIM0_CLK_DDR#0 M_B_DIM0_CLK_DDR1 M_B_DIM0_CLK_DDR#1
DDR OTHERS 33 10 9
SM_DRAMRST#
M_VREF_DQ_DIMM1_C M_VREF_DQ_DIMM0_C
SA_CS#0 SA_CS#1 SA_CS#2 SA_CS#3 SA_CK0 SA_CK#0 SA_CK1 SA_CK#1 SA_CK2 SA_CK#2 SA_CK3 SA_CK#3 RSVD_AW12
M_A_DIM0_CKE0 M_A_DIM0_CKE1
AU14 AV9 AU10 AW8
M_A_DIM0_CS#0 M_A_DIM0_CS#1
AY15 AY16 AW15 AV15 AV14 AW14 AW13 AY13
M_A_DIM0_CLK_DDR0 M_A_DIM0_CLK_DDR#0 M_A_DIM0_CLK_DDR1 M_A_DIM0_CLK_DDR#1
AW12
TP_RSVD_AW12
2013/04/10 Rossi del
2013/04/10 Rossi del
2013/04/10 Rossi del
1
TP110 TPAD28-1-GP-U
SA_WE#
RSVD_AW27 SA_CAS#
SM_DRAMRST#
M_A_RAS# M_A_WE#
AV20
TP_RSVD_AV20
1
TP107 TPAD28-1-GP-U
AW27
TP_RSVD_AW27
1
TP104 TPAD28-1-GP-U
AU9
M_A_CAS#
AK22
SM_DRAMRST#
(R) C420 SCD1U10V2KX-5GP
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
SB_CK0 SB_CK#0 SB_CK1 SB_CK#1 SB_CK2 SB_CK#2 SB_CK3 SB_CK#3 SB_CAS# RSVD_AL20 SB_RAS# SB_WE# SA_DIMM_VREFDQ SB_DIMM_VREFDQ
M_B_BS0 M_B_BS1 M_B_BS2
AW29 AY29 AU28 AU29
M_B_DIM0_CKE0 M_B_DIM0_CKE1
AP17 AN15 AN17 AL15
M_B_DIM0_CS#0 M_B_DIM0_CS#1
AM20 AM21 AP22 AP21
M_B_DIM0_CLK_DDR0 M_B_DIM0_CLK_DDR#0 M_B_DIM0_CLK_DDR1 M_B_DIM0_CLK_DDR#1
2013/04/10 Rossi del
2013/04/10 Rossi del
AN20 AN21 AP19 AP20
2013/04/10 Rossi del
AP16 AL20 AM18 AK16
M_B_CAS#
AB39 AB40
M_VREF_DQ_DIMM0_C M_VREF_DQ_DIMM1_C
B
M_B_RAS# M_B_WE#
M HASWE1NFU (62.10055.761)
M_VREF_DQ_DIMM0_R
RSVD_AV20
AU12
AU11
SB_CS#0 SB_CS#1 SB_CS#2 SB_CS#3
Can be left as no connects if no support ECC.
AK17 AL18 AW28
C71 SCD022U16V2JX-GP
SA_RAS#
SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3
C
R104 24D9R2F-L-GP
R105 24D9R2F-L-GP
W
AV22 AT23 AU22 AU23
SB_BS0 SB_BS1 SB_BS2
2013/04/10 Rossi del
AM26 AM25 AP25 AP26 AL26 AL25 AR26 AR25
M_VREF_DQ_DIMM1_R
HASWE1NFU (62.10055.761)
M_A_BS0 M_A_BS1 M_A_BS2
M_B_DIM0_ODT0 M_B_DIM0_ODT1
C73 SCD022U16V2JX-GP
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3
Can be left as no connects if no support ECC.
AV12 AY11 AT21
AM17 AL16 AM16 AK15
2
DDR CLOCK
SA_BS0 SA_BS1 SA_BS2
SB_ECC_CB0 SB_ECC_CB1 SB_ECC_CB2 SB_ECC_CB3 SB_ECC_CB4 SB_ECC_CB5 SB_ECC_CB6 SB_ECC_CB7
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
1
M_B_DIM0_ODT0 M_B_DIM0_ODT1
SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3
AL19 AK23 AM22 AM23 AP23 AL23 AY24 AV25 AU26 AW25 AP18 AY25 AV26 AR15 AV27 AY28
1
10 10
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15
2
M_B_DIM0_CKE0 M_B_DIM0_CKE1
HASWELL
2
10 10
2013/04/10 Rossi del
AW33 AV33 AU31 AV31 AT33 AU33 AT31 AW31
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS8 SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7 SB_DQS#8
1
M_B_DIM0_CS#0 M_B_DIM0_CS#1
M_A_DIM0_ODT0 M_A_DIM0_ODT1
AE34 AE35 AG35 AH35 AD34 AD35 AG34 AH34 AL34 AL35 AK31 AL31 AK34 AK35 AK32 AL32 AN34 AP34 AN31 AP31 AN35 AP35 AN32 AP32 AM29 AM28 AR29 AR28 AL29 AL28 AP29 AP28 AR12 AP12 AL13 AL12 AR13 AP13 AM13 AM12 AR9 AP9 AR6 AP6 AR10 AP10 AR7 AP7 AM9 AL9 AL6 AL7 AM10 AL10 AM6 AM7 AH6 AH7 AE6 AE7 AJ6 AJ7 AF6 AF7 AF35 AL33 AP33 AN28 AN12 AP8 AL8 AG7 AN25 AF34 AK33 AN33 AN29 AN13 AR8 AM8 AG6 AN26
1
10 10
SA_ECC_CB0 SA_ECC_CB1 SA_ECC_CB2 SA_ECC_CB3 SA_ECC_CB4 SA_ECC_CB5 SA_ECC_CB6 SA_ECC_CB7
AW10 AY8 AW9 AU8
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ17 M_B_DQ21 M_B_DQ19 M_B_DQ23 M_B_DQ20 M_B_DQ16 M_B_DQ18 M_B_DQ22 M_B_DQ25 M_B_DQ28 M_B_DQ27 M_B_DQ30 M_B_DQ24 M_B_DQ29 M_B_DQ26 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ45 M_B_DQ41 M_B_DQ47 M_B_DQ43 M_B_DQ44 M_B_DQ40 M_B_DQ46 M_B_DQ42 M_B_DQ52 M_B_DQ53 M_B_DQ50 M_B_DQ55 M_B_DQ48 M_B_DQ49 M_B_DQ54 M_B_DQ51 M_B_DQ61 M_B_DQ60 M_B_DQ59 M_B_DQ63 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ62 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
2
C
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
.C O
M_A_DIM0_ODT0 M_A_DIM0_ODT1
SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3
2 OF 10
CPU1B
AU13 AV16 AU16 AW17 AU17 AW18 AV17 AT18 AU18 AT19 AW11 AV19 AU19 AY10 AT20 AU21
AM
9 9
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15
LA T
M_A_DIM0_CS#0 M_A_DIM0_CS#1 M_A_DIM0_CKE0 M_A_DIM0_CKE1
HASWELL
IX
9 9
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS8 SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7 SA_DQS#8
.F
DDR CTRL
AD38 AD39 AF38 AF39 AD37 AD40 AF37 AF40 AH40 AH39 AK38 AK39 AH37 AH38 AK37 AK40 AM40 AM39 AP38 AP39 AM37 AM38 AP37 AP40 AV37 AW37 AU35 AV35 AT37 AU37 AT35 AW35 AY6 AU6 AV4 AU4 AW6 AV6 AW4 AY4 AR1 AR4 AN3 AN4 AR2 AR3 AN2 AN1 AL1 AL4 AJ3 AJ4 AL2 AL3 AJ2 AJ1 AG1 AG4 AE3 AE4 AG2 AG3 AE2 AE1 AE39 AJ39 AN39 AV36 AV5 AP3 AK3 AF3 AV32 AE38 AJ38 AN38 AU36 AW5 AP2 AK2 AF2 AU32
1
10 M_B_WE# 10 M_B_CAS# 10 M_B_RAS# 10 M_B_BS0 10 M_B_BS1 10 M_B_BS2
9 9
1 OF 10
CPU1A M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ9 M_A_DQ13 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ8 M_A_DQ14 M_A_DQ15 M_A_DQ17 M_A_DQ21 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ16 M_A_DQ22 M_A_DQ23 M_A_DQ25 M_A_DQ29 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ24 M_A_DQ30 M_A_DQ31 M_A_DQ33 M_A_DQ37 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ32 M_A_DQ38 M_A_DQ39 M_A_DQ41 M_A_DQ45 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ40 M_A_DQ46 M_A_DQ47 M_A_DQ49 M_A_DQ53 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ48 M_A_DQ54 M_A_DQ55 M_A_DQ57 M_A_DQ61 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ56 M_A_DQ62 M_A_DQ63 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
2
9 M_A_WE# 9 M_A_CAS# 9 M_A_RAS# M_A_BS0 M_A_BS1 M_A_BS2
W
9 9 9
W
9 10
D
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size C Date: 5
4
3
2
CPU uLGA (DDR)
Document Number
Madrid
Tuesday, January 21, 2014
1
Rev
SA Sheet
5
of
68
5
VCC
PCH_1D05V 7
4
1
R91
2 0R0402-PAD
PCH_1D05V
1
(R)
3
2
1
2 0R2J-2-GP
VCCST V_CPU_VCCIO2PCH
P_CPU_VCCIO
PWRGD_3V 2
12,13,20
R63
VCC_CORE
R87 0R0603-PAD-1-GP-U
VCC_CORE
6 OF 10
CPU1F
8 OF 10
CPU1H HASWELL
1
LA T 2
2
1 2
2 1
C67 SC22U6D3V5MX-2GP
VSS VSS VSS VSS VSS VSS VSS
1 1
TP79 TPAD28-1-GP-U TP61 TPAD28-1-GP-U
TP_RSVD_P37 TP_RSVD_N38
1 1
TP69 TPAD28-1-GP-U TP75 TPAD28-1-GP-U
R36 C39
TP_RSVD_R36 TP_RSVD_C39
1 1
TP77 TPAD28-1-GP-U TP36 TPAD28-1-GP-U
U35 P40 D
R38 T37 V34 R39 T38 U36 P39 T36 R37 J14 N36
TP_CPU_N36
1
TP65 TPAD28-1-GP-U
R578 1
R583 2
1
2K67R2F-2-GP
2
PWRGD_3V
6K04R2F-GP
Vcore
22uf 0805
V_SM
22uf 0805
22 4+5(R)
(R) C364 SC22U6D3V5MX-2GP
B
C66 SC22U6D3V5MX-2GP
C50 SC22U6D3V5MX-2GP
1
3D3V_S0
R82 10KR2F-2-GP (R)
C483 SC10U6D3V3MX-GP
2
1
CPU Power Capacitor Quantity Net CAP AMOUNT
7 VCORE_PWRGD
VCC_CORE
R78
1
(R)
2 10KR2F-2-GP
R75
1
(R)
2 10KR2F-2-GP
PWR_DEBUG
PWR_DEBUG
PWR_DEBUG_N
Q10 6 5 4
1 2 PWR_DEBUG_1
3
MBT3904DW1T1G-2-GP (R) (R) C380 SCD1U16V2ZY-2GP
2
(R) R558 0R2J-2-GP
1
VCORE_PWRGD
2
7,13,35,41
P_CPU_VCCIO
2
C15 SC4D7U6D3V3KX-GP
W
1
(R) C366 SC22U6D3V5MX-2GP
A
2
(R) C360 SC22U6D3V5MX-2GP
1
1
(R) C361 SC22U6D3V5MX-2GP
2
1
(R) C362 SC22U6D3V5MX-2GP
2
2
1
VCC_CORE
C53 SC22U6D3V5MX-2GP
(R) C363 SC22U6D3V5MX-2GP
Wistron Corporation
2
1
C46 SC22U6D3V5MX-2GP
2
1
C48 SC22U6D3V5MX-2GP
2
A
2
1
1
VCC_CORE
VSS VSS
TP_RSVD_K12 TP_RSVD_J13
P37 N38
2
C484 SC10U6D3V3MX-GP
W
PLACE CAPS AT TOP SOCKET EDGE
RSVD_TP_R36 RSVD_TP_C39
K12 J13
C
W
20131128 Madrid SB Charles NB team cost review
RSVD_TP_P37 RSVD_TP_N38
RSVD_AY18 RSVD_AW24 RSVD_AW23 RSVD_AV29 RSVD_AV24 RSVD_AU39 RSVD_AU27 RSVD_AU1 RSVD_AT40 RSVD_AK20 RSVD_Y7 RSVD_T34 RSVD_R34 RSVD_J40 RSVD_J17 RSVD_J15 RSVD_H12
DEFENSIVE DESIGN PWR_DEBUG
.F
2
(R) C367 SC22U6D3V5MX-2GP
(R) C365 SC22U6D3V5MX-2GP
2
C49 SC22U6D3V5MX-2GP
1
1
C59 SC22U6D3V5MX-2GP
IX
1
1
C47 SC22U6D3V5MX-2GP
2
2 1
C78 SC10U6D3V3MX-GP
2
2 1
C79 (R) SC22U6D3V5MX-2GP
2
1
C105 SC10U6D3V3MX-GP
2
1
2
1
(R) C701 SC22U6D3V5MX-2GP
2
C183 SC10U6D3V3MX-GP
2
1
C103 SC10U6D3V3MX-GP
2
C182 (R) SC10U6D3V3MX-GP
2
1
1D5V_S3
1
2
1
1
VCC_CORE
(R) C700 SC22U6D3V5MX-2GP
C60 SC22U6D3V5MX-2GP
2
1
C51 SC22U6D3V5MX-2GP
1
1
C45 SC22U6D3V5MX-2GP
C61 SC22U6D3V5MX-2GP
2
C68 SC22U6D3V5MX-2GP
2
1
C52 SC22U6D3V5MX-2GP
2
1
1 2
2
2
1
1
VCC_CORE
C63 SC22U6D3V5MX-2GP
1 1 1 1 1 1
M 1D5V_S3
VCC_CORE
C64 SC22U6D3V5MX-2GP
TP83 TP82 TP53 TP48 TP63 TP67
AY18 AW24 AW23 AV29 AV24 AU39 AU27 AU1 AT40 AK20 Y7 T34 R34 J40 J17 J15 H12
HASWE1NFU (62.10055.761)
PLACE ALL 0805 CAPS INSIDE CPU SOCKET CAVITY
C65 SC22U6D3V5MX-2GP
TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U
TP_RSVD_AY18 TP_RSVD_AW24 TP_RSVD_AW23 TP_RSVD_AV29 TP_RSVD_AV24 TP_RSVD_AU39 TP_RSVD_AU27 TP_RSVD_AU1 TP_RSVD_AT40 TP_RSVD_AK20 VCCST_PWRGD TP_RSVD_T34 TP_RSVD_R34 TP_RSVD_J40 TP_RSVD_J17 TP_RSVD_J15 TP_RSVD_H12
VSS RSVD_TP_N36
HASWE1NFU (62.10055.761)
B
1 1 1 1 1 1 1 1 1 1
1
C
TP109 TP106 TP108 TP103 TP101 TP100 TP97 TP99 TP96 TP93
RSVD_TP_K12 RSVD_TP_J13
VSS VSS
AJ12 AJ13 AJ15 AJ17 AJ20 AJ21 AJ24 AJ25 AJ28 AJ29 AJ9 AT17 AT22 AU15 AU20 AU24 AV10 AV11 AV13 AV18 AV23 AV8 AW16 AY12 AY14 AY9
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U
.C O
D
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
HASWELL
C31 C33 L16 L15 J35 H33 H35 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J32 J34 K19 K21 K23 K25 K27 K29 K31 M13 K33 K35 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L32 L33 M17 M15 M19 M21 M23 M25 M27 M29 M33
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCCST_PWRGD
L31 L18 L17 J33 A24 A25 A26 A27 A28 A29 A30 G33 B25 B27 B29 B31 J31 B33 G31 B35 C24 C25 C26 C27 C28 C29 C30 C32 C34 C35 D25 D27 D29 D31 E33 D33 E31 D35 E24 E25 E26 E27 E28 E29 E30 E32 E34 F23 F25 F27 F29 F31 E35 F33 F35 G22 G23 G24 G25 G26 G27 G28 G29 G30 G32 G34 G35 H23 H25 H27 H29 H31 L34
VCC_CORE
C43 SC4D7U6D3V3KX-GP
VCC VCCIO_OUT VCCIO2PCH
AM
P8 2 0R0402-PAD V_CPU_VCCIO_OUT L40 AB8 VCCIO2PCH
1
2 0R2J-2-GP
2
(R)
1
1
1
2
C40 SCD1U16V2ZY-2GP
2
1
R86
2
1
R64 1
VCCST
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size D Date:
5
4
3
2
CPU uLGA (VCC)
Document Number
Madrid
Tuesday, January 21, 2014 1
Rev
SA Sheet
6
of
68
5
4
CLOCK
H_VIDSCK
H_VIDSOUT_VR
R48
1
2 0R0402-PAD
H_VIDSOUT
H_VIDALERT_N_VR
R38
1
2 0R0402-PAD
H_VIDALERT_N
1
R51
(R)
CK_PE_100M_MCP_DN CK_PE_100M_MCP_DP
2 90D9R2F-1-GP H_VIDSCK H_VIDSOUT H_VIDALERT_N
R50 1 R49 1 R277 1
H_DRAMPWRGD R70
1
(R)
1
XDP
(R) R67 665R2F-2-GP
(R) R68 43R2J-GP
(R) C32 SCD1U16V2ZY-2GP
1
Defensive Design
+V_SM_VREF_CNT_1
R69 75R2J-1-GP (R)
9,10
2 150KR2J-GP
(R)
2 1K3R2F-1-GP
Q78 PLT_RST#
H_PM_SYNC_0 H_THERMTRIP_N H_PECI 12 PLTRST_CPU_N
R747 1
(R) C569 SC100P50V2JN-3GP
2013/04/09 Connect to PCH/SIO
H_PROCHOT_N
1 2
PLTRST_N_R
6 PLTRST_CPU_N1 R795 2
5 4
3
MBT3904DW1T1G-2-GP (R)
(R)
1 100KR2J-1-GP
2013/04/09 Rossi reserved JTAG
+V_SM_VREF_CNT TPAD28-1-GP-U TP33 TPAD28-1-GP-U TP59 TPAD28-1-GP-U TP39
FP_RST_DBR_N XDP_DBRESET_N R568 2
1 1 1 1 R42
1 49D9R2F-GP 1 1
PM_SYNC PECI
SM_VREF
AA37 Y38 AA36 W38 V39 U39 U40 V38 T40 Y35 AA34 V37 Y34 U38 W34 V35
HSW_PCUSTB_0_DP HSW_PCUSTB_0_DN HSW_PCUSTB_1_DP HSW_PCUSTB_1_DN
Y36 Y37 V36 W36
H_TCK H_TDI H_TDO H_TMS
D39 F38 F39 E39
H_TRST_N H_PRDY_N H_PREQ_N 2 0R0402-PAD
E37 L39 L37 G40
TESTLOW_2 TP_RSVD_K8 TP_RSVD_J10
THERMAL
CATERR# PROCHOT# THERMTRIP# SKTOCC#
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG17 CFG16 CFG19 CFG18 TCK TDI TDO TMS
JTAG
TESTLO_N5 RSVD_TP_K8 RSVD_TP_J10
RSVD_N35 DPLL_REF_CLK# DPLL_REF_CLK CFG_RCOMP
HASWE1NFU (62.10055.761)
1
2 0R0402-PAD
H_PROCHOT_R_N
H_THERMTRIP_N
R552 1
2 0R0402-PAD
CPU_THERMTRIP_N
2013/04/09 Rossi reserved JTAG P/H, P/L pin
B
3D3V_S0
2
PLace Near CPU
H_TDO
1
2 1
(R) R57 100R2F-L1-GP-U
2
2
(R) R41 825R2F-GP
R551 1
P_CPU_VCCIO (R) R37 249R2F-GP
R36 51R2F-2-GP
1 1 1 1 1 1 1 1 1 1
P6 K9 H15 J9 H14 M8 AV2 J16 H16 N40 N39 V7 AB6 K13 J8 R1 P1 R2 AB36 AW2 AV1 AC8 P4 U8 AB33 T8 Y8 M10 L10 M11 L12 W8 R33 P33 E40
TESTLOW_1 VCCST TP_RSVD_H15 TP_RSVD_J9 TP_RSVD_H14
1 1 1
TP_RSVD_AV2 TP_RSVD_J16 TP_RSVD_H16 PWR_DEBUG TP_RSVD_V7 TP_RSVD_AB6 TP_RSVD_K13 TP_RSVD_J8 DDR_RCOMP_0 DDR_RCOMP_1 DDR_RCOMP_2 TP_RSVD_AB36 TP_RSVD_AW2 TP_RSVD_AV1 TP_RSVD_AC8
R563
TP42 TP50 TP41 TP44 TP45 TP52 TP56 TP51 TP78 TP62
TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U
TP43 TP49 TP71
TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U
TP98 TP47 TP58
TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U
1
2
TP_RSVD_U8 TP_RSVD_AB33 CPU_VSS_T8 TP_RSVD_Y8 TP_RSVD_M10 TP_RSVD_L10 TP_RSVD_M11 TP_RSVD_L12 TP_RSVD_W8 TP_RSVD_R33 TP_RSVD_P33 VCC_SENSE
N33 J11 M9 J7 F40
VSS_SENSE
N35 W6 W5 H40
V_1P05_PECI_VCOM CK_DPNS_R_DN CK_DPNS_R_DP TPEV_CFG_RCOMP
R54
1
R53
1
(R)
(R)
2 51R2J-2-GP
H_TMS
2 51R2J-2-GP
H_TCK
2 51R2J-2-GP
R589 1 R596 1
1 1 R72 R71 R79
1 1 1 1
2 0R0402-PAD 2 0R0402-PAD TP70 TPAD28-1-GP-U TP55 TPAD28-1-GP-U 1 2 100R2F-L1-GP-U 1 2 75R2F-2-GP 1 2 100R2F-L1-GP-U TP86 TPAD28-1-GP-U TP105 TPAD28-1-GP-U TP102 TPAD28-1-GP-U TP88 TPAD28-1-GP-U
1 1
TP81 TP87
1 1 1 1 1 1 1 1
TP85 TP74 TP64 TP80 TP72 TP84 TP76 TP68
1
TP73
V_VCCIOA_LOAD TPAD28-1-GP-U TPAD28-1-GP-U (R) R571 1 2 0R2J-2-GP TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U
TPAD28-1-GP-U
R60 49D9R2F-GP
1
2012/04/05 SB BOM Change 1k47 to 3k3
D
P_CPU_VCCIO
1
2 51R2J-2-GP
H_PROCHOT_R_N
R553 1
2 1KR2J-1-GP
CPU_THERMTRIP_N
R96
1
PCH_1D05V
2 10KR2J-3-GP 2 (R) 1
C57 R73
1
R74
2
(R)
H_PWRGD 2010/12/20 SB Add EMI Cap
SCD1U16V2ZY-2GP
2 150R2F-1-GP
PWR_DEBUG
1 10KR2J-3-GP
3D3V_S5
2 10KR2J-3-GP H_SKTOCC_PU
R765 1
2 0R2J-2-GP H_SKTOCC_N R753
1
C
MCP TERMINATION HSW_PCUDEBUG_0
R585 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_1
R576 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_2
R582 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_3
R570 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_4
R562 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_5
R556 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_6
R559 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_7
R566 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_8
R555 1
HSW_PCUDEBUG_9
(R)
2 1KR2J-1-GP
R591 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_10 R594 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_11 R560 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_12 R561 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_14 R565 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_15 R569 1
(R)
2 1KR2J-1-GP
HSW_PCUDEBUG_13
R557 1
2 1KR2J-1-GP
2013/04/09 HSW_PCUDEUG[0-15] P/L reserved
20131106 Madrid SA Charles Set CFG[6:5] as 1x16
B
HSW_STRAP_13
PCH Strap
H_TRST_N VCC_SENSE R56
PLace Any where
.F
PLace Near XDP CONN
H_DRAMPWRGD
VCC_CORE
1 1 1
H_TCK TERMINATION PLACE NEAR CPU WITHIN 1.1 INCH R554 1
2 1K8R2F-GP
R266 3K3R2J-3-GP
R62
H_TDI
2 51R2J-2-GP
R284 1
49D9R2F-GP
PLace Near XDP CONN
1
1
P_CPU_VCCIO
TP_CPU_G39 TP_CPU_J39 TP_CPU_G38 TP_CPU_H37 TP_CPU_H38 TP_CPU_J38 TP_CPU_K39 TP_CPU_K37 TP_CPU_T35 TP_CPU_M38
IX
R61
G39 J39 G38 H37 H38 J38 K39 K37 T35 M38
LA T
THERMAL H_PROCHOT_N
TESTLO_P6 RSVD_K9 RSVD_H15 RSVD_J9 RSVD_H14 VCC_M8 RSVD_AV2 RSVD_TP_J16 RSVD_TP_H16 PWR_DEBUG VSS VSS VSS RSVD_TP_K13 RSVD_TP_J8 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 RSVD_AB36 RSVD_TP_AW2 RSVD_TP_AV1 RSVD_AC8 VCOMP_OUT RSVD_U8 RSVD_AB33 RSVD_T8 RSVD_Y8 RSVD_M10 RSVD_L10 RSVD_M11 RSVD_L12 RSVD_W8 RSVD_R33 RSVD_P33 VCC_SENSE VSS VSS VSS VSS VSS_SENSE
TRST# PRDY# PREQ# DBR#
N5 K8 J10
BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 RSVD_T35 RSVD_M38
AM
TPAD28-1-GP-U TP46 TPAD28-1-GP-U TP66
SM_DRAMPWROK PWRGOOD RESET#
AB38 HSW_PCUDEBUG_0 HSW_PCUDEBUG_1 HSW_PCUDEBUG_2 HSW_PCUDEBUG_3 HSW_PCUDEBUG_4 HSW_PCUDEBUG_5 HSW_PCUDEBUG_6 HSW_PCUDEBUG_7 HSW_PCUDEBUG_8 HSW_PCUDEBUG_9 HSW_PCUDEBUG_10 HSW_PCUDEBUG_11 HSW_PCUDEBUG_12 HSW_PCUDEBUG_13 HSW_PCUDEBUG_14 HSW_PCUDEBUG_15
2
(R)
1
34,41
3D3V_S5 VCORE_PWRGD R797 1
CK_DPNS_R_DN CK_DPNS_R_DP VCORE_PWRGD
2
C
PLTRST_CPU_N2
R622 24D9R2F-L-GP
12 12,54 12,20
1
2
H_PWRGD PLT_RST#
13 H_SKTOCC_N 13 FP_RST_DBR_N 13 H_DRAMPWRGD 14 14 6,13,35,41
M36 K38 F37 D38
2
1
VCCST PWR_DEBUG
C467
6
13,41 11,20,50
P36 N37
TP_H_CATERR_N H_PROCHOT_R_N CPU_THERMTRIP_N H_SKTOCC_N
HASWELL
VIDSCLK VIDSOUT VIDALERT#
AK21 AB35 M39
H_PM_SYNC_0 H_PECI
+V_SM_VREF_CNT P_CPU_VCCIO
SCD022U16V2JX-GP
OTHER 6
TP57 TPAD28-1-GP-U
2
2
2
HSW_STRAP_13
BCLK# BCLK
C38 C37 B37
H_DRAMPWRGD_CPU H_PWRGD H_CPURST_N
2 0R0402-PAD 1
PLTRST_CPU_N
V4 V5
H_VIDALERT_N_1
2 44D2R2F-GP 2 100R2J-2-GP 2 0R0402-PAD
5 OF 10
CPU1E
1D5V_S3
2
2 0R0402-PAD
2013/04/09 Rossi delete XDP_MBP
M
1
2 110R2F-GP
1
R52
2 75R2F-2-GP
1
2
H_VIDSCK_VR H_VIDSOUT_VR H_VIDALERT_N_VR
H_VIDSCK_VR
1
R47
.C O
41 VCC_SENSE 41 VSS_SENSE
16
SM_DRAMPWROK
R39
1
CPU_VCORE
D
1
2012/04/05 SB BOM Change 681 to 1k8 MINIMIZE STUB BETWEEN THESE AND RESISTORS AT SINAL PAGE PLACE IN CRB AREA
41 41 41
2
P_CPU_VCCIO
CK_PE_100M_MCP_DP CK_PE_100M_MCP_DN
1
14 14
3
1
(R)
2 49D9R2F-GP VSS_SENSE
HSW_PCUSTB_0_DP
R592 1
(R)
2 1KR2J-1-GP
HSW_PCUSTB_0_DN
R584 1
(R)
2 1KR2J-1-GP
HSW_PCUSTB_1_DP
R575 1
(R)
2 1KR2J-1-GP
HSW_PCUSTB_1_DN
R581 1
(R)
2 1KR2J-1-GP
XDP_DBRESET_N
2
1
CLOSE TO CPU
C26 SCD1U16V2ZY-2GP
A
4
W
5
W
W
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Date: 3
2
CPU uLGA (VCORE/XDP)
Document Number
Madrid
Tuesday, January 21, 2014 1
Rev
SA Sheet
7
of
68
5
4
HASWE1NFU (62.10055.761)
7 OF 10
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
10 OF 10
CPU1J
HASWELL AP11 AP14 AP15 AP24 AP27 AP30 AP36 AP4 AP5 AR11 AR14 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR27 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR39 AR40 AR5 AT1 AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT2 AT24 AT25 AT26 AT27 AT28 AT29 AT3 AT30 AT32 AT34 AT36 AT38 AT39 AT4 AT5 AT6 AT7 AT8 AT9 AU2 AU25 AU3 AU30 AU34 AU38 AU5 AU7 AV21 AV28 AV3 AV30 AV34 AV38 AV7 AW26 AW3 AW30
HASWELL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AW32 AW34 AW36 AW7 AY17 AY23 AY26 AY27 AY30 AY5 AY7 B24 B26 B28 B30 B34 B36 B4 B8 C4 C6 C12 C14 C16 C18 C19 C21 C23 C36 B10 B23 C3 D9 D11 D13 D15 D17 D2 D23 D24 D26 D28 D30 D34 D36 D37 D5 D6 D7 E7 E8 E10 E18 E3 E20 E22 E23 E36 E38 B32 E6 F1 F32 F12 F14 F16 F19 F21 F22 F24 F26 F28 F30 F34 F36 F4 D32 F7 G9 G11
G3 G6 G7 G12 G13 G14 G15 G16 G17 G21 G36 G37 H1 H4 H7 H8 H9 H10 H11 H13 H17 H18 H20 H21 H22 H24 H26 H28 H30 H32 H34 H36 H39 J3 J6 J18 J19 J20 J36 J37 K1 K4 K7 K10 K14 K17 K18 K20 K22 K24 K26 K28 K30 K34 K36 K40 L3 L6 L7 L8 L9 L11 L13 L14 L35 L38 M1 M12 M14 M16 M18 M20 M22 M24 M26 M28 M30 M32 M34 M37
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
HASWE1NFU (62.10055.761)
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS_NCTF_AU40 VSS_NCTF_AV39 VSS_NCTF_AW38 VSS_NCTF_AY3 VSS_NCTF_B38 VSS_NCTF_B39 VSS_NCTF_C40 VSS_NCTF_D40
K15 K16 K32 L36 M4 M5 M6 M7
D
M35 M40 N1 N2 N3 N4 N6 N7 N8 N34 P2 P5 P7 P34 P35 P38 R3 R5 R6 R7 R8 R35 R40 T1 T2 T4 T5 T6 T7 T33 T39 U2 U4 U7 U33 U34 U37 V3 V6 V8 V33 V40 W1 W4 W7 W33 W35 W37 Y4 Y5 Y6 Y33
M
CPU1G AJ5 AJ8 AJ34 AJ35 AJ36 AJ37 AJ40 AK1 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK18 AK19 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK36 AL5 AL11 AL14 AL17 AL21 AL22 AL24 AL27 AL30 AL36 AL37 AL38 AL39 AL40 AM1 AM2 AM3 AM4 AM5 AM11 AM14 AM15 AM19 AM24 AM27 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN14 AN16 AN18 AN19 AN22 AN23 AN24 AN27 AN30 AN36 AN37 AN40 AP1
.C O
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
C
AM
C
HASWELL
2
AU40 AV39 AW38 AY3 B38 B39 C40 D40
LA T
D
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
NCTF TEST PIN: AU40, AV39,AW38,AY3,B38,B39,C40,D40
9 OF 10
CPU1I A5 A7 A11 A13 A15 A17 A23 AA3 AA6 AA7 AA8 AA33 AA35 AA38 AB5 AB7 AB34 AB37 AC3 AC6 AC7 AC33 AC34 AC35 AC36 AC37 AC38 AC39 AC40 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD33 AD36 AE5 AE8 AE33 AE36 AE37 AE40 AF1 AF4 AF5 AF8 AF33 AF36 AG5 AG8 AG33 AG36 AG37 AG38 AG39 AG40 AH1 AH2 AH3 AH4 AH5 AH8 AH33 AH36 AJ11 AJ14 AJ16 AJ18 AJ19 AJ22 AJ23 AJ26 AJ27 AJ30 AJ31 AJ32 AJ33
3
HASWE1NFU (62.10055.761)
B
W
W
W
.F
IX
B
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size D Date: 5
4
3
2
CPU uLGA (VCC)
Document Number
Madrid
Tuesday, January 21, 2014 1
Rev
SA Sheet
8
of
68
5
4
3
2
1
DIMM1
30
DDR3_DRAMRST# 0D75V_S0
H =8mm
203 204
VREF_CA VREF_DQ RESET# VTT1 VTT2
M
4
1
1 2
1 2
1
1
2
C
1 M_VREF_DQ_DIMM0
R148 1 2 0R0603-PAD-1-GP-U
M_VREF_DQ_DIMM0_C
5
1
R149 1KR2F-3-GP
Tracew should be at least 20 mils wide
2
2
C110
B
1
1D5V_S3
R188 1KR2F-3-GP M_VREF_CA_DIMM0
R196 1 2 0R0603-PAD-1-GP-U
7,10
1
+V_SM_VREF_CNT
Tracew should be at least 20 mils wide
C140
2
R185 1KR2F-3-GP
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom
DDR3-204P-101-GP-U (62.10017.K01)
Date: 5
Layout Note: Place these Caps near SO-DIMMA.
R151 1KR2F-3-GP
1
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206
20131128 Madrid SB Charles NB team cost review
1D5V_S3
2
1D5V_S3
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
(R)
C104 SCD1U16V2KX-3GP
C506
2
197 201
C109 SCD1U16V2KX-3GP change 20131216 2 1
199
2
198
SODIMM A DECOUPLING
2
W
W W
1
C507 SC1U6D3V2KX-GP
2
1 2
C513 SC1U6D3V2KX-GP
10,33
ODT0 ODT1
2 10KR2J-3-GP
C75
M_VREF_CA_DIMM0 126 M_VREF_DQ_DIMM0 1
SMB_DATA 10,13,21,22,46,54 SMB_CLK 10,13,21,22,46,54 3D3V_S0 TS#_DIMM0_1 10
SC10U6D3V3MX-GP
116 120
M_A_DIM0_ODT0 M_A_DIM0_ODT1
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7
1R635
1D5V_S3
200 202
77 122 125
TS#_DIMM0_1
C485
5 5
A
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7#
5
11 28 46 63 136 153 170 187
D
3D3V_S0
SC10U6D3V3MX-GP
Place these caps close to VTT1 and VTT2.
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
5
Thermal EVENT
If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32
C76
12 29 47 64 137 154 171 188
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
M_A_DIM0_CLK_DDR1 M_A_DIM0_CLK_DDR#1
5
SC10U6D3V3MX-GP
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
SA0 SA1 NC#1 NC#2 NC#/TEST
5
C77
10 27 45 62 135 152 169 186
EVENT# VDDSPD
M_A_DIM0_CLK_DDR0 M_A_DIM0_CLK_DDR#0
SCD1U25V2KX-2-GP change 20131025
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
SDA SCL
Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30
SCD1U25V2KX-2-GP change 20131025
0D75V_S0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
5 5
SC10U6D3V3MX-GP
B
5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
102 104
5 5
M_A_DIM0_CKE0 M_A_DIM0_CKE1
SCD1U25V2KX-2-GP change 20131025
C
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
CK1 CK1#
BA0 BA1
101 103
M_A_DIM0_CS#0 M_A_DIM0_CS#1
1
109 108
73 74
2
5
M_A_BS2
5 M_A_BS0 5 M_A_BS1 M_A_DQ[63:0]
CK0 CK0#
114 121
1
5
CKE0 CKE1
M_A_RAS# 5 M_A_W E# 5 M_A_CAS# 5
2
D
CS0# CS1#
110 113 115
.C O
M_A_DQS[7:0]
RAS# WE# CAS#
2013/05/02 Rossi Change DIMM type follow London2 Symbol--> 62.10024.B81
NP1 NP2
AM
M_A_DQS#[7:0]
5
NP1 NP2
LA T
5
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
IX
M_A_A[15:0]
98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79
.F
5
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
3
2
Document Number
DDR3-DIMM1
Madrid Tuesday, January 21, 2014
Rev
SA Sheet 1
9
of
68
5
4
3
2
1
DIMM2
.F W W C108 SC1U6D3V2KX-GP
1 2
1
C501 SC1U6D3V2KX-GP
2
A
5 5
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
10 27 45 62 135 152 169 186
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
12 29 47 64 137 154 171 188 116 120
M_B_DIM0_ODT0 M_B_DIM0_ODT1 M_VREF_CA_DIMM1 M_VREF_DQ_DIMM1
9,33
126 1 30
DDR3_DRAMRST# 0D75V_S0
M
SMB_DATA 9,13,21,22,46,54 SMB_CLK 9,13,21,22,46,54
198
TS#_DIMM0_1
199
1D5V_S3
203 204
H = 5mm
1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2
2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206
C509
R639 10KR2J-3-GP
C
1D5V_S3
R170 1KR2F-3-GP M_VREF_DQ_DIMM1
R172 1 2 0R0603-PAD-1-GP-U R173 1KR2F-3-GP
C129
4
B
1D5V_S3
R190 1KR2F-3-GP M_VREF_CA_DIMM1
R197 1 2 0R0603-PAD-1-GP-U R192 1KR2F-3-GP
+V_SM_VREF_CNT
7,9
C142
Tracew should be at least 20 mils wide
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom
DDR3-204P-104-GP (62.10017.K11) 3
5
Tracew should be at least 20 mils wide
Date: 5
M_VREF_DQ_DIMM1_C
1
SA1_DIM1 2
2
197 201
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
3D3V_S0
9
1
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
D
SO-DIMMB is placed farther from the Processor than SO-DIMMA
SCD1U25V2KX-2-GP change 20131025
Place these caps close to VTT1 and VTT2.
0D75V_S0
W
-2
200 202
77 122 125
5
SCD1U25V2KX-2-GP change 20131025
B
5
2
NC#1 NC#2 NC#/TEST
M_B_DIM0_CLK_DDR1 M_B_DIM0_CLK_DDR#1
11 28 46 63 136 153 170 187
Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34
5
1
SA0 SA1
5
2
VDDSPD
M_B_DIM0_CLK_DDR0 M_B_DIM0_CLK_DDR#0
1
EVENT#
5 5
2
SDA SCL
IX
Layout Note: Place these Caps near SO-DIMMB.
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
102 104
5 5
M_B_DIM0_CKE0 M_B_DIM0_CKE1
1
20131128 Madrid SB Charles NB team cost review
5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
101 103
M_B_DIM0_CS#0 M_B_DIM0_CS#1
2
1 2
1 2
C100 SCD1U16V2KX-3GP
1 2 1 2
C99 SCD1U16V2KX-3GP change 20131216 2 1
C482
SC56P50V2JN-2GP 2 1
2
C81
SC10U6D3V3MX-GP
C82
SC10U6D3V3MX-GP
(R)
C83
(R)
SC10U6D3V3MX-GP
SC5D6P50V2CN-1GP
C489
1
C
SODIMM B DECOUPLING
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
CK1 CK1#
BA0 BA1
73 74
SCD1U25V2KX-2-GP change 20131025
1D5V_S3
109 108
CK0 CK0#
114 121
1
5
M_B_BS2
5 M_B_BS0 5 M_B_BS1 M_B_DQ[63:0]
CKE0 CKE1
2013/05/02 Rossi Change DIMM type follow London2 Symbol--> 62.10017.W31
M_B_RAS# 5 M_B_W E# 5 M_B_CAS# 5
2
5
CS0# CS1#
110 113 115
1
D
RAS# WE# CAS#
NP1 NP2
2
M_B_DQS[7:0]
NP1 NP2
.C O
M_B_DQS#[7:0]
5
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2
AM
M_B_A[15:0]
5
98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79
LA T
5
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
2
DDR3-DIMM2
Document Number
Rev
SA
Madrid
Tuesday, January 21, 2014
Sheet 1
10
of
68
5
4
3
2
1
USB3.0 Port Mapping
DMI
2 C503 SCD1U16V2ZY-2GP
2013/04/15 Rossi Delete not support
close to CONN FOR LAN
FOR AspireLink
HSO_C_DN3 HSO_C_DP3
C134 1 C133 1
2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP
PCIE_TXN4 PCIE_TXP4
C753 1 C754 1
change 20131025 2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP
PCIE_TXN5 PCIE_TXP5 FOR WLAN PCIE5 For WLAN
C130 1 C131 1
HSI_DN3 HSI_DP3 HSO_DN3 HSO_DP3 PCIE_RXN4 PCIE_RXP4 PCIE_C_TXN4 PCIE_C_TXP4 PCIE_RXN5 PCIE_RXP5 PCIE_C_TXN5 PCIE_C_TXP5
2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP change 20131025
CLKIN_DOT96# CLKIN_DOT96_P
(R)
1 1 1 1
TP113 TP114 TP111 TP112
P_PME# CK_PCH_33M_FB TP_PCH_A2 TP_PCH_A3 TP_PCH_B2 TP_PCH_B1 TD_IREF
AA31 AM22 A2 A3 B2 B1 C3
PME# CLKIN_33MHZLOOPBACK
PLTRST# GPIO35_NMI# GPIO50 GPIO51 GPIO52 GPIO53 GPIO54 GPIO55
TP16 TP17 TP18 TP19 TD_IREF
1
TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U
2 10KR2J-3-GP
FDI_TX_DN[0..1] FDI_TX_DP[0..1] 4 4
1
PIRQA# PIRQB# PIRQC# PIRQD# GPIO2 GPIO3 GPIO4 GPIO5
FDI_INT FDI_CSYNC
W
4 4
TP130
AU29 AU27 AW28 AV27 AR30 AV29 AV28 AT27
OTHERS USB_OC_01_N 27 USB_OC_23_N 27 USB_OC_45_N BT_EN 46 WLAN_EN 13 Wake#_LOM_EN 13 Wake#_WLAN_EN 20,21 LPC_PME#
W
46
CK_PCH_33M_FB 7,20,50 PLT_RST#
49
AA37 M40 AH26 AU31 AJ26 AV31 AW33 R30
PCI
LYNX-POINT-2-GP-U (KI.H8101.002)
PANEL_SW
PLT_RST#
AV20 AU20 AP11 AM11
P_GNT_N1
16
P_GNT_N2
16
PCH_NMI#_PU PCH_GPIO50 1 P_GNT_N1 PCH_GPIO52 1 P_GNT_N2 PCH_GPIO54 1 P_GNT_N3
W
2 TPAD28-1-GP-U
P_INTA_N P_INTB_N P_INTC_N P_INTD_N GPIO2 GPIO3 GPIO4 PCH_GPIO5_TP
2013/04/15 Rossi Delete not support
AE40 AF37 AD39 AD40 AF39 AC41 AF40 AG40
IX
R723 1
20131010 Madrid checked
2013/04/15 OC# function follow Swift
USB_OC_01_N USB_OC_23_N USB_OC_45_N Wake#_LOM_EN Wake#_WLAN_EN BT_EN WLAN_EN LPC_PME#
USBRBIAS_PCH
Rear USB 2.0 Side USB Charger
LAN Wake function WLAN Wake function BT En WLAN En LPC_PME
R652 2
CK_96M_DREF_DN R642 1 CK_96M_DREF_DP R644 1
Rear USB3.0
1 OF 11
PCH1A
2013/04/15 Rossi Delete not support USB_PN8 USB_PP8 USB_PN9 USB_PP9 USB_PN10 USB_PP10 USB_PN11 USB_PP11
USB3.0 Ext. port 2 (Side) Real USB2.0 ()
3
Real USB2.0 ()
4
Real USB2.0 ()
5 6
RF USB2.0 (Dual) X
7
X
2 10KR2J-3-GP 2 10KR2J-3-GP
USB30_RN1 USB30_RP1 USB30_TN1 USB30_TP1
Side USB3.0
2013/04/08 Rossi delete thunderbolt GPIO
G18 H18 B15 B16 K20 L20 D15 C15
TP131 TPAD28-1-GP-U
TP132 TPAD28-1-GP-U TP19
TPAD28-1-GP-U
P_GNT_N3
2013/04/15 Rossi Delete not support
16
TPAD28-1-GP-U
TP142
KEY0_TEST 1 PCH_GPIO71
L18 K18 B14 A14 AK28 AT34
D
2 10KR2J-3-GP
RN2
1 2 3 4
2012/06/25 SC Ryan SWAP FORCE PWR & TBGPIO6
8 7 6 5
SRN8K2J-4-GP 3D3V_S5
20131027 CM USB_OC_01_N PCH_GPIO71 Wake#_LOM_EN Wake#_WLAN_EN
R998 R683 R735 R200
1 1 1 1
2 2 2 2
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
CR
8 9
Wireless LAN+BT
10
Touch
11 12
Webcam X
13
X
C
OC[0..3] for Ports 0-7 OC[4..7] for Ports 8-13
3D3V_S0
6 OF 11
PLACE NEAR PCH
1D5V_S0
F20 G20 B18 C18
8K2R2J-3-GP 8K2R2J-3-GP 8K2R2J-3-GP 8K2R2J-3-GP 8K2R2J-3-GP 8K2R2J-3-GP 8K2R2J-3-GP
USBRBIAS_PHY (R465): TIE TRACES TOGETHER CLOSE TO PINS, WITH LENGTH NO LONGER THAN 1 INCHE TO RESISTOR
1 22D6R2F-L1-GP
USB30_RN0 USB30_RP0 USB30_TN0 USB30_TP0
1
R298
P_INTA_N P_INTC_N P_INTD_N P_INTB_N
USB3.0 Ext. port 1 (Side)
2
2 2 2 2 2 2 2
20131128 Madrid SB Charles modify GPIO5 pull up to 3D3V_S0, Fix leakage
Device
13/11/02 Delete USB3 port 1 for USB3S1--Kai 20131125 Madrid SB Charles Modify the USB2R1 as USB3R1 PCH1F
.F
USB30_RN0 USB30_RP0 USB30_TP0 USB30_TN0
GPIO59 GPIO40 GPIO41 GPIO42 GPIO43 GPIO9 GPIO10 GPIO14 USBRBIAS# USBRBIAS
3D3V_S5
R637 8K2R2F-1-GP
14
PERN1/USB3RN2 PERP1/USB3RP2 PETN1/USB3TN2 PETP1/USB3TP2 PERN2/USB3RN3 PERP2/USB3RP3 PETN2/USB3TN3 PETP2/USB3TP3 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 PERN6 PERP6 PETN6 PETP6 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8
(KI.H8101.002)
USB30_RN1 USB30_RP1 USB30_TN1 USB30_TP1
20131125 Madrid SB Charles Modify the USB2R1 as USB3R1
A
CLKIN_DMI# CLKIN_DMI_P
LYNX-POINT-2-GP-U
26 26 26 26
FDI
DMI_RCOMP PCIE_RCOMP
USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5
PCH_GPIO5_TP
R1941 R1931 R1911 R2541 R9001 R9011 R9021
USB3RN0 USB3RP0 USB3TN0 USB3TP0
FDI_RXN0 FDI_RXP0 FDI_RXN1 FDI_RXP1
USB3RN1 USB3RP1 USB3TN1 USB3TP1
FDI_CSYNC FDI_INT USB3
USB3RN4 USB3RP4 USB3TN4 USB3TP4
FDI_RCOMP
N1 N2 P2 P3
FDI_TX_DN0 FDI_TX_DP0 FDI_TX_DN1 FDI_TX_DP1
L2
FDI_CSYNC
L3
FDI_INT
K2
FDI_RCOMP
1
Only USB 3.0 ports 1 and 2 are enabled
L14 K14 B12 B11 F14 G14 D11 C11 F11 H11 B9 A9 J11 L11 B8 C8 G9 F9 B7 A7 F7 H7 E1 D2 K6 K8 G3 G5 J2 J3 H2 H1
USB Table
USB_PN0 USB_PP0 USB_PN1 USB_PP1
1
G22 F22
GPIO2 GPIO3 GPIO4 PCH_NMI#_PU PCH_GPIO50 PCH_GPIO52 PCH_GPIO54
C144 SC4D7U10V5ZY-3GP
C495 SCD1U10V2KX-5GP R636 7K5R2F-1-GP
2
B19 C13
100M_DMI_PCH_DN 100M_DMI_PCH_DP
USB3.0
B
USB30_RN2 USB30_PN2 USB30_TN2 USB30_TP2
2
DMIRCOMP DMICOMP
1 10KR2J-3-GP 1 10KR2J-3-GP
2013/04/08 Rossi delete Thunderbolt PCIE signal
26 26 26 26
USB_PN1 USB_PP1
1
2 7K5R2F-1-GP 2 7K5R2F-1-GP
R656 2 R657 2
AV10 AU10 AV11 AW11 AN14 AP14 AJ16 AK16 AU15 AV15 AU12 AT12 AV14 AW14 AU17 AT17 AW16 AV16 AN16 AP16 AJ18 AK18 AP18 AN18 AW18 AV18 AP20 AN20
LA T
USB_PN3 USB_PP3 USB_PN4 USB_PP4 USB_PN5 USB_PP5 USB_PN8 USB_PP8 USB_PN9 USB_PP9 USB_PN10 USB_PP10 USB_PN11 USB_PP11
R187 1 R643 1
USB2N0 USB2P0 USB2N1 USB2P1 USB2N2 USB2P2 USB2N3 USB2P3 USB2N4 USB2P4 USB2N5 USB2P5 USB2N6 USB2P6 USB2N7 USB2P7 USB2N8 USB2P8 USB2N9 USB2P9 USB2N10 USB2P10 USB2N11 USB2P11 USB2N12 USB2P12 USB2N13 USB2P13
PCI-E
27 27 27 27 27 27 24 24 46 46 27 27 27 27
USB Port 2
3D3V_S0
2013/05/14 Rossi P/H 8.2K follow design guide
(R)
(R)
B
FDILINK
USB3RN5 USB3RP5 USB3TN5 USB3TP5 TACH6/GPIO70 TACH7/GPIO71 LYNX-POINT-2-GP-U (KI.H8101.002)
Key test 3D3V_S0
1
1D5V_S0
DMI_RXN0 DMI_RXP0 DMI_TXN0 DMI_TXP0 DMI_RXN1 DMI_RXP1 DMI_TXN1 DMI_TXP1 DMI_RXN2 DMI_RXP2 DMI_TXN2 DMI_TXP2 DMI_RXN3 DMI_RXP3 DMI_TXN3 DMI_TXP3
DMI
USB_PN0 USB_PP0
20131125 Madrid SB Charles Modify the USB2R1 as USB3R1
L24 K24 C20 B20 G24 H24 D21 B21 F26 G26 B22 C22 K26 L26 A24 B24
R669 10KR2J-3-GP (63.10234.1DL)
2
C508 SCD1U16V2ZY-2GP
DMI_MT_IR_DN0 DMI_MT_IR_DP0 DMI_IT_MR_DN0 DMI_IT_MR_DP0 DMI_MT_IR_DN1 DMI_MT_IR_DP1 DMI_IT_MR_DN1 DMI_IT_MR_DP1 DMI_MT_IR_DN2 DMI_MT_IR_DP2 DMI_IT_MR_DN2 DMI_IT_MR_DP2 DMI_MT_IR_DN3 DMI_MT_IR_DP3 DMI_IT_MR_DN3 DMI_IT_MR_DP3
KEY0_TEST A
D
1
2
20131010 Madrid SA Charles checked Connect to PCH 16,17
USB2.0
C
USB30_RN1 USB30_PN1 USB30_TN1 USB30_TP1
13/11/02 Delete USB2 port 0 for USB3S1--Kai 20131125 Madrid SB Charles Pair Modify the USB2R1 as USB3R1 13/11/02 Add 0 restore USB port 2 1 for USB2R1--Kai
2 OF 11
PCH1B
Stitching Capacitor for USB3.0
USB_PN1 USB_PP1
USB_PN0 USB_PP0
M
3D3V_S0
26 26
USB Port 1
.C O
25 PCIE_RXN4 25 PCIE_RXP4 25 PCIE_TXN4 25 PCIE_TXP4
AM
Stitching Capacitor for DMI
46 PCIE_RXN5 46 PCIE_RXP5 46 PCIE_TXN5 46 PCIE_TXP5
26 26
SuperSpeed Signals
Q65 2N7002-11-GP (84.2N702.J31)
PANEL_SW G
Wistron Corporation
S
28 HSI_DN3 28 HSI_DP3 28 HSO_C_DN3 28 HSO_C_DP3
USB
1
PCIE D
USB 2.0 Signals
3D3V_S0
2
4 DMI_MT_IR_DN[0..3] 4 DMI_MT_IR_DP[0..3] 4 DMI_IT_MR_DN[0..3] 4 DMI_IT_MR_DP[0..3]
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
20131010 Madrid SA Charles Need check
FOR LPT: GP70 STRAP - USB3 PORT4 GP71 - USB3 PORT5 SOFT STRAP TO DETERMINE NATIVE FUNCTION 5
4
3
2
PCH(FDI/PCIE/DMI/USB) Size Custom Date:
Document Number
Rev
Madrid
Tuesday, January 21, 2014
1
SA Sheet
11
of
68
5
4
3
2
1
Thermal shuntdown 20
PCH_GPIO6
VGA 2013/04/15 Modified SATA defined
AA32
TPAD28-1-GP-U TPAD28-1-GP-U TPAD28-1-GP-U
R680 1
1 1 1
TP135 TP136 TP139
TP_PCH_PWM0 TP_PCH_PWM1 TP_PCH_PWM2
AL31 AM31 AP31 AV30
BOARD_ID_2 EC_SMI# PCH_GPIO6 PCH_GPIO7 SMBUS_ISP TACH5
AP28 AT31 AM28 AV34 AT30 AV35
(R)
2 0R2J-2-GP
SST_CTL_R
SATA_RXN2 SATA_RXP2 SATA_TXN2 SATA_TXP2 SATA_RXN3 SATA_RXP3 SATA_TXN3 SATA_TXP3
TACH0/GPIO17 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 TACH4/GPIO68 TACH5/GP69
SATA_RXN4/PERN1 SATA_RXP4/PERP1 SATA_TXN4/PETN1 SATA_TXP4/PETP1 SATA_RXN5/PERN2 SATA_RXP5/PERP2 SATA_TXN5/PETN2 SATA_TXP5/PETP2 CLKIN_SATA# CLKIN_SATA_P
SSTCTL SCLOCK/GPIO22 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48
SATALED# SATA_RCOMP
GPIO
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA2GP/GPIO36 SATA3GP/GPIO37 SATA4GP/GPIO16 SATA5GP/GPIO49
PWRGD_3V
PCH_GP34_PU H_A20GATE 20 H_RCIN# INT_SERIRQ PLTRST_CPU_N 20
13.05/20 change GPIO by BOM change
SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0
A26 B26 L28 K28 C27 B27 G28 F28 H35 H36 J39 D33 M37 J40 H40 N41 M39 N40
13.05/22 Add EC_SMI P/H Core PWR
SATA_RXN4 SATA_RXP4 SATA_TXN4 SATA_TXP4
CK_SATA_PCH_DN CK_SATA_PCH_DP
RSVD#N30 RCIN# SERIRQ THRMTRIP# PECI PM_SYNCH PLTRST_PROC#
2
1
R763 10KR2J-3-GP
PCH_GP39_PU
SATARBIAS_PCH
2 10KR2J-3-GP 2 10KR2J-3-GP
R203 1
2 7K5R2F-1-GP
N30 K36 G39 C40 G40 F40 F41
H_A20GATE H_RCIN# INT_SERIRQ H_THERMTRIP_N PECI_PCH H_PM_SYNC_0 PLTRST_CPU_N
PCH_GP48_PU
(R) R261 1
2 0R2J-2-GP
SATA1GP
16
SATA2GP
(KI.H8101.002)
B
2 10KR2J-3-GP
H_RCIN#
R238 1
2 10KR2J-3-GP
EC_SMI#
R199 1
2 10KR2J-3-GP
PCH_GP38_PU
R257 1
2 10KR2J-3-GP
PCH_GPIO16
R252 1
2 10KR2J-3-GP
VGA_DET
R283 1
2 10KR2J-3-GP
PCH_1D05V R233
PCH_GP34_PU
R739 1
SATA3GP
HDMI_DETECT
5 OF 11
R1631
2 2K2R2J-2-GP
R1611
2 2K2R2J-2-GP
R1621
2 2K2R2J-2-GP 2 2K2R2J-2-GP
R1591 R1521 (R) (R)
B
2 10KR2J-3-GP 2 10KR2J-3-GP
(R)
2 10KR2J-3-GP
R206 1
(R)
2 10KR2J-3-GP
R204 1
2 47KR2J-2-GP
1
2 4K7R2J-2-GP
1
R167 150R2F-1-GP (R)
2013/04/18 Rossi add EDP AUX PH
2
R166 150R2F-1-GP (R)
3D3V_S0 DPD_AUXP_S DPD_AUXN_S
R630 1K8R2-GP (R)
RN10
4 3
SRN10KJ-11-GP-U (R)
1
1
1 2
R629 1K8R2-GP (R)
A
DDPD_CTRL_CLK
DDPD_CTRL_DATA
2012/11/09 David vendor suggest(Dallas)
DDPB_CTRL_CLK
Wistron Corporation
DDPB_CTRL_DATA
2 2K2R2J-2-GP
DDPC_CTRL_CLK
2 2K2R2J-2-GP
DDPC_CTRL_DATA
W
4
3D3V_S0
2 10KR2J-3-GP
CLOSE TO PCH : NG for production -1A change to use 62.10078.291 and check alternate source
Michael 2011/12/01 change R283 and R305 from 100ohm to 47ohm Vendor Comment
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size C Date: 5
4
3
2
HDMI IN
Document Number
Rev
Madrid
Tuesday, January 21, 2014
SA Sheet
1
43
of
68
5
4
3
HDMI Level Shifter & CONNECTOR
SSID = VIDEO
UMA_Muxless : default setting used PS8101. if don't used PS8101 please change C5103~C5110 to 0 ohm resister
Pin 3
Pin 4
Pin 6
Pin 10
Pin 34
Pin 35
71.03411.B03
Low
Low
Low
Low
Low
Low
71.03411.D03
Low
Low
NC
NC
NC
NC
Eq
NC
NC
NC
NC
NC
NXP
2
1
Eq： ： Check SPEC
20131014 Madrid SA Charles HDMI port0 & port2 cross
3D3V_S0
R904 (S) 0R3J-0-U-GP
1
(S)
(S)
C619 SCD1U16V2ZY-2GP
1
(S)
2
1
(S)
C622 SCD1U16V2ZY-2GP
(S)
2
(S)
C621 SCD1U16V2ZY-2GP
(S)
2
(S)
1
HDMI_VDD
20131027 CM
C620 SCD1U16V2ZY-2GP
HDMI_DATA2_R# HDMI_DATA2_R
1
HDMI_DATA1_R# HDMI_DATA1_R
2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP
2
2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP
C246 1(S) C245 1(S)
C613 SCD1U16V2ZY-2GP
C248 1(S) C247 1(S)
DDSP_B_TX_DATA0# DDSP_B_TX_DATA0
1
DDSP_B_TX_DATA1# DDSP_B_TX_DATA1
2
DDSP_B_TX_DATA0# DDSP_B_TX_DATA0
HDMI_VDD
1
DDSP_B_TX_DATA1# DDSP_B_TX_DATA1
4 4
D
F5 (R) POLYSW-2A6V-2-GP
2
4 4
2
20131212 Madrid SB Charles modify NXP/ Parade Colay solution
C611 SCD1U16V2ZY-2GP
HDMI_DATA0_R# HDMI_DATA0_R
2
2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP
1
C250 1(S) C249 1(S)
C612 SCD1U16V2ZY-2GP
DDSP_B_TX_DATA2# DDSP_B_TX_DATA2
2
DDSP_B_TX_DATA2# DDSP_B_TX_DATA2
C616 SCD1U16V2ZY-2GP
DDSP_B_TX_DATA3# DDSP_B_TX_DATA3
4 4
HDMI_CLK_R# HDMI_CLK_R
1
4 4
2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP
1
D
C244 1(S) C243 1(S)
2
change 20131025 DDSP_B_TX_DATA3# DDSP_B_TX_DATA3
2
HDMI_VDD
R418
4
1 2
HDMI_DATA2_C_RH
3
HDMI_DATA2_C_RH#
DLM11SN900HY2L-GP
(S) R1060 180R2J-1-GP
(S66.10036.04L)
M
.F
(S66.10036.04L)
B
20131027 CM
4
HDMI_DATA1_C_RH
3
HDMI_DATA1_C_RH#
HDMI_CLK_C_R
1
HDMI_CLK_C_R#
4
HDMI_CLK_C_RH
3
HDMI_CLK_C_RH#
(S) R1063 180R2J-1-GP
;
1 2 R846 4K7R2J-2-GP
1
R856 487R2F-GP (S)
2
(R)
2
R852 4K7R2J-2-GP
1
1
(R)
2
2
(R)
R861 4K7R2J-2-GP
R853 4K7R2J-2-GP
1 2
R847 4K7R2J-2-GP
1 2
(R)
R404 4K7R2J-2-GP
1
R400 4K7R2J-2-GP
1 2
1 R406 4K7R2J-2-GP
1
2
2
2
R422 4K7R2J-2-GP
1 R398 4K7R2J-2-GP
1 2
R397 4K7R2J-2-GP
1 1
2
(R)
2
1 2 1
HDMI_LVL_27
2 1
HDMI_LVL_33
HDMI_LVL_11
(R) OC_2
C
HDMI_DATA2_C_RH
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21
HDMI_DATA2_C_RH# HDMI_DATA1_C_RH HDMI_DATA1_C_RH# HDMI_DATA0_C_RH HDMI_DATA0_C_RH# HDMI_CLK_C_RH HDMI_CLK_C_RH# 5V_HDMI
DDC_CLK_HDMI DDC_DATA_HDMI 5V_HDMI
5V_S0
1
F6 (S)
2
20131128 Madrid SB Charles NB team cost review
POLYSW-1D1A6V-9-GP-U
SKT-HDMI22-11-GP
F5102 from 1.5A change to 1.1A--Kai 0519
20140106 Madrid -1A Charles change symbol as 62.10078.631
3D3V_S0
2
1
HPD_HDMI_CON
R411 10KR2J-3-GP (R)
HPD_HDMI_CON_R
1
1
(R)
C609 (S) SCD1U16V2ZY-2GP
R389 200KR2J-L1-GP (R)
D6 BZX84-C6V8-GP (R)
HPD_HDMI_CON_R
12
R407 1MR2J-1-GP (R)
2
2
DY
1 2
PCH PU to 2.2K
(S) EQ_1
B
22 1
2
4 3 RN16 (S) SRN1K5J-GP
(R) EQ_0
3
2
1 3
BAT54C-12-GP D23 (S75.00054.T7D) DDC_HDMI_PU
(R) OC_3
(S) HDMI2
W
5V_S0
DDC CLK & DATA
(S)
OC_1
HDMI CONN
20
W
20131028 Madrid SA Charles Swap
2
DLM11SN900HY2L-GP (S66.10036.04L)
2
DLM11SN900HY2L-GP (S66.10036.04L)
(S) R1057 180R2J-1-GP
W
HDMI_DATA1_C_R#
2
1
1
2
HDMI_DATA1_C_R
TR13
1
TR16
OC_0
1
1
HDMI_DATA2_C_R#
(S)
2
HDMI_DATA2_C_R
1
(S) R1054 180R2J-1-GP
2
DLM11SN900HY2L-GP
(R)
(R)
LA T IX
HDMI_DATA0_C_RH#
2
HDMI_DATA0_C_RH
3
1
TR14
2
1
VDD VDD VDD VDD VDD VDD VDD VDD
Down size CMC--Kai 0307 TR15
HDMI_CLK_1 HDMI_DATA_1 HPD_HDMI_CON_R
2
DDC_EN
Modify for Madrid 20131001 Charles Modify HDMI as 62.10078.521
4
.C O
OE_N
25
32
OE#
2 11 15 21 33 40 46 26 (R) (R)
2
2
SCL_SOURCE SDA_SOURCE HPD_SOURCE
R1071 0R2J-2-GP
(S) C781 SC2D2U6D3V2MX-GP
1
DDC_CLK_HDMI DDC_DATA_HDMI HPD_HDMI_CON
0R2J-2-GP R1078
1
U5103 change to NXP--Kai 0319
HDMI_DATA0_C_R#
28 29 30 9 8 7
(S)
HDMI_VDD
(R)
AM
EQ_1
PI3VDP411LSZBE-GP
HDMI_DATA0_C_R
HDMI_CLK_C_R# HDMI_CLK_C_R
GND GND GND GND GND GND GND GND GND GND GND
EQ_0
C
OC_2/REXT OC_3
35
HDMI_DATA2_C_R# HDMI_DATA2_C_R
14 13
R1075
OC_1
6 10
EQ_1
SCL_SINK SDA_SINK HPD_SINK
OC_0
OC_2 OC_3
34
17 16
1 5 1 HDMI_LVL_12 12 18 24 HDMI_LVL_27 27 31 36 37 43 49
4
EQ_0
OUT_D4OUT_D4+
1 HDMI_LVL_1
3
OC_1
OUT_D3OUT_D3+
IN_D4IN_D4+
2
OC_0
IN_D3IN_D3+
HDMI_DATA1_C_R# HDMI_DATA1_C_R
0R2J-2-GP R1074
47 48
20 19
OE SELECTION
0R2J-2-GP R1073
44 45
HDMI_CLK_R# HDMI_CLK_R
OUT_D2OUT_D2+
HDMI_DATA0_C_R# HDMI_DATA0_C_R
0R2J-2-GP R1072
HDMI_DATA2_R# HDMI_DATA2_R
IN_D2IN_D2+
23 22
0R2J-2-GP R1077
41 42
OUT_D1OUT_D1+
0R2J-2-GP R1076
HDMI_DATA1_R# HDMI_DATA1_R
IN_D1IN_D1+
0R2J-2-GP
38 39
DDC_EN
U16 (S71.08171.B03)
HDMI_DATA0_R# HDMI_DATA0_R
HDMI_LVL_11
2
2
(S)
1 1KR2J-1-GP
HDMI_LVL_33
R412 HDMI_VDD
1
DUMMY 0 ohm change to 0 ohm--Kai 0308
0R0402-PAD
5V Tolerance 1 2
DDPB_CTRL_CLK DDPB_CTRL_DATA
4 3
HDMI_CLK_1 HDMI_DATA_1
DDC_CLK_HDMI DDC_DATA_HDMI
A
RN9 SRN0J-6-GP(S)
1
C618 SC470P50V2KX-3GP (R)
C617 SC470P50V2KX-3GP (R)
ESD
U19
3
CHPZ6V2PT-1-GP-U D24 (R)
1
2
2
1
12 12
2
A
HDMI_DATA1_C_RH# HDMI_DATA1_C_RH HDMI_DATA2_C_RH# HDMI_DATA2_C_RH
(R)
U18
1 2 4 5
3 8
6 7
9 10
HDMI_CLK_C_RH# HDMI_CLK_C_RH HDMI_DATA0_C_RH# HDMI_DATA0_C_RH
SP3010-04UTG-GP
(R)
1 2 4 5
3 8
6 7
9 10 SP3010-04UTG-GP
20131028 Madrid SA Charles Swap
;
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Date:
5
4
3
2
HDMI OUT Document Number
Rev
SA
Madrid
Tuesday, January 21, 2014 1
Sheet
44
of
68
SATA HDD/Power Connector Layout: Put them together
HDD1
(69.50014.001)
(20.81593.007) SKT-SATA7P-19-GP-U
Black color SATA 2.0 CONN 5V_HDD
1
LA T
2
2013/06/24_CLOSE HDDPW1_EMI
1
F4
R349 (R) 0R3J-0-U-GP
3D3V_HDD
2
FUSE-1D5A6V-11GP
1
20131202 Madrid SB Charles Delete C189 for connector layout
12V_HDD
F2
2
FUSE-3A15V-GP
C190 SC1U25V3KX-1-GP
20131220 Madrid SB Charles change BOM to 1u 25V update Symbo
IX
(21.61820.105)
C219 SCD1U16V2ZY-2GP
SCD1U10V2KX-5GP
20131202 Madrid SB Charles Delete R368 for connector layout
12V_S0
3D3V_HDD
JWT-CON5-S7-GP
3D3V_S0
C211 SC10U10V5ZY-1GP
SB
20131220 Madrid SB Charles OBS change, study to cost down
AM
12V_HDD
2 3 4 5
(R78.10421.2FL) C201
2
HDDPW1 1
2
POLYSW-2A6V-GP
1 8
20131010 Madrid SA Charles Net name follow superb
F3
1
SATA_RXN0_C SATA_RXP0_C
5V_HDD 1
2
2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP
5V_S0
1
1 1
SATA_TXP0_C SATA_TXN0_C
1
C238 C236
2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP
2
SATA_RXN0 SATA_RXP0
1 1
1
12 12
C257 C255
M
SATA_TXP0 SATA_TXN0
.C O
12 12
5V_HDD
9 7 6 5 4 3 2
2
SSID = SATA
.F
SATA ODD/ Power Connector
SKT-SATA7P-19-GP-U (20.81593.007)
Black color
SATA_TXN4_C C122 SATA_TXP4_C C125
1 1
2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP
SATA_TXN4 SATA_TXP4
SATA_RXP4 12 SATA_RXN4 12 SATA_TXN4 12 SATA_TXP4 12
20131010 Madrid SA Charles Net name follow superb
1
ODDPW1 V_5_ODD
2
POLYSW-2A6V-GP (69.50014.001)
C106 (R) SC10U10V5ZY-1GP
1
SATA_RXP4 SATA_RXN4
V_5_ODD F1
1 2
C102 SC1U16V3KX-2GP
2
2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP
5V_S0
1
1 1
W
SATA_RXP4_C C112 SATA_RXN4_C C113
W
2 3 4 5 6 7 9
W
8 1
2
ODD1
JWT-CON2-S14-GP (21.61783.102)
Front View
SATA 2.0 CONN
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Pin1(GND) Title
20.60341.104: 4pin right angle 20.60334.103: 3pin right angle
Size Custom Date:
HDD/ODD
Document Number
Madrid Tuesday, January 21, 2014
Rev
SA Sheet
45
of
68
4
3
2
SSID = Wireless and Bluetooth
Mini Card Connector(Wireless LAN+BT) Michael 2011/11/29 Change 1D5V_MEM to 1D5V_S0
Height: 5.2mm T-CONN: 62.10043.831 BELLWETHER: 62.10043.A81
1D5V_S0_WLAN 3D3V_S5
PC60 SC10U10V5KX-2GP (R78.10693.41L)
24 39 41 52 8 16
C
10 12 14
modify for Madrid 20131001 Charles symbol follow Superb, net/sch follow Pisa2
2
R536 10KR2J-3-GP
11
BT_EN
BT_EN
17 19 45 47 49 51 3 5
3D3V_S5
1 R550 11
210KR2J-3-GP
R542 1 MTK_USB_SW R541 1 (R) SMB_CLK SMB_DATA
R549 R548
1 1
(R) (R)
PETN0 PETP0
+3_3VAUX +3_3VAUX +3_3VAUX +3_3VAUX
USB_DUSB_D+
UIM_PWR WAKE# CLKREQ# PERST#
UIM_VPP UIM_DATA UIM_CLK UIM_RESET
53 54
RESERVED#17/UIM_C8 RESERVED#19/UIM_C4 RESERVED#45 RESERVED#47 RESERVED#49 RESERVED#51
20
210KR2J-3-GP 2 0R2J-2-GP
MTK_PWR_EN_R MTK_USB_SW_R
42 44 46
2 0R2J-2-GP 2 0R2J-2-GP
SMB_CLK_WL SMB_DATA_WL
30 32
COEX1 COEX2
W_DISABLE#
LED_WWAN# LED_WLAN# LED_WPAN# SMB_CLK SMB_DATA
IX
9,10,13,21,22,54 SMB_CLK 9,10,13,21,22,54 SMB_DATA
WLAN_EN
WLAN_EN
PERN0 PERP0
+1_5V +1_5V
B
CLK_PCIE_WLAN# CLK_PCIE_WLAN
23 25
PCIE_RXN5 PCIE_RXP5
31 33
PCIE_TXN5 PCIE_TXP5
36 38
USB_PN9W USB_PP9W
1 7 22
PCIE_WAKE_N_WLAN_R W1_CLKREQ_N R29
1
USB_PN9W
2
NP1 NP2
GND GND GND GND GND GND GND GND GND GND GND GND GND GND
CLK_PCIE_WLAN# 14 CLK_PCIE_WLAN 14
PCIE_RXN5 PCIE_RXP5 PCIE_TXN5 PCIE_TXP5
R31 1
1
2
20130726 Add 0 ohm, CM
11 11
11 20131010 Madrid 11 checked
2 0R0402-PAD-2-GP PCIE_WAKE_N_WLAN 0R2J-2-GP CLK_PCIE_WLAN_REQ# 13 PLT_WLAN_RST# 20
13 C
53 54
NP1 NP2
4 9 15 18 21 26 27 29 34 35 37 40 43 50
LA T
1
3D3V_S5
3_3VAUX
11 13
1D5V_S0_WLAN
Please close to PCIE2 C12 SCD1U16V2ZY-2GP (R)
1
1 2 2
2013/05/07 ADD_Ryan
3D3V_S5_RSV
REFCLKREFCLK+
C357 SCD1U16V2ZY-2GP (R)
2
28 48
0R2J-2-GP R544
1_5V
1
2
2
6
(R)
(R) 1 0R2J-2-GP
USB_PN9
M
1D5V_S0_WLAN
USB_PP9 USB_PN9
D
USB_PP9W
20131027 CM
1
R534 2
3D3V_S5 1
1D5V_S0
11 11
USB_PP9
(66.R0036.04L) FILTER-4P-137-GP 4 3
MINI1
.C O
Michael 2011/11/29 Change 3D3V_S0 to 3D3V_EUP
L44
2012/06/26_ROME SA Change symbol to 5.2mm
AM
D
1
2011/11/29 Michael ADD USB for BT Function
2
5
C349 SC10U10V5ZY-1GP (R)
B
SKT-MINI52P-93-GP
.F
W
A
1
1
C358 SCD1U16V2ZY-2GP
C348 SC10U10V5ZY-1GP
2
2
C13 SCD1U16V2ZY-2GP
2
1
Please close to PCIE2
1
PLT_WLAN_RST#
(R) 2
MTK_USB_SW
C359 SC10P50V2JN-4GP
W
2
R328 (R) 10KR2J-3-GP
MTK_USB_SW
3D3V_S5
W
P3P3V 1
Michael 2011/11/29 Add W3_DISABLE_N for Bluetooth Add R1091 and R1089
SB
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Date:
5
4
3
2
Mini PCIE Card WLAN / BT
Document Number
Madrid
Tuesday, January 21, 2014
Rev
SA Sheet 1
46
of
68
5
4
3
2
1
D
.C O
M
D
C
LA T
AM
C
B
W
W
.F
IX
B
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
4
Mini PCIE Card (TV & SIM)
Size Custom Date:
5
A
W
A
3
2
Document Number
Rev
SA
Madrid
Tuesday, January 21, 2014
Sheet 1
47
of
68
5
4
3
2
1
D
.C O
M
D
C
IX
LA T
AM
C
B
W
W
W
.F
B
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
A
A
Title Size Custom Date: 5
4
3
Mini PCIE Card mSATA
Document Number
Madrid Tuesday, January 21, 2014 2
Rev
SA Sheet
48
of 1
68
4
3
V_5_LED
2
3D3V_S5
R481 1 2 (63.10133.16L) 130R5J-GP
1
R510
SUSLED_2
2
(63.10334.1DL)
2009/12/01
20 SUSLED_CON
B
PWRBT1 DCBATOUT
2
1 R181
Panel_SW
2
2
PANEL_ON_R 1
33R2J-2-GP
3
B
PANSW1
21
PANEL_SW_SC
20
PANEL_SW_EC
PANEL_SW_SC PANEL_SW_EC
2 4
SW-TACT-48-GP (22.40126.181)
2
C136 SCD1U16V2ZY-2GP
PANEL_SW
20131202 Madrid SB Charles Delete D7
Wistron Corporation
USB_PWR_3
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Date:
3
SA Sheet 1
W
PWRLED_CON
Rev
Madrid
Tuesday, January 21, 2014
2
PWRLED_CON
PWR BT/Side Key/LED
Document Number
W
W
20121205 Charles Add EMI solution
4
1
3
.F
1
D2 LBAV99LT1G-1-GP (R83.BAV99.D11)
close to PWRBT1 as much as possible.
5
Panel_SW
IX
11 2
1 2
1 2
1 2
1 2
EC1 SC100P50V2JN-3GP
EC23 SC100P50V2JN-3GP
A
C314 SC100P50V2JN-3GP
CLX-CON6-8-GP
C313 SC100P50V2JN-3GP
C286 SC100P50V2JN-3GP
8
1
near to PWRBT1 two side
PWRBTN# PWRLED_CON SUSLED_CON
(S) PANEL_SW_SC 1 2 R414 0R2J-2-GP (U) PANEL_SW_EC 1 2 R409 0R2J-2-GP
Pannel_SW
1 2 3 4 5 6
LA T
USB_PWR_3
7
R413 10KR2J-3-GP (S)
20110616
2
1
U24 (R) BAV99-13-GP
R408 10KR2J-3-GP (U)
AM
R460 10KR2J-3-GP (R)
3
C320 SCD01U50V2KX-1GP
20131020 Madrid SA Charles Pannel on/off switch Branch
3D3V_A P3P3V
2
PWRBTN_IN
C
.C O
PWRBTN_IN
1
1
R486 470R2J-2-GP (64.47005.6DL)
1
2
L21 MHC1608S601LBP-GP
2
2 PWRBTN#_1
1
1
L31 1
MHC1608S601LBP-GP
2
2
10mW
20131212 Madrid 1A Charles modify to change pin
M
2
20131204 Madrid SB Charles modify R477 to 150 ohm to meet ACER spec V_5_SUS1
C
R492 330KR2J-L1-GP
SUSLED_N 20
R526 10KR2J-3-GP (R)
1
1
SUSLED_CON_P1
2010/11/15 add as vendor suggestion
R477 150R5J-GP 3D3V_A
SUSLED_N
2K2R2J-2-GP
3
Michael 2011/12/16 LED SW will be defined later
Q55 (84.T3906.E11) SUSLED_1 1 PMBS3906-GP
D
1
2
20110626
PWRBTN#
R511 10KR2J-3-GP
2
R519 4K7R2J-2-GP (R) 2
V_5_PWR1
2
2
1
MHC1608S601LBP-GP
USB_PWR_3
SUSPEND LED
1
G1
COPPER-CLOSE-GP-U
1
L26
PWRLED_CON D
1
1
2
USB_PWR_3 5V_S0
2
1
5
49
of
68
A
5
4
3
2
1
R864
D
1
3D3V_S0
D
4 6 8 10 12 14
LPC_AD2
13,20 LPC_AD1 13,20 LPC_AD0 20 SIO_DEBUG_TX 20 SIO_DEBUG_RX
X
1 3 5 7 9 11 13
13,20
CLK_PCI_LPC
14
PLT_RST#
7,11,20
3D3V_S0
JWT-CONN14D-SFP-1-GP
AM
MP0822
C
C
2012/09/07_aPisa_SA Add TPM Header
LA T
TPM Header INT_SERIRQ
.F
IX
12,20
LPC_FRAME# V_3P3_DBP
M
13,20
DBGH1 2
LPC_AD3
.C O
13,20
2
10KR2J-3-GP
B
W
W
W
B
Wistron Corporation
A
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Debug connector
Size A4
Document Number
Madrid Tuesday, January 21, 2014
Date: 5
4
3
2
Rev
SA Sheet
50
of 1
68
A
5
4
2
1
1U X 2 Under GPU
10U X 2 mid TO GPU
4.7U X 2 NEAR TO GPU
22U X 2 mid TO GPU
R99 (G) 1 2 0R0402-PAD-2-GP
10KR2J-3-GP
1D05V_VGA_S0
5
4
PEG_TXN[0..3]
AN17 AM17 AH17 AG17
IX
AK20 AJ20 AP20 AP21 AH20 AG20 AN21 AM21 AK21 AJ21
.F
AN23 AM23 AL22 AK22
AK23 AJ23 AN24 AM24 AH23 AG23 AN26 AM26 AK24 AJ24 AP26 AP27
since GPU PCI-E is 8 lanes.--Kai 0313
AL25 AK25 AN27 AM27
1 2
1 2
1 2
1 2
1 2
1 2
2
2
1
1
1
1 2
1 2
GK208/GK107/GF117
NC
PEX_PLL_HVDD PEX_SVDD_3V3
AH12
3D3V_VGA_S0
AG12
PEX_TX6 PEX_TX6# PEX_RX6 PEX_RX6# PEX_TX7 PEX_TX7# PEX_RX7 PEX_RX7# PEX_TX8 PEX_TX8# VDD_SENSE PEX_RX8 PEX_RX8# GND_SENSE
X7R C392
C456
(G78.10421.2FL) (G)
L4 L5
C451
3.3V +/- 5% 120mA (See NV DG)
(G)
VGACORE_VDD_SENSE_1
60
VGACORE_GND_SENSE_1
60
PEX_TX9 PEX_TX9# PEX_RX9 PEX_RX9# PEX_TX10 PEX_TX10# NC_3V3AUX
P8
PEX_RX10 PEX_RX10#
B
1.05V +/- 3% 120mA (See NV DG)
PEX_TX11 PEX_TX11# PEX_RX11 PEX_RX11# PEX_TX12 PEX_TX12# PEX_RX12 PEX_RX12# PEX_TX13 PEX_TX13# PEX_RX13 PEX_RX13# PEX_TX14 PEX_TX14# PEX_RX14 PEX_RX14#
PEX_TSTCLK_OUT PEX_TSTCLK_OUT#
PEX_TSTCLK_OUT PEX_TSTCLK_OUT#
R572 1 (R)
2 200R2F-L-GP
PEX_PLLVDD
1D05V_VGA_S0 L45
PEX_PLLVDD
TESTMODE
AG26
PEX_PLLVDD
R564 1 AK11 TESTMODE (G)
2 10KR2J-3-GP
X7R
C389 (G78.10421.2FL)
1
C391 (G)
2
MCB1608S121IBP-GP (G63.00000.00L) C390 (G78.10520.5FL)
Change to 0603 0 ohm.--Kai 0313
100MHZ 120mohm
PEX_TX15 PEX_TX15# PEX_RX15 PEX_RX15#
AJ26 AK26
Use 0 ohm at L8301 with N14P-GV2, please change to 63.00000.00L Use 120 ohm@100MHz bead (ESR = 0.18 ohm)at L8301 for N14M-GE, please mount 68.00335.141
SC1U10V2KX-1GP
W
AP23 AP24
GF108
PEX_RX5 PEX_RX5#
SC4D7U6D3V3KX-GP
W
AN20 AM20
PEX_TX5 PEX_TX5#
SCD1U10V2KX-5GP
W
AL19 AK19
C396
PEX_RX4 PEX_RX4#
SC4D7U6D3V3KX-GP
AN18 AM18
C399
C
SC4D7U6D3V3KX-GP
B
AK18 AJ18
(G)
PEX_TX4 PEX_TX4#
SCD1U10V2KX-5GP
LA T
AP17 AP18
C376
Add CAP follow vendor suggestion--Kai 0314
PEX_RX3 PEX_RX3#
1
PEG_TXP[0..3]
(G)
2
AK17 AJ17
4
PEX_TX3 PEX_TX3#
C387
1
AN15 AM15
2
PEG_TXP3 PEG_TXN3
PEX_RX2 PEX_RX2#
1
PEG_RXN[0..3]
AL16 AK16
2
PEG_RXP[0..3]
4
AP14 AP15
AM
C
4
PEG_C_RXP3 PEG_C_RXN3
C369 (G)
(G78.10520.5FL)
PEG_TXP2 PEG_TXN2
C373 (G)
(G78.10520.5FL)
2 SCD22U10V2KX-1GP 2 SCD22U10V2KX-1GP
PEX_TX2 PEX_TX2#
D
C405
SC1U10V2KX-1GP
(G) 1 (G) 1
PEX_RX1 PEX_RX1#
SC1U10V2KX-1GP
C371 C375
AK15 AJ15
SC4D7U6D3V3KX-GP
PEG_RXP3 PEG_RXN3
PEG_C_RXP2 PEG_C_RXN2
SC4D7U6D3V3KX-GP
2 SCD22U10V2KX-1GP 2 SCD22U10V2KX-1GP
SC10U6D3V3MX-GP
(G) 1 (G) 1
SC10U6D3V3MX-GP
C374 C377
SC22U4V3MX-GP C398 (G78.22610.5BL)
PEG_RXP2 PEG_RXN2
PEX_TX1 PEX_TX1#
C395
1D05V_VGA_S0
AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28
SC22U4V3MX-GP C386 (G78.22610.5BL)
reserve an active driver for PEX_RST#--Kai 0313
AH14 AG14
AN14 AM14
(G)
10U X 2 mid TO GPU
1
PEG_C_RXP1 PEG_C_RXN1
PEG_TXP1 PEG_TXN1
C385
22U X 2 mid TO GPU
2
2 SCD22U10V2KX-1GP 2 SCD22U10V2KX-1GP
PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14
(G)
4.7U X 2 NEAR TO GPU
1
(G) 1 (G) 1
PEX_RX0 PEX_RX0#
C388
1U X 2 Under GPU
2
C378 C382
PEX_TX0 PEX_TX0#
.C O
PEG_RXP1 PEG_RXN1
AN12 AM12
PEX_REFCLK PEX_REFCLK#
1
PEG_TXP0 PEG_TXN0
AK14 AJ14
2
2 SCD22U10V2KX-1GP 2 SCD22U10V2KX-1GP
PEX_CLKREQ#
AG19 AG21 AG22 AG24 AH21 AH25
1
(G) 1 (G) 1
PEG_C_RXP0 PEG_C_RXN0
PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6
2
C381 C383
AL13 AK13
CLK_PCIE_VGA CLK_PCIE_VGA#
NC
PEX_RST#
1
14 14
AK12
PEX_WAKE#
2
AJ12
PEG_CLKREQ#_1
PEG_RXP0 PEG_RXN0
2
GK208/GF117
VGA_RST#
2
1 2
GK107/GF108
AJ11
OD AND gate required
(G) C372
(G78.10520.5FL)
1/17 PCI_EXPRESS
(R)
(G) C368
(G78.10520.5FL)
73.01G09.AAH
1 OF 17
VGA1A
10KR2J-3-GP R586 (G)
SC1U10V2KX-1GP
U5 74VHC1G09DFT2G-GP
1
3D3V_VGA_S0
VGA_RST#
SC1U10V2KX-1GP
GND OUT Y
4
SC4D7U6D3V3KX-GP
2
VCC
IN A
SC4D7U6D3V3KX-GP
10KR2J-3-GP (R78.10421.2FL) (R) C70 SCD1U10V2KX-5GP
IN B
1
3
SC10U6D3V3MX-GP
2
SC10U6D3V3MX-GP
IN_A_R
2
2
M
1
SC22U4V3MX-GP C379 (G78.22610.5BL)
R107
SC22U4V3MX-GP C402 (G78.22610.5BL)
3D3V_VGA_S0
PEX LANES 8 TO 15 NC FOR GF117/GK208
1
PLTRST_GPU#
1
20,54 D
3D3V_VGA_S0
1
2
(R)
2
1
3D3V_VGA_S0
R109
3
For U3702 not OD AND gate R3719 to 64.15015.6DL R3720 to 64.75005.6DL R3702 to DY
PEX_TERMP
R81 1 AP29 PEX_TERMP
2 2K49R2F-GP
(G)
N14P-GS-A1-GP (G)
madrid 20131017 Charles power ask to modify as 09.8271N.A5L
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date: 5
4
3
2
GPU (1/5): PEG
Document Number
Rev
SA
Madrid
Tuesday, January 21, 2014
Sheet 1
51
of
68
5
4
3
2
1
LVDS Interface
HDMI Interface
10 OF 17
VGA1J
11 OF 17
VGA1K
5/17 IFPAB
6/17 IFPC
ALL PINS NC FOR GF117
ALL PINS NC FOR GF117 DP(GK208)
IFPA_TXD0# IFPA_TXD0
AF8
IFPAB_PLLVDD
DPA_L1 DPA_L1
IFPA_TXD1# IFPA_TXD1
IFPC_PLLVDD_PD
AN3 AP3 AM5 AN5
(R)
1
IFPC_PLLVDD
R580 10KR2J-3-GP
IFPAB_IOVDD_PD
AG8 AG9
IFPA_IOVDD IFPB_IOVDD
DPB_L3 DPB_L3
IFPB_TXC# IFPB_TXC
DPB_L2 DPB_L2
IFPB_TXD4# IFPB_TXD4
DPB_L1 DPB_L1
IFPB_TXD5# IFPB_TXD5
DPB_L0 DPB_L0
IFPB_TXD6# IFPB_TXD6
IFPC
AK6 AL6 AH6 AJ6
M
2
IFPA_TXD2# IFPA_TXD2
AH9 AJ9
IFPC_IOVDD_PD
AP5 AP6
DVI/HDMI
DP
I2CW_SDA I2CW_SCL
IFPC_AUX_I2CW_SDA# IFPC_AUX_I2CW_SCL
TXC TXC
IFPC_L3# IFPC_L3
TXD0 TXD0
IFPC_L2# IFPC_L2
TXD1 TXD1
IFPC_L1# IFPC_L1
TXD2 TXD2
IFPC_L0# IFPC_L0
IFPAB
AL8 AK8
N4
LA T
N14P-GS-A1-GP (G)
13 OF 17
VGA1M 8/17 IFPEF
ALL PINS NC FOR GF117
TXC TXC
TXC TXC
TXD0 TXD0
TXD0 TXD0
TXD1 TXD1
TXD1 TXD1
TXD2 TXD2
TXD2 TXD2
IFPEF_PLLVDD IFPEF_RSET
2
NC FOR GK208
IFPE
B
IFPE_AUX_I2CY_SDA# IFPE_AUX_I2CY_SCL
AB4 AB3
IFPE_L3# IFPE_L3 IFPE_L2# IFPE_L2 IFPE_L1# IFPE_L1 IFPE_L0# IFPE_L0
W
AC7
IFPE_IOVDD
I2CZ_SDA I2CZ_SCL
IFPF_IOVDD
W
AC8
W
IFPDE_PLL_IO_VDD_PD
IFPF
1
GPIO18
IFPF_AUX_I2CZ_SDA# IFPF_AUX_I2CZ_SCL
TXC TXC
IFPF_L3# IFPF_L3
TXD3 TXD3
TXD0 TXD0
IFPF_L2# IFPF_L2
TXD4 TXD4
TXD1 TXD1
IFPF_L1# IFPF_L1
TXD5 TXD5
TXD2 TXD2
IFPF_L0# IFPF_L0
NC FOR GK208
R597 10KR2J-3-GP
HPD_E
12 OF 17
7/17 IFPD
ALL PINS NC FOR GF117 AN2
IFPD_PLLVDD_PD
(R)
AC3 AC2
AG7
R590 10KR2J-3-GP
IFPD_RSET
IFPD_PLLVDD
IFPD
IFPD_IOVDD_PD
AC1 AD1 AD3 AD2
C
VGA1L
AC5 AC4
(R)
NC FOR GK208
HPD_E
P2
EDP Interface
AG6
DP
DVI/HDMI
I2CX_SDA I2CX_SCL
IFPD_AUX_I2CX_SDA# IFPD_AUX_I2CX_SCL
TXC TXC
IFPD_L3# IFPD_L3
TXD0 TXD0
IFPD_L2# IFPD_L2
TXD1 TXD1
IFPD_L1# IFPD_L1
TXD2 TXD2
IFPD_L0# IFPD_L0
IFPD_IOVDD
GPIO17
AK2 AK3 AK5 AK4 AL4 AL3 AM4 AM3 AM2 AM1
M6
N14P-GS-A1-GP (G)
1
R598 10KR2J-3-GP
DP
.F
AD6 (R)
AJ1 AK1
R587 10KR2J-3-GP
IX
AB8
I2CY_SDA I2CY_SCL
1
IFPEF_PLLVDD_PD
DVI-SL/HDMI
I2CY_SDA I2CY_SCL
AJ2 AJ3
B
R573 10KR2J-3-GP
2
DVI-DL
AH4 AH3
2
AM8 AN8
C
GPIO14
GPIO15
D
AG4 AG5
N14P-GS-A1-GP (G)
1
IFPB_TXD7# IFPB_TXD7
AL7 AM7
IFPC_IOVDD
AG2 AG3
2
2
R577 10KR2J-3-GP
AM
1
(R)
(R)
AF6
1
DPA_L0 DPA_L0
IFPA_TXD3# IFPA_TXD3
2
AF7
.C O
(R) R579 10KR2J-3-GP
(R)
IFPC_RSET
2
AH8
DPA_L2 DPA_L2
AN6 AM6
IFPAB_RSET
D
IFPAB_PLLVDD_PD
IFPA_TXC# IFPA_TXC
1
AJ8
LVDS
DPA_L3 DPA_L3
R1
AF2 AF3 AF1 AG1 AD5 AD4 AF5 AF4 AE4 AE3
NC FOR GK208 A
HPD_F
GPIO19
A
P3
N14P-GS-A1-GP (G)
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom
GPU DIGITALOUT(2/5)
Document Number
Madrid
Date: Tuesday, January 21, 2014 5
4
3
2
1
Rev
SA Sheet
52
of
68
5
4
3
2
1
2 OF 17
VGA1B 2/17 FBA
3 OF 17
VGA1C 3/17 FBB
FBA_WCKB1 FBA_WCKB1# FBA_WCKB23 FBA_WCKB23# FBA_WCKB45 FBA_WCKB45# FBA_WCKB67 FBA_WCKB67# FBA_PLL_AVDD
D9 E4 B2 A9 D22 D28 A30 B23
N14P-GS-A1-GP (G)
NV suggestion
66mA
FB_PLLVDD
U27
L46
1
2
MHC1608S300QBP-GP
X7R
C430
C457 (G)
20131029 Madrid SA Charles NV Review change to 30 ohm --> 68.00335.051 Pisa2: 80ohm --> 68.00335.181
C461
C444
(G)
(R)
SC22U6D3V3MX-1-GP
C422
X7R
FBB_DEBUG0 FBB_DEBUG1
FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7
FBB_CLK0 FBB_CLK0# FBB_CLK1 FBB_CLK1#
FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7
FBB_WCK1 FBB_WCK1# FBB_WCK23 FBB_WCK23# FBB_WCK45 FBB_WCK45# FBB_WCK67 FBB_WCK67#
FBB_WCKB1 FBB_WCKB1# FBB_WCKB23 FBB_WCKB23# FBB_WCKB45 FBB_WCKB45# FBB_WCKB67 FBB_WCKB67#
THE FBB_WCKBxx PINS ARE USED ONLY ON GK107 THEY ARE NC FOR GF108
1D05V_VGA_S0 (G68.00335.181)
1
1
D
C472
2
2
C469
(G)
SC4D7U6D3V3KX-GP
1
1 (G)
SC4D7U6D3V3KX-GP
C468
2
2
C477
(G)
SC4D7U6D3V3KX-GP
1
SC4D7U6D3V3KX-GP
C480
(G78.10521.5BL)
1
X7R
2
C481
SC1U6D3V3KX-2GP
1
X7R
2
2
Under GPU.
SC1U6D3V3KX-2GP
C464
(G78.10521.5BL)
X7R
(G78.10521.5BL)
1
SC1U6D3V3KX-2GP
C476
(G78.10521.5BL)
1
X7R
2
SC1U6D3V3KX-2GP
C463
(G78.10421.2FL)
1
X7R
2
SCD1U10V2KX-5GP
C466
(G78.10421.2FL)
1
X7R
2
SCD1U10V2KX-5GP
C460
(G78.10421.2FL)
1
X7R
2
2
SCD1U10V2KX-5GP
C454
(G78.10421.2FL)
SCD1U10V2KX-5GP
X7R
(G)
(G)
1 C475
2
SC10U6D3V3MX-GP
1 C474
2
SC10U6D3V3MX-GP
1
C478 (G)
2
2
1
1D5V_VGA_S0
SC22U6D3V5MX-2GP
M .C O
(G)
Modify power cap--Kai 0315
Near GPU.
FB_VDDQ_SENSE
1D5V_VGA_S0
(G) R614
2
1
40D2R2F-GP
G14 G20
D12 E12 E20 F20
F2
FB_CAL_PD_VDDQ
J27
FB_CAL_PU_GND
H27
FB_CAL_TERM_GND
H25
FB_GND_SENSE FB_CAL_PD_VDDQ FB_CAL_PU_GND FB_CAL_TERM_GND C
N14P-GS-A1-GP (G) R620
1
C12 C20
1
1
J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33
SCD1U10V2KX-5GP
FB_VREF
K31 L30 H34 J34 AG30 AG31 AJ34 AK34
FBB_CMD_RFU0 FBB_CMD_RFU1
F1
AA27 AA30 AB27 AB33 AC27 AD27 AE27 AF27 AG27 B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24 H8 H9 L27 M27 N27 P27 R27 T27 T30 T33 V27 W27 W30 W33 Y27
R608 51D1R2F-GP (G)
(G)
2
FBA_WCK1 FBA_WCK1# FBA_WCK23 FBA_WCK23# FBA_WCK45 FBA_WCK45# FBA_WCK67 FBA_WCK67#
D10 D5 C3 B9 E23 E28 B30 A23
CLKA0 56,58 CLKA0# 56,58 CLKA1 57,59 CLKA1# 57,59
FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7
D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17
FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43 FBVDDQ_44
F8 E8 A5 A6 D24 D25 B27 C27
LA T
FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7
R30 R31 AB31 AC31
FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8 FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31
2
60D4R2F-GP
VGA1D 14/17 FBVDDQ
AM
2 2 60D4R2F-GP
1D5V_VGA_S0
4 OF 17
NC
FBB_PLL_AVDD
GF108
D6 D7 C6 B6 F26 E26 A26 A27
H17
FB_PLLVDD
GK107
N14P-GS-A1-GP (G)
Follow vendor suggestion--Kai 0319
IX
FBA_CLK0 FBA_CLK0# FBA_CLK1 FBA_CLK1#
THE FBA_WCKBxx PINS ARE USED ONLY ON GK107 THEY ARE NC FOR GK208/GF108 /GF117
H26
R599 1 (G) R593 1 (G)
1
M30 H30 E34 M34 AF30 AK31 AM34 AF32
R28 AC28
E11 E3 A3 C9 F23 F27 C30 A24
1D5V_VGA_S0
FBA_DEBUG1
FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7
56,57,58,59 57,59
FBA_ODT1 57,59 FBA_CKE1 57,59 FBA_A13 56,57,58,59 FBA_A8 56,57,58,59 FBA_A6 56,57,58,59 FBA_A11 56,57,58,59 FBA_A5 56,57,58,59 FBA_A3 56,57,58,59 FBA_BA2 56,57,58,59 FBA_BA1 56,57,58,59 FBA_A12 56,57,58,59 FBA_A10 56,57,58,59 -FBA_RAS 56,57,58,59
1
QSAN_0 QSAN_1 QSAN_2 QSAN_3 QSAN_4 QSAN_5 QSAN_6 QSAN_7
-FBA_CAS -FBA_CS1
Need to connect FBA_CMD4 to FBA_A14 for support 256Mx16 memory--Kai 0315
R32 AC32
GF117/GK208 GK107/GF108
FBA_DEBUG0 FBA_DEBUG1
56,58
FBA_ODT0 56,58 FBA_CKE0 56,58 FBA_A14 56,57,58,59 FBA_RST 56,57,58,59 FBA_A9 56,57,58,59 FBA_A7 56,57,58,59 FBA_A2 56,57,58,59 FBA_A0 56,57,58,59 FBA_A4 56,57,58,59 FBA_A1 56,57,58,59 FBA_BA0 56,57,58,59 -FBA_WE 56,57,58,59 FBA_A15 56,57,58,59
2
58 56 56 58 59 59 57 57
FBA_CMD_RFU0 FBA_CMD_RFU1
-FBA_CS0
2
M31 G31 E33 M33 AE31 AK30 AN33 AF33
NC NC
U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31
SC10U6D3V3MX-GP
QSAP_0 QSAP_1 QSAP_2 QSAP_3 QSAP_4 QSAP_5 QSAP_6 QSAP_7
FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31
FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63
42D2R2F-GP
58 56 56 58 59 59 57 57
FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7
Place close to Ball
1
P30 F31 F34 M32 AD31 AL29 AM32 AF34
DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7
C443 (G78.10421.2FL)
1
58 56 56 58 59 59 57 57
X7R
2
C
MDA[63..56]
G9 E9 G8 F9 F11 G11 F12 G12 G6 F5 E6 F6 F4 G4 E2 F3 C2 D4 D3 C1 B3 C4 B5 C5 A11 C11 D11 B11 D8 A8 C8 B8 F24 G23 E24 G24 D21 E21 G21 F21 G27 D27 G26 E27 E29 F29 E30 D30 A32 C31 C32 B32 D29 A29 C29 B29 B21 C23 A21 C21 B24 C24 B26 C26
33mA
2
57
MDA[55..48]
FB_PLLVDD
K27
SC10U6D3V3MX-GP
57
MDA[47..40]
FB_DLL_AVDD
(G78.10421.2FL)
59
MDA[39..32]
ALL PINS NC FOR GF117/GK208
2 10KR2J-3-GP
1
59
MDA[31..24]
R129 (G)
1
2
58
MDA[23..16]
FB_CLAMP
E1
SCD1U10V2KX-5GP
56
FB_CLAMP
(G78.10421.2FL)
D
FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63
2
MDA[15..8]
L28 M29 L29 M28 N31 P29 R29 P28 J28 H29 J29 H28 G29 E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32 L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28 AM29 AM31 AN29 AM30 AN31 AN32 AP30 AP32 AM33 AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33
SC22U4V3MX-GP C431 (G78.22610.5BL)
MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63
SCD1U10V2KX-5GP
56
MDA[7..0]
FBA_DEBUG0
58
Near GPU
.F
N14P-GV2 only have one partition (FBA), FBB is NC so you should not connect memory signals to FBB.--Kai 0313
B
1
CLKA0
W R606
R110
1
1
(G)
(G)
R567
(G)
R124
W
2
(G)
10KR2J-3-GP
R93
2
10KR2J-3-GP
(G)
2
FBA_ODT1
1
FBA_ODT0
ODT1
2
FBA_RST
ODT0
10KR2J-3-GP
Reset
1
FBA_CKE1
2
FBA_CKE0
CKE1
1
CKE0
B
W
Group A
CLKA0#
FBCLK Termination place on VRAM side
10KR2J-3-GP
CLKA1#
2
R128 (G) 162R2F-GP
2
R85 (G) 162R2F-GP
10KR2J-3-GP
1
CLKA1
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
GPU_VRAM I/F(3/5) Size A1 Date: 5
4
3
2
Document Number
Rev
SA
Madrid
Tuesday, January 21, 2014 1
Sheet
53
of
68
5
4
3
1
1
3D3V_VGA_S0 RN1 (G) SRN2K2J-1-GP
(R)
6
GPU_SMDAT0 Q11 2N7002KDW-GP
TP7 TP5
TPAD28 TPAD28
AK9
VGA_CRT_RED
TP8
AL10
VGA_CRT_GREEN
TP10
TPAD28
AL9
VGA_CRT_BLUE
TP9
TPAD28
20130426 SWAP D/S connection by NV_Ryan
TPAD28
10/19 MISC1
I2CS_SCL I2CS_SDA I2CC_SCL I2CC_SDA
N14P-GS-A1-GP (G) TPAD28
TP95
TP_THERMDN
K4
TPAD28
TP12
TP_THERMDP
K3
TPAD28 TPAD28 TPAD28
TP6 TP4 TP3
R80 10KR2J-3-GP
1
AM10 AP11 AM11 AP12 AN11
THERMDP
GF117
1 2
NC NC NC
GK208
GF117
GPIO16 NC NC GK107
TP90 TP11
TP94 TP91
GPIO10_MEM_VREF_CTL GPIO11_PWM_VID
GPIO9_ALERT#
GPIO12_AC_DETECT GPIO13_NVVDD_PSI
GPIO11_PWM_VID
2
R603 (G)
R604 (G)
R600 (G)
R601 (G)
R123
(R)
2 3
2
4
1
R120 390R2J-1-GP (G63.10234.1DL)
20140114 Madrid 1A Charles change to 1K
27MHZ_OUT_R
1
1
2
2
C88 (G) SC15P50V2JN-2-GP
C87 SC15P50V2JN-2-GP (G)
PCI_DEVID[1] 0
SOR0_EXPOSED
0
0
PCI_MAX_SPEED
DP_PLL_VDD33V
1
1
External BIOS ROM
3D3V_VGA_S0
Reserve EEPROM for VBIOS U30
MX25L1006EMI-10G-GP (R72.02510.001) C55 (R)
2
1
ROM_CS_R*
2
SCD1U16V2KX-3GP
33R2J-2-GP
ROM_SI_R
33R2J-2-GP
3D3V_VGA_S0
UNUSED(No Need to Set in VBIOS)
GPIO 14
N/A on Package
GPIO 15
N/A on Package
GPIO 16
N/A on Package
GPIO 17
N/A on Package
GPIO 18
N/A on Package
GPIO 19
N/A on Package
GPIO 20
N/A on Package
GPIO 21
N/A on Package
C
W
13/11/02 modify VRAM strap R619 (default set Hynix)--Kai Hynix H5TC4G63AFR-11C R619=4.99K(64.49915.6DL)
A
R112 2KR2J-1-GP
1
45K3R2F-L-GP R618 24K9R2F-L-GP
2
(R)
R605 45K3R2F-L-GP (R)
(R)
STRAP3
1 (R)
(R)
STRAP4 R607 4K99R2F-L-GP
(R) R610 15KR2F-GP
R108 4K99R2F-L-GP
20131024 Madrid SA Charle
20131029 Madrid SA Charles NV Review R113 45K3R2F-L-GP (R)
7,12 60
H_THERMTRIP_N GPU_THERM_SHUTDOWN*
R119 1 (R)
2 0R2J-2-GPGPU_THERM_SHUTDOWN*_R
R118 1
2 0R2J-2-GP
Q13 PMBS3904-1-GP (G84.T3904.H11)
1
PCIE_MAX_SPEED Strap--STRAP4
2
(G) C86 SCD1U16V2ZY-2GP
Change R8619 to 45.3K.--Kai 0313
1 (G) R127 10KR2J-3-GP
C89 SC1KP50V2JN-2GP (G78.10224.2FL)
GPU_3D3V_S0_THERM
3D3V_VGA_S0
R114
1
2 2K2R2J-2-GP
GPU_PLTRST
(G) R103
1
GPIO8_OVERT#
2 2K2R2J-2-GP
(G)
2 R125
(G)
1GPU_THERM_SHUTDOWN*_2
1
10KR2J-3-GP
(G64.33025.6DL) R126 33KR2J-3-GP
A
Q12 Q15 PMBS3904-1-GP (G84.T3904.H11)
C90 SC1KP50V2JN-2GP (G78.10224.2FL)
G
(G84.2N702.J31) 2N7002A-7-GP
PLTRST_N_1A 2
R117
1
(G) 1KR2J-1-GP
(G) C84 SC100P50V2JN-3GP
PLTRST_GPU#
20,51
2
Unstuff R8634, Stuff R8635 with 10K.--Kai 0313 R8635 should be 15K--Kai 0314
1
PMBS3906-GP Q14 (G84.T3906.E11)
GPU_THERM_SHUTDOWN*_1 2
1
2
(R)
R613 34K8R2F-1-GP
1
STRAP0 STRAP1 STRAP2
(R)
R623
GPU_3D3V_S0_THERM_2
VGA_DEVICE Strap--ROM_SO_C4
R111 45K3R2F-L-GP (G64.49925.6DL)
2
SMB_ALT_ADDR Strap--ROM_SLK_D4
3D3V_VGA_S0
20131029 Madrid SA Charles NV Review
1
SUB_VENDOR Strap--ROM_SI_D3
THERMAL PROTECTION
3D3V_VGA_S0
3D3V_VGA_S0
Samsung K4W4G1646D-BC1A R619=15K(64.15025.6DL)
2
2
2
R611 4K99R2F-L-GP (G)
1
2 R617 4K99R2F-L-GP
(G)
20131029 Madrid SA Charles NV Review With GB4B-128: Unstuff R616, Stuff R611 with 4.99K Unstuff R626, Stuff R617 with 4.99K The strapping value of ROM_SI depends on which memory part will be use. Change R111 to 50K Unstuff R605, Unstuff R610, Unstuff R607, Unstuff R113
1
1 R619 4K99R2F-L-GP (G)
R616 4K99R2F-L-GP (R)
2
1 R626 4K99R2F-L-GP
(R)
1
R621 10KR2F-2-GP
2
(R) ROM_SI ROM_SO ROM_SCLK
1
1 2
L3
2
CEC
CEC IS NC FOR GK107/GK208/GF117
N14P-GS-A1-GP (G)
2
MULTI_STRAP_REF
(G) R115 40K2R2F-GP
1
J1
L2
1
BUFRST#
PWR_Level AC Detect
GPIO 13
W
NC NC GF108
GK107/GF117 GK208
STRAP_REF0_GND_N9
ROM_SI ROM_SO ROM_SCLK
2
STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
ROM_CS*
1
J2 J7 J6 J5 J3
H6 H5 H7 H4
2
STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
ROM_SI ROM_SO ROM_SCLK
2
ROM_CS#
FB Vref Control
GPIO 12
W
33R2J-2-GP
12/17 MISC2
2
16 OF 17
VGA1P
ROM_SCLK_R
1
2
GPU Thermal Alert
NVVDD PWM_VID
B
2
2
R615 1 (R)
20131121 Madrid SB Charles Modify As winbom 1M
1
2
R625 1 (R)
8 7 6 5
R627
(R)10KR2F-2-GP
R624 1 (R)
VCC HOLD# SCLK SI/SIO0
1
1
CS# SO/SIO1 WP# GND
GPU Overtemp
GPIO 11
.F
1 2 3 4
3D3V_VGA_S0 B
3DVision(UNUSED)
GPIO 10
1
0
FB_CLAMP_TGL_REQ
GPIO 9
2
PCI_SPEED_CHANGE_GEN3
0
N11P Fermi QS 1
1
SOR1_EXPOSED
0
0 RESERVED
PEX_PLL_EN_TERM =0 SLOT_CLK_CFG =1 SUB_VENDOR =0 PCI_DEVID[4] =1
PCI_DEVID[0]
Reserved
GPIO 6
D
0 SOR2_EXPOSED
GPU_ROM_SCLK
0
UNUSED
GPIO 5
S
STRAP3
1 3GPO_PADCFG[0]
3
1 SOR3_EXPOSED
STRAP4
1 3GPO_PADCFG[1] 1
PCI_DEVID[2]
VGA_DEVICE =1 (low bit) SMB_ALT_ADDR =0 FB_0_BAR_SIZE =0 XCLK_417 =0 (High bit)
GPU_ROM_SO
1 USER[0]
1
PCI_DEVID[3]
STRAP2
for 2Gbit Samsung VRAM RAM_CFG[0]=1 RAM_CFG[1]=1 RAM_CFG[2]=1 RAM_CFG[3]=0
2
1
1
for 1Gbit Samsung VRAM RAM_CFG[0]=1 RAM_CFG[1]=1 RAM_CFG[2]=0 RAM_CFG[3]=0
VGA_DEVICE
0 USER[1]
3GPO_PADCFG[2]
0
for 2Gbit Hynix VRAM RAM_CFG[0]=0 RAM_CFG[1]=1 RAM_CFG[2]=1 RAM_CFG[3]=0
UNUSED
GPIO 4
2
1 3GPO_PADCFG[3]
STRAP1
SMB_ALT_ADDR
0 USER[2]
for 1Gbit Hynix VRAM RAM_CFG[0]=0 RAM_CFG[1]=1 RAM_CFG[2]=0 RAM_CFG[3]=0
GPU_ROM_SI
0 1
3
Bar_size
1 USER[3]
0 RAM_CFG[0]
1 1
GPIO 3
AM
0 0
PCI_PLL_EN_TER_M
1 RAM_CFG[1]
3
0 0
Logical strapping name bit0#
2
0 RAM_CFG[2]
PCI_DVID[5]
UNUSED
LA T
0 RAM_CFG[3]
XCLK_417
ROM_SO
STRAP0
Logical strapping name bit1#
SUB_VENDOR
MEM_VDD_CTL
GPIO 2
IX
ROM_SI Hynix Samsung
Logical strapping name bit2#
FAN_PWM/FB_CLAMP/DEBUG Service
GPIO 1
GPIO 8
27MHZ_OUT
(G)
GF117
GPIO 0
GPIO 7
Strap PCI_DEVID[4]
GPIO
60
R106 (G)
R609 10KR2J-3-GP
20130507 COST DOWN PART_Ryan
ROM_SCLK
60
GF108
XTAL-27MHZ-137-GP
Strap pin name Logical strapping name bit3#
34,60
GPIO13_NVVDD_PSI
1 (G)
1 1MR2J-1-GP 2
X1
C
TPAD28 (G) TPAD28 (G)
TPAD28 (G) TPAD28 (G)
.C O
1
20PF 5% 50V +/-0.25PF 0402
R116 10KR2J-3-GP
2
Add CAP follow vendor suggestion--Kai 0314 remove L8603 / L8604 follow vendor suggestion--Kai 0319
2 R100
H2
XTAL_OUT
N14P-GS-A1-GP (G)
27MHZ_IN
2 R101
1 (G)
GPIO5_PWM_VID_BOOT_EN GPIO6_FB_CLAMP_TGL_REQ GPIO7_3D_STEREO GPIO8_OVERT# GPIO9_ALERT#
N14P-GS-A1-GP (G)
N12P_XTAL_OUTBUFF
J4
XTAL_OUTBUFF
XTAL_IN
2 R102
1 (G)
GPIO1_FBVDDQCTL GPIO2_BL_PWM GPIO3_PPEN_R GPIO4_BLEN
GF117
XTAL_SSIN
1 (G)
100KR2J-1-GP
GPIO0_FB_CLAMP
P6 M3 L6 P5 P7 L7 M7 N8 M1 M2 L1 M5 N3 M4 R8 P4 P1
1
H1 H3
(G)
GPIO16 GPIO20 GPIO8
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO16 GPIO20 GPIO21
2
1
1
VIDEO_CLK_XTAL_SS
TP13
1
(G78.10421.2FL) SCD1U10V2KX-5GP
2
GF108/GK107 GK208
2
1
1 2
C408
TPAD28
100KR2J-1-GP
GPIO9_ALERT#
GK208
100KR2J-1-GP
C409
GPIO8_OVERT#
100KR2J-1-GP
NC
VID_PLLVDD
D
R7 R6
100KR2J-1-GP
C404
AD7
3D3V_VGA_S0
I2CC_SCL_PU I2CC_SDA_PU
R2 R3
100KR2J-1-GP
(G)
PLLVDD SP_PLLVDD
20R2J-2-GP SMB_CLK 2 0R2J-2-GPSMB_DATA
100KR2J-1-GP
(G) C403
SC4D7U6D3V3KX-GP
C417 (G78.10520.5FL)
11/17 XTAL_PLL
1 (R) 1 (R)
100KR2J-1-GP
MHC1608S300QBP-GP
15 OF 17
VGA1O
SMB_CLK_GPU R94 SMB_DATA_GPU R95
GK107/GF108
JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST#
C416
AD8 AE8
T4 T3
GPIO12_AC_DETECT
GK208 OVERT
SP_PLLVDD_L
SC22U6D3V3MX-1-GP
SC1U10V2KX-1GP
1
2
2
1
NEAR GPU
(G78.10421.2FL) SCD1U10V2KX-5GP
2 (G68.00335.181)
(G78.10421.2FL) SCD1U10V2KX-5GP
1
(G) C419 SC22U6D3V3MX-1-GP
L47
2
N12P_GPIO_JTAG_TRST
I2CB_SCL I2CB_SDA
2 MHC1608S300QBP-GP
1D05V_VGA_S0
N12P_JTAG_TCK N12P_JTAG_TMS N12P_JTAG_TDI N12P_JTAG_TDO
2
NC NC
THERMDN
R83 (G) 10KR2J-3-GP
UNDER GPU
(G68.00335.181)
L48
1
1D05V_VGA_S0
2
(R)
1
PLLVDD_PWR
(G) R97 2K2R2J-2-GP
17 OF 17
VGA1Q
2
DACA_BLUE
(G) R98 2K2R2J-2-GP
1
DACA_GREEN
NC
3D3V_VGA_S0
2 0R2J-2-GP
2
DACA_RED
NC
1 (R)
R89
2
(G78.10421.2FL) CD1U10V2KX-5GP
NC
SMB_CLK SMB_DATA
1
(G)
DACA_HSYNC DACA_VSYNC
9,10,13,21,22,46 9,10,13,21,22,46 SMB_CLK_GPU
GPU_SMCLK0
M
VGA_CRT_HSYNC VGA_CRT_VSYNC
1
NC NC
3
1
AM9 AN9
20
NC
DACA_RSET
2
4
(G75.27002.F7C)
TSEN_VREF
DACA_VREF
R84 124R2F-U-GP
2
I2CA_SCL I2CA_SDA
TPAD28 TPAD28
2
NC NC
TP89 TP92
2
NC
DACA_VDD
VGA_CRT_DDCCLK VGA_CRT_DDCDATA
1
1 1 C41S D
AP8
R4 R5
1
AP9
DACA_RSET
SMB_DATA_GPU
1
5
DGPU_PWROK
84.2N702.A3F 2nd = 84.DM601.03F
GF108/GK107 GK208
GF117
1
DACA_VREF_AK12
GF117
20R2J-2-GP
(R)
2
20 60,61
14 OF 17
4/17 DACA GF108/GK107 GK208
1
R90
2
X7R, Under GPU.
VGA1N
AG10
4 3
C415
1
(R)
2
C400
2
(R)
1 2
1
1
C421
2
1
(R)
2
1 2
X7R
2
1 2
C413
SC4D7U6D3V3KX-GP
2
X7R
SC1U10V2KX-1GP
10KR2J-3-GP
(R)
SCD1U10V2KX-5GP
C414
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
(G)
X7R
1
2
(R)
R588
2
3D3V_VGA_S0
L49 MMZ1608S301CTAH0-GP
3D3V_VGA_S0_DACA_VDD_16MIL
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
GPU_GPIO/STRAP(4/5) Size Custom Date:
5
4
3
2
1
Document Number
Rev
Madrid
Tuesday, January 21, 2014
SA Sheet
54
of
68
5
4
3
2
1
EDP 50A (TDP 37W) 7 OF 17
VGA1G VGA_CORE
16/17 GND_2/2
1
1
2
2 (G78.10421.2FL)
2 (G78.10421.2FL)
(G78.10421.2FL)
1
1 2
(G78.10421.2FL)
(G78.10421.2FL)
1
(G78.10421.2FL)
2
C407
SCD1U10V2KX-5GP
C411
SCD1U10V2KX-5GP
C412
SCD1U10V2KX-5GP
C418
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
2
AG11
GND_F
C36 (R)
C16 W32
GND_OPT_1 GND_OPT_2 NC for 4-Lyr cards
N14P-GS-A1-GP (G)
9 OF 17
VGA1I 9/17 XVDD CONFIGURABLE POWER CHANNELS
XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8 XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16
N14P-GS-A1-GP (G)
W
C
Optional CMD GNDs (2)
N14P-GS-A1-GP (G)
XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22
5 OF 17
VGA1E
D
AH11
GND_H
.F
(G)
T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23
GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198
W
2
C426
(G)
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
NEAR TO GPU
(G)
1
1
C449 (G)
2
1
2 1 2
C427
2
2
B
1
1
1
1
2
1 2
1
1 2
1
2
2
2
2 (G)
SC22U4V3MX-GP C37 (R78.22610.5BL)
C442
SC4D7U6D3V3KX-GP
(G)
SC22U4V3MX-GP C448 (G78.22610.5BL)
(G)
SC4D7U6D3V3KX-GP
C441
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
C440
SC22U4V3MX-GP C401 (G78.22610.5BL)
SC22U4V3MX-GP C425 (G78.22610.5BL)
SC22U4V3MX-GP C445 (G78.22610.5BL)
NEAR TO GPU
SC22U4V3MX-GP C450 (G78.22610.5BL)
SC22U4V3MX-GP C447 (G78.22610.5BL)
1
NEAR TO GPU
1
C
C664
2
1
Under GPU C665
C434
2
(G)
GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169
M
C433
2
(G)
AM25 AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34 AN4 AN7 AP2 AP33 B1 B10 B22 B25 B28 B31 B34 B4 B7 C10 C13 C19 C22 C25 C28 C7 D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16
AM
C432
VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71 VDD_72
GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99 GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140
LA T
(G)
1
1
1 C429
2
(G)
AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23 M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15 V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22
15/17 GND_1/2
GND_1 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_2 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_3 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_4 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70
IX
(G)
2
C428
2
2
1
1
1
1 2
2
2
C436
SC4D7U6D3V3KX-GP
(G)
SC4D7U6D3V3KX-GP
C439
SC4D7U6D3V3KX-GP
(G)
SC4D7U6D3V3KX-GP
C438
SC4D7U6D3V3KX-GP
(G)
SC4D7U6D3V3KX-GP
C435
SC4D7U6D3V3KX-GP
(G)
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
2
1
1
1
D
C446
A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19 AB2 AB21 A33 AB23 AB28 AB30 AB32 AB5 AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22 AE2 AE28 AE30 AE32 AE33 AE5 AE7 AH10 AA15 AH13 AH16 AH19 AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33 AH5 AH7 AJ7 AK10 AK7 AL12 AL14 AL15 AL17 AL18 AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33 AL5 AM13 AM16 AM19 AM22
8 OF 17 13/17 NVVDD
.C O
VGA1H
Under GPU
N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22
6 OF 17
VGA1F
U1 U2 U3 U4 U5 U6 U7 U8 V1 V2 V3 V4 V5 V6 V7 V8
B
W2 W3 W4 W5 W7 W8
THESE PINS
XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30
(G)
C452
1
1
X7R
C393 (G)
XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38
N14P-GS-A1-GP (G)
Change C8709 to 0.1uF, Add additional 0.1uF at 3V3MISC..--Kai 0314
A
N14P-GS-A1-GP (G)
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
1U NEAR TO GPU
Size Custom Date: 3
A
Wistron Corporation
4.7U NEAR TO GPU
4
AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8
0.1U Under GPU
5
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
2
2
C471
2
1
X7R
(G78.10421.2FL)
CONNECT
C462
(G78.10421.2FL)
C453
(G78.10421.2FL)
DO NOT
1
X7R
2
1
L8 M8
2
VDD33_1 VDD33_2
SC4D7U6D3V3KX-GP
W
1 2
2
3V3MISC_1 3V3MISC_2
SCD1U10V2KX-5GP
DNU#AC6 DNU#AJ4 DNU#AJ5 DNU#AL11 DNU#T8
3V3MISC 3V3MISC
J8 K8 SCD1U10V2KX-5GP
AC6 AJ4 AJ5 AL11 T8
NC#AJ28 NC#C15 NC#D19 NC#D20 NC#D23 NC#D26 NC#H31 NC#V32
3D3V_VGA_S0 GK107
SC1U6D3V2KX-GP
(R)
C370 (R) SC47U6D3V5MX-1-GP
TC2
SE470UF2VDM-GP
NEAR TO GPU
AJ28 C15 D19 D20 D23 D26 H31 V32
GK208 GF117
SCD1U10V2KX-5GP
1
17/17 NC/VDD33
2
GPU_PWR/GND(5/5)
Document Number
Madrid
Tuesday, January 21, 2014
Rev
SA Sheet 1
55
of
68
5
4
3
2
1
CHANNEL A:2GB DDR3 MICRON 256x16 900MHz 4Gb MT41K256M16HA-107G:E LF+HF KN.00404.001
1D5V_VGA_S0 VRAM2
FBA_BA0 FBA_BA1 FBA_BA2
M2 N8 M3
53,58 53,58
CLKA0 CLKA0#
53,58 53 53
J7 K7 K9
FBA_CKE0
D3 E7
DQMA1 DQMA2
53,57,58,59 53,57,58,59 53,57,58,59
L3 K3 J3
-FBA_WE -FBA_CAS -FBA_RAS
BA0 BA1 BA2 CK CK#
CS# RESET# NC#M7 NC#L9 NC#L1 NC#J9 NC#J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
CKE VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
DMU DML W E# CAS# RAS#
L2 T2 M7 L9 L1 J9 J1 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
M
53 53
.C O
53,57,58,59 53,57,58,59 53,57,58,59
ODT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14
QSAP_2 QSAN_2 53,58
-FBA_CS0 FBA_RST
53,58 53,57,58,59
FBA_A15
53,57,58,59
1D5V_VGA_S0
VRAM1_VREF (G)
G1 F9 E8 E2 D8 D1 B9 B1 G9
VRAM1_VREF
R612 1K33R2F-GP (G)
C
R602 1K33R2F-GP
VRAM1_VREF
C465 SCD01U50V2KX-1GP
2
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7
FBA_ODT0
53 53
1
Need to connect FBA_CMD4 to FBA_A14 for support 256Mx16 memory--Kai 0315
FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 FBA_A14
K1
QSAP_1 QSAN_1
AM
C
53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59 53,57,58,59
C7 B7 F3 G3
53
LA T
1
R121 243R2F-2-GP (G)
MDA[15..8]
MDA12 MDA8 MDA15 MDA10 MDA13 MDA9 MDA14 MDA11
D
C458 SCD01U50V2KX-1GP
(G)
IX
DQSL DQSL#
2
VRAM_ZQ2
DQSU DQSU#
VREFDQ VREFCA ZQ
Hynix 256x16 900MHz 4Gb H5TQ4G63MFR-11C KN.0040G.006
1
H1 M8 L8
D7 C3 C8 C2 A7 A2 B8 A3
53
2
VRAM1_VREF
MDA[23..16]
MDA23 MDA19 MDA22 MDA16 MDA21 MDA18 MDA20 MDA17
2
VRAM1_VREF
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
E3 F7 F2 F8 H3 H8 G2 H7
1
A8 A1 C1 C9 D2 E9 F1 H9 H2
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
1
D
VDD VDD VDD VDD VDD VDD VDD VDD VDD
2
K8 K2 N1 R9 B2 D9 G7 R1 N9
(G)
W
OBS,follow Lily_Tripoli--Kai 0311
W
1
W
2
2
C91
DG requires 4x0.1uF and 8x1.0uF per VRAM chip
1D5V_VGA_S0
1 2
1 2
C69 (G78.10520.5FL)
1 2
(G78.10520.5FL)
(G78.10520.5FL)
2
C58
SC1U10V2KX-1GP
C424
SC1U10V2KX-1GP
1
(G78.10421.2FL) (G78.10421.2FL)
SC1U10V2KX-1GP
SC1U10V2KX-1GP
A
C92
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
FOR VRAM1
1
1D5V_VGA_S0
B
SC10U6D3V3MX-GP 2 1
B
.F
K4W4G1646B-HC11-GP (GKN.0040G.002)
C423 (G)
CLOSE TO THE MEMORY
A
C479 (G78.10520.5FL)
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
GPU-VRAM1 (1/4) Size Custom
Add VRAM decoupling cap--Kai 0315
Date: 5
4
3
2
Document Number
Rev
SA
Madrid
Tuesday, January 21, 2014
Sheet 1
56
of
68
4
3
2
VRAM1
53,59 53,59
53,59 53 53
J7 K7
CLKA1 CLKA1#
K9
FBA_CKE1
D3 E7
DQMA6 DQMA7
53,56,58,59 53,56,58,59 53,56,58,59
L3 K3 J3
-FBA_WE -FBA_CAS -FBA_RAS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BA0 BA1 BA2 CK CK# CKE
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
DMU DML WE# CAS# RAS#
M7 L9 L1 J9 J1 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
-FBA_CS1 FBA_RST
53,59 53,56,58,59
FBA_A15
53,56,58,59
VRAM3_VREF
G1 F9 E8 E2 D8 D1 B9 B1 G9
VRAM3_VREF
(G)
R88 1K33R2F-GP
C410 SCD01U50V2KX-1GP
(G)
(G)
.F
FB CMD mapping Mode D-N12x
B
VRAM SAMSUNG 1Gb S72.41646.Q0U VRAM HYNIX 1Gb H72.51G63.H0U
W W
1 2
C94
1D5V_VGA_S0
W 1 2
1 (G78.10520.5FL)
(G78.10520.5FL)
2
1 2
(G78.10520.5FL)
C39
SC10U6D3V3MX-GP
SC1U10V2KX-1GP
C38
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C62 2
C394 SCD01U50V2KX-1GP
(G78.10421.2FL) (G78.10421.2FL)
1
2
C42
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
A
1
FOR VRAM3 CLOSE TO THE MEMORY
R595 1K33R2F-GP
(G)
VRAM3_VREF
OBS,follow Lily_Tripoli--Kai 0311
1D5V_VGA_S0
C
1D5V_VGA_S0
K4W4G1646B-HC11-GP (GKN.0040G.002)
B
M
M2 N8 M3
NC#M7 NC#L9 NC#L1 NC#J9 NC#J1
L2 T2
53 53
53,59
.C O
FBA_BA0 FBA_BA1 FBA_BA2
CS# RESET#
QSAP_7 QSAN_7
2
53,56,58,59 53,56,58,59 53,56,58,59
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14
FBA_ODT1
D
AM
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7
K1
53 53
1
Need to connect FBA_CMD4 to FBA_A14 for support 256Mx16 memory--Kai 0315
FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 FBA_A14
ODT
QSAP_6 QSAN_6
Hynix 256x16 900MHz 4Gb H5TQ4G63MFR-11C KN.0040G.006
1
C
53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59 53,56,58,59
DQSL DQSL#
F3 G3
53
2
1
R92 243R2F-2-GP (G)
VREFDQ VREFCA ZQ
C7 B7
MDA[55..48]
MICRON 256x16 900MHz 4Gb MT41K256M16HA-107G:E LF+HF KN.00404.001
2
2
VRAM_ZQ3
DQSU DQSU#
MDA51 MDA53 MDA50 MDA52 MDA48 MDA54 MDA49 MDA55
53
2
H1 M8 L8
D7 C3 C8 C2 A7 A2 B8 A3
MDA[63..56]
1
VRAM3_VREF
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
MDA58 MDA57 MDA62 MDA60 MDA63 MDA61 MDA56 MDA59
LA T
VRAM3_VREF
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
E3 F7 F2 F8 H3 H8 G2 H7
1
A8 A1 C1 C9 D2 E9 F1 H9 H2
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
2
D
VDD VDD VDD VDD VDD VDD VDD VDD VDD
IX
K8 K2 N1 R9 B2 D9 G7 R1 N9
1
CHANNEL A:2GB DDR3
1D5V_VGA_S0
1
5
C34 (G)
CLOSE TO THE MEMORY
C56 (G78.10520.5FL)
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom
Add VRAM decoupling cap--Kai 0315
GPU-VRAM3 (2/4)
Document Number
Madrid
Date: Tuesday, January 21, 2014 5
4
3
2
Rev
SA Sheet 1
57
of
68
4
3
2
CHANNEL B:2GB DDR3
1D5V_VGA_S0 VRAM4
H1 M8 L8
DQSL DQSL#
2
VRAM_ZQ1
DQSU DQSU#
VREFDQ VREFCA ZQ
Need to connect FBA_CMD4 to FBA_A14 for support 256Mx16 memory--Kai 0315
FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 FBA_A14
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7
53,56,57,59 53,56,57,59 53,56,57,59
FBA_BA0 FBA_BA1 FBA_BA2
M2 N8 M3
53,56 53,56
53,56 53 53
J7 K7
CLKA0 CLKA0#
K9
FBA_CKE0
D3 E7
DQMA0 DQMA3
53,56,57,59 53,56,57,59 53,56,57,59
L3 K3 J3
-FBA_WE -FBA_CAS -FBA_RAS
CKE
WE# CAS# RAS#
53,56 53,56,57,59
FBA_A15
53,56,57,59
G1 F9 E8 E2 D8 D1 B9 B1 G9
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
53,56
-FBA_CS0 FBA_RST
J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
DMU DML
FBA_ODT0
M7 L9 L1 J9 J1
NC#M7 NC#L9 NC#L1 NC#J9 NC#J1
CK CK#
53 53
L2 T2
CS# RESET#
BA0 BA1 BA2
QSAP_3 QSAN_3
K1
ODT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14
53 53
C
VRAM1_VREF
C85 SCD01U50V2KX-1GP
(G)
.F
K4W4G1646B-HC11-GP (GKN.0040G.002)
OBS,follow Lily_Tripoli--Kai 0311 N14P-GV2 only have one partition (FBA)--Kai 0313
W
1D5V_VGA_S0
2
1
1
C459
W
(G78.10520.5FL)
1
1 2
1 2
1 2
(G78.10520.5FL)
C437 (G78.10520.5FL)
1
SC10U6D3V3MX-GP
C35
SC1U10V2KX-1GP
C470
SC1U10V2KX-1GP
C455
C473 2
2
DG requires 4x0.1uF and 8x1.0uF per VRAM chip
(G78.10421.2FL) (G78.10421.2FL)
SC1U10V2KX-1GP
SC1U10V2KX-1GP
A
C397
SCD1U10V2KX-5GP
CLOSE TO THE MEMORY
SCD1U10V2KX-5GP
FOR VRAM2
B
W
1D5V_VGA_S0
(G78.10520.5FL)
B
2
C
53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59 53,56,57,59
QSAP_0 QSAN_0
F3 G3
IX
1
R122 243R2F-2-GP (G)
C7 B7
D
1
VRAM1_VREF
MDA7 MDA0 MDA6 MDA2 MDA4 MDA3 MDA5 MDA1
Hynix 256x16 900MHz 4Gb H5TQ4G63MFR-11C KN.0040G.006
53
M
VRAM1_VREF
D7 C3 C8 C2 A7 A2 B8 A3
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
MDA[7..0]
MICRON 256x16 900MHz 4Gb MT41K256M16HA-107G:E LF+HF KN.00404.001
53
.C O
A8 A1 C1 C9 D2 E9 F1 H9 H2
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
MDA[31..24]
MDA26 MDA27 MDA28 MDA30 MDA24 MDA31 MDA25 MDA29
AM
D
VDD VDD VDD VDD VDD VDD VDD VDD VDD
E3 F7 F2 F8 H3 H8 G2 H7
LA T
K8 K2 N1 R9 B2 D9 G7 R1 N9
1
2
5
(G)
CLOSE TO THE MEMORY
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom
Add VRAM decoupling cap--Kai 0315
GPU-VRAM2 (3/4)
Document Number
Madrid
Date: Tuesday, January 21, 2014 5
4
3
2
Rev
SA Sheet 1
58
of
68
4
3
2
VRAM3
1
R574 243R2F-2-GP (G)
Need to connect FBA_CMD4 to FBA_A14 for support 256Mx16 memory--Kai 0315
FBA_A0 FBA_A1 FBA_A2 FBA_A3 FBA_A4 FBA_A5 FBA_A6 FBA_A7 FBA_A8 FBA_A9 FBA_A10 FBA_A11 FBA_A12 FBA_A13 FBA_A14
N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7
53,56,57,58 53,56,57,58 53,56,57,58
FBA_BA0 FBA_BA1 FBA_BA2
M2 N8 M3
53,57 53,57
53,57 53 53
J7 K7
CLKA1 CLKA1#
K9
FBA_CKE1
D3 E7
DQMA4 DQMA5
53,56,57,58 53,56,57,58 53,56,57,58
L3 K3 J3
-FBA_W E -FBA_CAS -FBA_RAS
ODT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14
CS# RESET# NC#M7 NC#L9 NC#L1 NC#J9 NC#J1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
BA0 BA1 BA2 CK CK# CKE
VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ
DMU DML WE# CAS# RAS#
QSAP_4 QSAN_4
53 53
F3 G3
QSAP_5 QSAN_5
53 53
K1
FBA_ODT1
L2 T2
53,57 53,56,57,58
FBA_A15
53,56,57,58
M7 L9 L1 J9 J1 J8 M1 M9 J2 P9 G8 B3 T1 A9 T9 E1 P1 G1 F9 E8 E2 D8 D1 B9 B1 G9
53,57
-FBA_CS1 FBA_RST
B
VRAM3_VREF
1
W 1 2
1
C44 (G)
1
1 (G78.10520.5FL)
(G78.10520.5FL)
C72 2
1 2
(G78.10520.5FL)
2
C33
SC1U10V2KX-1GP
1
W
2
SC10U6D3V3MX-GP
C74
SC1U10V2KX-1GP
C406
A
C93 (G78.10520.5FL)
Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom
Add VRAM decoupling cap--Kai 0315
GPU-VRAM4 (4/4)
Document Number
Madrid
Date: Tuesday, January 21, 2014 5
4
C54 SCD01U50V2KX-1GP
1D5V_VGA_S0
(G78.10421.2FL) (G78.10421.2FL)
SC1U10V2KX-1GP
SC1U10V2KX-1GP
A
C384
SCD1U10V2KX-5GP
SCD1U10V2KX-5GP
CLOSE TO THE MEMORY
C
CLOSE TO THE MEMORY
W
1D5V_VGA_S0
D
B
OBS,follow Lily_Tripoli--Kai 0311
FOR VRAM4
Hynix 256x16 900MHz 4Gb H5TQ4G63MFR-11C KN.0040G.006
(G)
.F
K4W 4G1646B-HC11-GP (GKN.0040G.002)
53
C7 B7
2
C
53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58 53,56,57,58
DQSL DQSL#
MDA[39..32]
MICRON 256x16 900MHz 4Gb MT41K256M16HA-107G:E LF+HF KN.00404.001
2
2
VRAM_ZQ4
DQSU DQSU#
VREFDQ VREFCA ZQ
MDA33 MDA37 MDA32 MDA36 MDA35 MDA39 MDA34 MDA38
53
1
H1 M8 L8
D7 C3 C8 C2 A7 A2 B8 A3
MDA[47..40]
M
VRAM3_VREF
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ
MDA43 MDA42 MDA45 MDA40 MDA46 MDA41 MDA44 MDA47
.C O
VRAM3_VREF
DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7
E3 F7 F2 F8 H3 H8 G2 H7
AM
A8 A1 C1 C9 D2 E9 F1 H9 H2
DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7
LA T
D
VDD VDD VDD VDD VDD VDD VDD VDD VDD
IX
K8 K2 N1 R9 B2 D9 G7 R1 N9
1
CHANNEL B:2GB DDR3
1D5V_VGA_S0
2
5
3
2
Rev
SA Sheet 1
59
of
68
4
3
2
1
20131206 Madrid SB Charles PC4,PC5,PC6,PC7,PC9,PC10 Always mount for UMA EMI solution
1
1
1 2
1 2
1 2
1
1 2
1 2
1
(G) PC79 SC1500P50V3KX-GP
1 2
1
(G) PTC8
1
1
(G) PC26
2
2
(G) PR135 2D2R5J-1-GP
1
2 5 6 7 8
0R0603-PAD 2
1 PR143
0R0603-PAD 2
1 PR36
0R0603-PAD 2
1 PR35
0R0603-PAD 2
1 PR136
0R0603-PAD 2
1 PR137
0R0603-PAD 2
1 PR138
0R0603-PAD 2
1 PR139
0R0603-PAD 2
1 PR140
0R0603-PAD 2
1 PR141
0R0603-PAD 2
1 PR37
0R0603-PAD 2
1 PR31
0R0603-PAD 2
1 PR32
0R0603-PAD 2
1 PR33
0R0603-PAD 2
1 PR34
Iomax=40A OCP>60A
(G) PTC9
B
madrid 20131017 Charles power ask to modify as 09.8271N.A5L
2
3 2 1
2
1
1 2
2
5 6 7 8 3 2 1
3 2 1
1 PR142
2 IND-D36UH-19-GP
2
5 6 7 8
1 2
2
2
IX
(G84.010DP.037) PQ2
1 2
(G) PR132 100R2F-L1-GP-U
PR129 2 0R0402-PAD
1
VGACORE_GND_SENSE_1
51
VGACORE_VDD_SENSE_1
51
(G) PC78 SC47P50V2JN-3GP
(G) PR126 51R2F-2-GP
2
NCP81172_FB1 1
2
PWR_VGA_CORE_SENCE+_1
(G) PR130 2 10KR2F-2-GP 1
1
PR133 2 0R0402-PAD
A
(G) PR134 100R2F-L1-GP-U
2
.F
W
W
VGA_CORE
0R0603-PAD 2
1
LA T
2
5 6 7 8
AM
1 2 1 1 2
1 2 1
W
(R) PTC1
E820U2D5VM-7-GP
2
5 6 7 8
2
2 2 2
2
1
1
1
2
1 2
1
VDDC_PWR
1
E820U2D5VM-7-GP
4
20131206 Madrid SB Charles Unmount PTC1 ; Add PC104,PC109,PC157 [Layout] PC104 place back to PC4 PC109 place back to PC9 PC157 place back to PC57
0.36uH, DCR=1.05~1.2mohm, Idc=30A
SC22U6D3V5MX-2GP
2
(G) PC109
SC10U25V5KX-GP
1
PC9
(G) PC104
SC10U25V5KX-GP
5
D
330uF/2.5V, ESR=9mohm
1 (G) PC75 SC100P50V2JN-3GP
PC4
SC10U25V5KX-GP
2
NCP81172_COMP11
PC7
SC10U25V5KX-GP
SC22P50V2JN-4GP
1
(G) PR124 82KR2F-1-GP
2
20131209 Madrid SB Charles Muount C6 (1uF) for GPU PWR sequence
1 PR5
C
SCD1U25V3KX-GP
(G) PC77
54
62
S S S
PWR_VGA_CORE_EN
1 PR6
2
(G84.A14DP.037)
SIRA12DP-T1-GE3-GP
2 0R2J-2-GP GPU_THERM_SHUTDOWN*
SIR172ADP-T1-GE3-GP
A
1
C6(G) SC1U10V2KX-1GP
4
G
PWR_VGA_CORE_EN
R6(G)
D D D D
(G) R9 47KR2J-2-GP
S S S
3D3V_VGA_S0
4
S S S
(R) C8 SCD01U25V2KX-L1-GP
(R) R12 15KR2F-GP
SIRA12DP-T1-GE3-GP
PWR_VGA_CORE_PSI
G
R15 0R0402-PAD 2 1
GPIO13_NVVDD_PSI
(G84.010DP.037) PQ3
(G) PTC7
madrid 20131017 Charles power ask to modify as 09.8271N.A5L
330uF/2.5V, ESR=9mohm
(G) PL3
D D D D
54
(G) R11 33KR2F-GP
4
G
3D3V_VGA_S0
PWR_VGA_CORE_UGATE2_R
PU2
(G) PTC6
DCBATOUT_VGA_CORE
D D D D
PR29 0R0402-PAD
4
S S S
SCD1U50V3KX-GP
(G) PC59
G
PWR_VGA_CORE_VREF_2
(G84.A14DP.037) PU1 SIR172ADP-T1-GE3-GP
(G) PC20 SC2700P50V3KX-1GP
B
(G) PC71 SC1500P50V3KX-GP
(G) PC25
(G) R546 21KR2F-GP
D D D D
Put colse to VCORE hot spot
1
.C O
PWR_VGA_CORE_LGATE2
PWR_VGA_CORE_UGATE2_R
(G) PR23 NTC-100K-8-GP
2
0R0805-PAD
VDDC_PWR (G) PR125 2D2R5J-1-GP
2
PWR_VGA_CORE_PHASE2
4
M
2
3 2 1
4
3 2 1
1
(G84.010DP.037) PQ1
1NCP81172_PH1_SB 1
5 6 7 8 2
(G) PR109 2D2R5J-1-GP
(G) PR128 49K9R2F-L-GP
(G) PR28 18KR2F-GP
2
1 5 6 7 8
3 2 1
2
1
(G84.010DP.037) PQ6
3 2 1
NCP81172_TSENSE (G) PC19 SCD1U16V2ZY-2GP
PWR_VGA_CORE_BOOT2
1
2 20KR2F-L-GP
PWR_VGA_CORE_UGATE2
1
(G) PR25 1
NCP81172_FBRTN NCP81172_FB NCP81172_COMP
2
(R) PC24 SC2700P50V3KX-1GP
PWR_VGA_CORE_TON
PWR_VGA_CORE_REFADJ
1 2
2 5K9R3F-3-GP
2
(G) 1 PR22
1
1 2
PWR_VGA_CORE_VREF_1
PWR_VGA_CORE_VREF
(G) PR27 2KR2F-3-GP
10 11 12
NCP81172MNTXG-GP-U (G)
(G) PR131 2D2R5J-1-GP
S S S
C
GPIO11_PWM_VID
PR123 2 0R0402-PAD
FBRTN FB COMP
PWR_VGA_CORE_LGATE1
PWR_VGA_CORE_BOOT2_1
54
1
(G) PC22 SCD1U25V2KX-GP
0R0805-PAD
PWR_VGA_CORE_PHASE1
17 18 19 20
G
2 SC1000P50V3JN-GP-U
VREF REFIN VIDBUF FS
S S S
1
HG2 BST2 PH2 LG2
TSNS
8 7 6 9
G
(R) PC76
13
PWR_VGA_CORE_VREF PWR_VGA_CORE_REFIN
2 20KR2F-L-GP
2
2
1 2
NCP81172_TSENSE (G) PR24 1
1 PR97
VDDC_PWR
E820U2D5VM-7-GP
PR21 2 0R0402-PAD
1 PR96
2
2IND-D36UH-19-GP
E820U2D5VM-7-GP
1 100KR2F-L1-GP
1
(G) PL4 1
SCD1U50V3KX-GP 2
1
SC22U6D3V5MX-2GP
2
2PWR_VGA_CORE_BOOT1_1
SIRA12DP-T1-GE3-GP
GPIO9_ALERT#
1
2
0R0805-PAD
0.36uH, DCR=1.05~1.2mohm, Idc=30A
PWR_VGA_CORE_UGATE1_R
(G) PC61
20131206 Madrid SB Charles Unmount PTC1 ; Add PC105 [Layout] PC105 place back to PC5
(G84.A14DP.037)
2PWR_VGA_CORE_UGATE1_R
(G) PR110 2D2R5J-1-GP
PC6
0R0805-PAD
SE47U25VM-14-GP
(G) PR19
3D3V_VGA_S0
34,54
1
(G) PC53
DCBATOUT_VGA_CORE
DCBATOUT
SC10U25V5KX-GP
PR15 2 0R0402-PAD
PWR_VGA_CORE_BOOT1
(G) PR127 2D2R5J-1-GP
D D D D
1 100KR2F-L1-GP
1
PWR_VGA_CORE_UGATE1
SIRA12DP-T1-GE3-GP
2
22 2 1 24 23
PC5
SC10U25V5KX-GP
(R) PR17
HG1 BST1 PH1 LG1
D D D D
DGPU_PWROK
PGND
EN PSI PGOOD TALERT# VID
(G) PC105
DCBATOUT_VGA_CORE
SC10U25V5KX-GP
3D3V_VGA_S0
54,61
GND
S S S
25
PWR_VGA_CORE_EN 3 PWR_VGA_CORE_PSI 4 PWR_VGA_CORE_PGOOD 16 PWR_VGA_CORE_TALERT 14 PWR_VGA_CORE_VID 5
4
PC10
SC10U25V5KX-GP
4
SIR172ADP-T1-GE3-GP
(G) PC8 SC1U10V3KX-3GP
G
NCP81172_PVCC
D D D D
21
PU10
SIR172ADP-T1-GE3-GP
PVCC
S S S
VCC
G
15
D D D D
PU9 NCP81172_VCC
(G84.A14DP.037) PU3
SCD1U25V3KX-GP
84.SRA12.037 SIRA12DP Vgs @ 4.5V, Id = 20A, Rds(on) = 4.4~6.0mohm,
3 2 1
1
(G) PR9 2D2R5J-1-GP
VIN RIPPLE CURRENT Imax=5.86.A
5 6 7 8
1 2 D
(G) PC73 SC4D7U10V3KX-GP
84.00172.037 SIR172DP Vgs @ 4.5V, Id = 12.9A, Rds(on) = 10.3~12.4mohm,
5V_S0
(G) PR115 2D2R3J-2-GP
2
5V_S0
1 NCP81172_PH2_SB 1
5
Wistron Corporation
VDDC_PWR
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size
GPU PWR_NVVDD(NCP81172)
Document Number
Rev
SA Date: 3
2
Tuesday, January 21, 2014 1
Sheet
60
of
68
5
1D5V_VGA_S0 MAX=6A
3
2
D
GPU VCORE -> MEMORY POWER 1D5V_S3
D D D D
MEMORY DIE_S0 2A
1
(G) Q62 FDMS7698-GP
3 2 1
.C O
2
1D5V_VGA_S0
1
1
1 D S
C25 (G78.10421.2FL) SCD1U25V2KX-GP
20131211 Madrid SB Charles Delete TC1 20131105 Madrid SA unmount to check when SA
AM
1
2
2
1 2 G
B
LA T
S
DGPU_PWROK
1
54,60
2
(G) R25 10KR2J-3-GP
C28
20110228
R30 100KR2J-1-GP (G)
D
2
Q4 2N7002-11-GP (G84.2N702.J31)
R58 100KR2J-1-GP (G)
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
IX W
W
4
W
5
.F
A
C
GPUPG_3
SCD1U25V2KX-GP
3D3V_VGA_S0
R55 (G) 1 2 10KR2J-3-GP
(G78.10421.2FL)
Q7 2N7002-11-GP (G84.2N702.J31) GPUPG_1 G
GPUPG_2
S S S
R32 100KR2J-1-GP (G)
4
G
R33 82K5R2F-GP (G)
2
DCBATOUT
C
M
20131220 Madrid SB Charles Modify Symbol to costdown 84.07698.037
DCBATOUT
B
1
5 6 7 8
D
4
A
Title Size Custom
GPU PWR_1D5V_VGA(51363)
Document Number
Madrid
Date: Tuesday, January 21, 2014 3
2
Rev
SA Sheet 1
61
of
68
3
2
Power Sequencing Requiremen N15S-GT-B-A2 Power-on: 3D3V_VGA_S0-->NVVDD==1D05V_VGA_S0-->1D5V_VGA_S0 Power-off: The timing of all power rail need power down to 0V under 10ms.
1
1.05V to 1.05V_VGA_S0 Transfer FDMS0310, POWER PAK Max Rdson=3.5m ohm at Vgs=10V,21A PCH_1D05V
D
C7
2
IX
.F
1
1
2
5 6 7 8 3 2 1 1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Date: 4
1
2
Wistron Corporation
R65 100KR2J-1-GP (G63.10334.1DL)
Size Custom 5
1
1 D
1D05V_VGA_S0
2
R66 100KR2J-1-GP
(G63.10334.1DL)
2
W
1
1D5V_VGA_S0
A
B
W
C95 (R) SCD22U10V2KX-1GP
W
2
1
3D3V_S0
PWR_VGA_CORE_EN
R131 10KR2F-2-GP 1 23D3V_VGA_S0_EN (R)
20110228
R34 100KR2J-1-GP (G)
Q5
(R78.10421.2FL) SCD1U25V2KX-GP
60
3.3V_RUN_VGA_1
2
1
R26
GPUPG_10 G
C27 (R78.10421.2FL) SCD1U25V2KX-GP
S
0R2J-2-GP
3
2
1
(R75.27002.F7C)
2
84.2N702.A3F 2nd = 84.DM601.03F B
10KR2J-3-GP R903 1 2
R130 200R2F-L-GP
1
(R)
R44 100KR2J-1-GP (G)
C
C29 (R78.10421.2FL) SCD1U25V2KX-GP
1
4
5
Q16 2N7002KDW-GP
6
1
(G)
D
LA T
1 3.3V_ALW_1
Q8 2N7002-11-GP (G84.2N702.J31) GPUPG_11 G
GPUPG_12
3.6A
2
3D3V_VGA_S0
2
G
84.02130.031 2ND = 84.03413.A31
2N7002-11-GP (G84.2N702.J31)
2
Q17 DMP2130L-7-GP
G
(R)
D
(R) R133 100KR2J-1-GP
2
D
R59 (G) 1 2 10KR2J-3-GP
S
S
3D3V_S0
SC4D7U6D3V3KX-GP
M .C O 1
AM
R35 100KR2J-1-GP (G)
S S S
3D3V_VGA_S0
R40 82K5R2F-GP (G)
1D05V_VGA_S0
RUNON_R_2_C
DCBATOUT
0R0603-PAD-2-GP (G) C
4
G
2
D D D D
DCBATOUT
R132
1
(G) FDMS7698-GP
20131220 Madrid SB Charles Modify Symbol to costdown 84.07698.037
+3VS to 3.3V_DELAY Transfer
SCD1U25V2KX-GP (G78.10421.2FL) C30 Q9
2
(G) C31
2
1
D
4
2
5
3
2
GPU PWR_1D05V/3D3V
Document Number
Madrid Tuesday, January 21, 2014
Rev
SA Sheet
62 1
of
68
A
5
4
HS3 STF296R205H152-GP
HS4 STF296R205H152-GP
M
1
1
1
2
4
MINI1 WLAN/BT
VGA
(G) HS5 STF296R205H152-GP
GENS315R158-8-F-A-GP
(G) HS6 STF296R205H152-GP
HS7 STF256R113-UH258-GP
34.3HJ02.001 -> 1.5mm 34.3KF01.001 -> 3.3mm 34.3HJ03.001 -> 6.5mm 34.3KF01.001 for 5.2mm slot 62.10043.G11 34.3HJ03.001 for 9.0mm slot 62.10043.E41
2
4 1
7
LA T
8
SKT1
B
W
2012/09/10_aPisa_SA 2012/09/30_aPisa_SB Modify H4 symbol
Load Plate (22.78005.181)
W 1
FC1 SCD01U25V2KX-3GP (78.10324.2FL)
3D3V_S5
Back Plate (22.78002.011)
1D5V_S3
(R) FC3 SC33P50V2JN-3GP
(R) EC26 SCD1U16V2KX-3GP
2
W 1
DY
FC2 SC47P50V2JN-3GP
2
FC4 SC33P50V2JN-3GP (R)
1
1D5V_S3
2
2
A
1
5V_S0
SKT2
.F
B
C
CPU Plate
IX
GENS315R158-8-F-A-GP
1
6
5
1
3
H5
1
1
C
AM
1
GENS315R158-8-F-A-GP
7
6
8
.C O
1 5
7
8
6
5
2
1
2
H4
3
H3
2
HS2 STF296R205H152-GP
D
GENS315R158-8-F-A-GP
3
HS1 STF296R205H152-GP
8
GENS315R158-8-F-A-GP
4
1
7
6
D
5
6
8
1
7
5
2
CPU
4 1
1
4
2
3
H2
2
3
H1
3
(R) EC24 SCD1U16V2KX-3GP
A
Wistron Corporation
20121007 Charles Marge material
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:
5
4
3
2
STAND OFF/HOLE/EMI CAP
Document Number
Madrid
Tuesday, January 21, 2014
Rev
SA Sheet 1
63
of
68
5
4
3
2
1
Material part
HeatSink+FAN Symbol Vendor P/N:
LGA115x CPU SOCKET Symbol D
SKTY Back Plate (R) SKTX
ILMCOVER
SKTZ
Load Plate (R)
(R)
D
Vendor: LOTES P/N:22.78002.011 Thickness: max 2.2mm (含mylar及及及耐)
Vendor:LOTES P/N:22.78003.011
Vendor:LOTES P/N: 22.78005.171
Vendor: FOXCONN P/N:22.78006.011 Thickness:2.0mm(含mylar)
Vendor:FOXCONN P/N: 22.78005.161
HSFAN1 (R60.3KN01.001)
.C O
M
Vendor:FOXCONN P/N:22.78006.001
SKT4 ILMCOVER (R60.3EE01.001)
AM
C
LABEL
LAN ID : F80F4105EB9A
MB serial NO# and MAC address 45.41101.001 -> 35 x 15mm 45.41107.011 -> 70 x 8mm
LBL2 LABEL (R) LBL3 LABEL (R)
BAT1 BATTERY CR2032_30MM (R23.21221.024)
Wire Length:30mm
B
HeatSink Symbol
Battery Symbol
Vendor P/N: 23.20068.001 23.20023.311 23.22063.001
W
BAT3 BATTERY CR2032 (23.20068.001)
B
Vendor P/N: 23.21221.024 23.21212.031
.F
W
PCHHS1 HEATSINK (60.3MN01.001)
Vendor P/N: Pisa2 60.3ET05.001 60.3ET05.011 60.3ET05.021 Vendor P/N: Madrid 60.3MN01.011(second source) 60.3MN01.001
W
PCH
A
LA T
LAN ID : F80F4105EB9A
LBL1 LABEL (45.41107.011)
Vendor:FOXCONN P/N: 22.78005.161
IX
LAN ID : F80F4105EB9A
C
Vendor:LOTES P/N: 22.78005.171
BAT2 BATTERY BR2032_60MM (R23.24220.612)
Wire Length:60mm 耐耐耐>85C Vendor P/N: 23.21208.061 23.24220.612
PCB Symbol PCB1 PCB (R)
Wistron Incorporated 12F, 88, Hsin Tai Wu Rd Hsichih, Taipei Title Size B Date:
5
4
3
2
HeatSink / Battery cell /etc Document Number
Rev SA
Madrid Tuesday, January 21, 2014
Sheet 1
64
of
68
A
5
4
3
2
1
PU4701
0D75V_EN PM_SLP_S3#
PU4501
1D8V_S0
PU4801
RUNPWROK
1.05VTT_PWRGD
PU4601 D
1D05V_S0
PM_SLP_S4#
0D85V_S0
1D5V_S3 0D75V_EN
Power Sequence
0D85V_S0 1D05V_VTT
D
ALL_POWER_OK
1D5V_S3 0D75V_S0
PCH1
CPU1
PCH
ATXPG ITE8731
SUSB# 3D3V_S0
S0_PWR_GOOD
.C O
U7901
M
PLT_RST#
PM_DRAM_PWRGD
And Gate
SIO can delay:
ALL_POWER_OK
00b
01b
10b
AM
23h
C
H_CPUPWRGD
PU4201
VCC_GFXCORE ALL_POWER_OK SYS_PWROK
IX
H_CPU_SVIDCLK IMVP_PWRGD
B
AND GATE
S0_PWR_GOOD
B
W
W
W
Reserve
.F
VCC_CORE
C
LA T
400ms / 15ms / 200ms
CPU_CORE
H_CPU_SVIDCLK CPU
A
A
Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date: 5
4
3
2
SEQUENCE DIAGRAM
Document Number
Madrid
Tuesday, January 21, 2014
Rev
SA Sheet 1
65
of
68
A
B
PCH SMBus Block Diagram
C
3D3V_S5
3D3V_S0
‧
‧
D
KBC SMBus Block Diagram 5V_S0
3D3V_S0
‧
SRN2K2J-1-GP
SRN2K2J-1-GP
‧ 1
SMBCLK
SMB_CLK
SMBDATA
SMB_DATA
E
‧PCH_SMBCLK ‧ PCH_SMBDATA
‧ ‧
3D3V_S5
DIMM 1
SRN10KJ-5-GP
TouchPad Conn.
SCL SDA
SMBus Address:A0
PSDAT1
TPDATA
PSCLK1
TPCLK
‧ ‧
TPDATA
TPDATA
TPCLK
TPCLK
1
2N7002SPT
3D3V_AUX_KBC
‧ SRN2K2J-8-GP
SML1DATA
SML1_DATA
To KBC & eDP ‧PCH_SMBCLK ‧ PCH_SMBDATA
3D3V_S5 SML0CLK
SML0_CLK
SML0DATA
SML0_DATA
‧
SCL
SRN2K2J-1-GP
GPIO17/SCL1
BAT_SCL
GPIO22/SDA1
BAT_SDA
G-Sensor
XDP
‧
‧PCH_SMBCLK ‧ PCH_SMBDATA
KBC NPCE795
SCLK SDATA
SRN2K2J-1-GP
SDVO_CTRLCLK SDVO_CTRLDATA
Level Shift
PCH_HDMI_CLK PCH_HDMI_DATA
AM
SMBus address:xx
UMA
2
DDC_CLK_HDMI DDC_DATA_HDMI
UMA
‧PCH_SMBCLK ‧ PCH_SMBDATA
3D3V_S0
Minicard WLAN SMB_CLK SMB_DATA
UMA
SRN0J-6-GP PCH_SMBCLK
L_DDC_CLK L_DDC_DATA
LVDS_DDC_CLK_R
PCH_SMBDATA
LVDS_DDC_DATA_R
LA T
‧ SRN2K2J-1-GP
Minicard W-WAN SMB_CLK SMB_DATA
UMA 3D3V_VGA_S0
CRT_DDC_CLK CRT_DDC_DATA
‧ SRN2K2J-1-GP
DDC1CLK
GPU_LVDS_CLK
DDC1DATA
GPU_LVDS_DATA
LVDS_DDC_CLK
CLK
LVDS_DDC_DATA
DATA
VGA_CRT_DDCCLK
DDC2DATA
VGA_CRT_DDCDATA
W
3D3V_S0
VGA
GPIO73/SCL2
SML1_CLK
GPIO74/SDA2
SML1_DATA
SCL SDA
‧
SMBus address:16
BQ24745 SCL SDA
SMBus address:12 LCDVDD_eDP
PCH
2
‧ LCDVDD_eDP SRN2K2J-1-GP
‧
eDP ‧ ‧
LCD_SMBCLK
SCL
LCD_SMBDATA
SDA
SMBus address:XX
2N7002DW-1-GP
‧
W
UMA
5V_S0
3
SRN0J-6-GP
5V_S0
DIS
‧
SRN0J-6-GP
3D3V_VGA_S0
DAT_SMB
LCD CONN
W
DIS DDC2CLK
CLK_SMB
BATA_SDA_1
.F
DIS SRN0J-6-GP
3
BATA_SCL_1
IX
CRT_DDC_CLK CRT_DDC_DATA
Battery Conn.
SRN100J-3-GP
SDA
SMBus Address:A4
3D3V_S0
PCH
SRN4K7J-8-GP
DIMM 2
.C O
SML1_CLK
M
‧ SML1CLK
‧ 3D3V_S0 SRN2K2J-1-GP
UMA
SRN10KJ-6-GP
‧
CRT_DDCCLK_CON CRT_DDCDATA_CON
CRT CONN
UMA 2N7002DW-1-GP
‧
‧ 5V_S0
4
4
SRN1K5J-GP
SRN2K2J-1-GP
DIS DDC2CLK
GPU_HDMI_CLK
DDC2DATA
GPU_HDMI_DATA
DDC_CLK_HDMI
TSCBTD3305CPWR
HDMI CONN
DDC_DATA_HDMI
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
SRN0J-6-GP Title
SMBUS BLOCK DIAGRAM Size A2
DIS A
Date: B
C
D
Document Number
Rev
SA
Madrid
Tuesday, January 21, 2014
Sheet E
66
of
68
A
B
C
D
Thermal Block Diagram
E
Audio Block Diagram
1
1
SPKR_PORT_D_LP2800_DXP SC2200P50V2KX-2GP
UMA Thermal P2800
DXN
P2800_DXN
Codec 92HD79B1
Place near CPU PWM CORE
GPIO5 GPIO92
2
SYS_THRM
TDR
CPU_THRM
TDL
HP1_PORT_B_R
T8
OTZ
THERM_SYS_SHDN#
2N7002
PURE_HW_SHUTDOWN#
EN
D
S
IMVP_PWRGD
G
VGA_THRM
TDR PAGE28 P2800_VGA_DXP
FAN
P2800_VGA_DXN DXN
THRMDC
MMBT3904-3-GP
3
PH
HP0_PORT_A_R VREFOUT_A_OR_F
VGA
Digital MIC
DMIC_CLK/GPIO1 DMIC0/GPIO2
3
W
VIN
OTZ VSET
MIC IN
HP0_PORT_A_L
Place near GPU(DISCRETE only).
VIN
5V
SC2200P50V2KX-2GP
IX
TACH
VGA Thermal P2800
2
THRMDA
SC2200P50V2KX-2GP
.F
FAN1_DAC
FAN_TACH1
DXP
3V/5V
LA T
GPIO4 GPIO56
PGOD
VR
Put under CPU(T8 HW shutdown)
GPIO94
AM
PAGE27
HP OUT
HP1_PORT_B_L
MMBT3904-3-GP
KBC NPCE795P
SPEAKER
SPKR_PORT_D_R+ MMBT3904-3-GP
M
DXP
.C O
PAGE28
VOUT
W
FAN CONTROL
P2793
PORTC_L
Analog MIC
PORTC_R VREFOUT_C
W
PAGE28
4
4
Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Thermal/Audio Block Diagram
Size Custom Date: A
B
C
D
Document Number
Madrid Tuesday, January 21, 2014
Rev
SA Sheet E
67
of
68
5
4
3
2
1
3D3V_S0
D
D
SI4128*1 SI4712*1
3D3V_A Imax=5A
SI4128*1 SI4712*1
5V_CHARGER Imax=9A
3D3V_S5 (EUP)
PWM RT8243B
VCC5_USB
PWM NCP1589A
12V_PWR Imax=3A
+12V_S0 Imax=3A
C
1D5V_S3 Imax=5.5A
LA T
0D75V_S0
AM
PWM RT8207MZQW
B
SIR172A*2 SIRA12 *4
UMA
GPU DDR3 VRAM
5V_S5 (EUP)
V_5_CODEC C
MOS GATE ??
1D5V_S0 Imax=0.3 A
MOS GATE AO4468L
1D5V_VGA_S0 Imax= 2A B
PWM
1D05V_VTT Imax=6A
VCC_CORE TDC= 9A Imax=32A
PWM NCP81172
SIR172A*4 SIRA12 *4
GPU_CORE Imax=40A
Wistron Corporation
4
W
5
W
W
A
.F
IX
PWM ISL95812HRZ
M
ADP_19V
Dual PWM Design
.C O
DC_IN
5V_S0
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Date: 3
2
POWER BLOCK DIAGRAM
Document Number
Rev
SA
Madrid Tuesday, January 21, 2014
Sheet 1
68
of
68
A